1
LTC1658
14-Bit Rail-to-Rail
Micropower DAC in MSOP
FEATURES
s
14-Bit Resolution
s
8-Lead MSOP Package
s
Buffered True Rail-to-Rail Voltage Output
s
3V or 5V Single Supply Operation
s
Very Low Power: I
CC(TYP)
= 270
A
s
Power-On Reset
s
3-Wire Cascadable Serial Interface is Compatible
with SPI and MICROWIRE
TM
s
Maximum DNL Error: 1LSB
s
Low Cost
The LTC
1658 is a single supply, rail-to-rail voltage out-
put, 14-bit digital-to-analog converter (DAC) in an 8-lead
MSOP package. It includes an output buffer amplifier and
an easy-to-use 3-wire cascadable serial interface.
The LTC1658 output swings from 0V to V
REF
. The REF pin
can be tied to V
CC
for rail-to-rail output swing. The LTC1658
operates from a single 2.7V to 5.5V supply. The typical
power supply current is 270
A.
The low power supply current makes the LTC1658 ideal
for battery-powered applications. The space saving MSOP
provides the smallest 14-bit DAC system available.
DESCRIPTIO
N
U
Functional Block Diagram: 14-Bit Rail-to-Rail DAC
s
Digital Calibration
s
Industrial Process Control
s
Automatic Test Equipment
s
Cellular Telephones
APPLICATIO
N
S
U
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
N
U
+
14-BIT
DAC
2.7V TO 5.5V
GND
POWER-ON
RESET
TO
OTHER
DACS
16-BIT
SHIFT
REG
AND
DAC
LATCH
P
D
IN
V
CC
14
REF
2
8
6
D
OUT
4
5
1658 TA01
CLK
1
CS/LD
3
7
RAIL-TO-RAIL
VOLTAGE
OUTPUT
V
OUT
MICROWIRE is a trademark of National Semiconductor Corporation.
CODE
0
1.0
0.2
0.4
0.6
0.8
0
0.2
0.4
0.6
0.8
1.0
DNL ERROR (LSB)
4096
8192
1658 TA02
12288
16383
Differential Nonlinearity
vs Input Code
2
LTC1658
ABSOLUTE
M
AXI
M
U
M
RATINGS
W
W
W
U
V
CC
to GND .............................................. 0.5V to 7.5V
TTL Input Voltage .................................... 0.5V to 7.5V
V
REF
.......................................................... 0.5V to 7.5V
V
OUT
........................................... 0.5V to (V
CC
+ 0.5V)
Junction Temperature .......................... 65
C to 125
C
Operating Temperature Range
Commercial ............................................ 0
C to 70
C
Industrial ............................................. 40
C to 85
C
Storage Temperature Range ................ 65
C to 150
C
Lead Temperature (Soldering, 10 sec)................. 300
C
V
CC
= 2.7V to 5.5V, V
OUT
unloaded, REF
V
CC
, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
ORDER PART
NUMBER
ORDER PART
NUMBER
LTC1658CMS8
LTC1658IMS8
S8 PART MARKING
1658
1658I
LTC1658CN8
LTC1658IN8
LTC1658CS8
LTC1658IS8
Consult factory for Military grade parts.
T
JMAX
= 125
C,
JA
= 100
C/W(N8)
T
JMAX
= 125
C,
JA
= 150
C/W(S8)
1
2
3
4
8
7
6
5
TOP VIEW
CLK
D
IN
CS/LD
D
OUT
V
CC
V
OUT
REF
GND
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 150
C,
JA
= 250
C/W
1
2
3
4
CLK
D
IN
CS/LD
D
OUT
8
7
6
5
V
CC
V
OUT
REF
GND
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
LTCW
LTFW
W
U
U
PACKAGE/ORDER I FOR ATIO
(Note 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC
Resolution
q
14
Bits
Monotonicity
q
14
Bits
DNL
Differential Nonlinearity
V
REF
V
CC
0.1V (Note 2)
q
1.0
LSB
INL
Integral Nonlinearity
V
REF
V
CC
0.1V (Note 2)
q
8.0
LSB
Zero Scale Error
T
A
= 25
C, N8 and S8 Package
1.5
mV
T
A
= T
MIN
to T
MAX
, N8 and S8 Package
q
4.0
mV
T
A
= T
MIN
to T
MAX
, MSOP Package
q
7.0
mV
Offset Error
T
A
= 25
C, N8 and S8 Package, (Note 7)
1.5
mV
T
A
= T
MIN
to T
MAX
, N8 and S8 Package, (Note 7)
q
4.0
mV
T
A
= T
MIN
to T
MAX
, MSOP Package, (Note 7)
q
7.0
mV
V
OS
TC
Offset Error Temperature
5
V/
C
Coefficient
Gain Error
q
20
LSB
Gain Error Drift
2.5
ppm/
C
Power Supply
V
CC
Positive Supply Voltage
For Specified Performance
q
2.7
5.5
V
I
CC
Supply Current
2.7V
V
CC
5.5V (Note 4)
q
270
550
A
Op Amp DC Performance
Short-Circuit Current Low
V
OUT
Shorted to GND
q
55
120
mA
Short-Circuit Current High
V
OUT
Shorted to V
CC
q
55
120
mA
3
LTC1658
V
CC
= 2.7V to 5.5V, V
OUT
unloaded, REF
V
CC
, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance to GND
Input Code = 0
q
70
200
Output Line Regulation
Input Code = 16383, V
CC
= 2.7V to 5.5V, REF = 2.5V
q
1.5
mV/V
AC Performance
Voltage Output Slew Rate
q
0.35
1.0
V/
s
Voltage Output Settling Time
(Note 3) to
0.5LSB
12
s
Digital Feedthrough
0.3
nV s
Reference Input
R
IN
REF Input Resistance
q
30
60
k
V
REF
REF Input Range
(Notes 5, 6)
q
0
V
CC
V
Digital I/O
V
IH
Digital Input High Voltage
V
CC
= 5V
q
2.4
V
V
IL
Digital Input Low Voltage
V
CC
= 5V
q
0.8
V
V
OH
Digital Output High Voltage
V
CC
= 5V, I
OUT
= 1mA, D
OUT
Only
q
V
CC
0.7
V
V
OL
Digital Output Low Voltage
V
CC
= 5V, I
OUT
= 1mA, D
OUT
Only
q
0.4
V
V
IH
Digital Input High Voltage
V
CC
= 3V
q
2.0
V
V
IL
Digital Input Low Voltage
V
CC
= 3V
q
0.6
V
V
OH
Digital Output High Voltage
V
CC
= 3V, I
OUT
= 1mA, D
OUT
Only
q
V
CC
0.7
V
V
OL
Digital Output Low Voltage
V
CC
= 3V, I
OUT
= 1mA, D
OUT
Only
q
0.4
V
I
LEAK
Digital Input Leakage
V
IN
= GND to V
CC
q
10
A
C
IN
Digital Input Capacitance
(Note 6)
q
10
pF
Switching (V
CC
= 4.5V to 5.5V)
t
1
D
IN
Valid to CLK Setup
q
40
ns
t
2
D
IN
Valid to CLK Hold
q
0
ns
t
3
CLK High Time
(Note 6)
q
40
ns
t
4
CLK Low Time
(Note 6)
q
40
ns
t
5
CS/LD Pulse Width
(Note 6)
q
50
ns
t
6
LSB CLK to CS/LD
(Note 6)
q
40
ns
t
7
CS/LD Low to CLK
(Note 6)
q
20
ns
t
8
D
OUT
Output Delay
C
LOAD
= 15pF
q
5
100
ns
t
9
CLK Low to CS/LD Low
(Note 6)
q
20
ns
Switching (V
CC
= 2.7V to 5.5V)
t
1
D
IN
Valid to CLK Setup
q
60
ns
t
2
D
IN
Valid to CLK Hold
q
0
ns
t
3
CLK High Time
(Note 6)
q
60
ns
t
4
CLK Low Time
(Note 6)
q
60
ns
t
5
CS/LD Pulse Width
(Note 6)
q
80
ns
t
6
LSB CLK to CS/LD
(Note 6)
q
60
ns
t
7
CS/LD Low to CLK
(Note 6)
q
30
ns
t
8
D
OUT
Output Delay
C
LOAD
= 15pF
q
10
150
ns
t
9
CLK Low to CS/LD Low
(Note 6)
q
30
ns
4
LTC1658
ELECTRICAL CHARACTERISTICS
The
q
denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
a device may be impaired.
Note 2: Nonlinearity is defined from code 50 to code 16383 (full scale).
See Applications Information.
Note 3: DAC switched between code 16383 and code 50.
Note 4: Digital inputs at 0V or V
CC
.
Note 5: V
OUT
can only swing from (GND +
V
OS
) to (V
CC
V
OS
) when
output is unloaded. See Applications Information.
Note 6: Guaranteed by design. Not subject to test.
Note 7: Measured at code 50.
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Differential Nonlinearity (DNL) vs
Input Code
Supply Current vs Logic Input
Voltage
CODE
0
5
1
2
3
4
0
1
2
3
4
5
INL ERROR (LSB)
4096
8192
1658 G01
12288
16383
Integral Nonlinearity (INL) vs
Input Code
LOGIC INPUT VOLTAGE (V)
0
1
2
3
4
5
SUPPLY CURRENT (mA)
1658 G03
3
2
1
0
ALL DIGITAL INPUTS
TIED TOGETHER
CODE
0
1.0
0.2
0.4
0.6
0.8
0
0.2
0.4
0.6
0.8
1.0
DNL ERROR (LSB)
4096
8192
1658 G02
12288
16383
Minimum Output Voltage vs
Output Sink Current
Offset Error vs Temperature
Minimum Supply Headroom for
Full Output Swing vs Load Current
OUTPUT SINK CURRENT (mA)
0
5
10
15
OUTPUT PULL-DOWN VOLTAGE (V)
1658 G05
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
CODE: ALL ZEROS
125
C
25
C
55
C
LOAD CURRENT (mA)
0
5
10
15
V
CC
V
OUT
(V)
1658 G04
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
OUT
< 1LSB
CODE: ALL 1s
V
OUT
= 4.096V
125
C
25
C
55
C
TEMPERATURE (
C)
55
25
5
35
65
95
125
OFFSET ERROR (LSB)
1658 G06
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5
LTC1658
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Broadband Noise
TEMPERATURE (
C)
55
25
5
35
65
95
125
GAIN ERROR (LSB)
1658 G06
5
4
3
2
1
0
1
2
3
4
5
Gain Error vs Temperature
BW = 1Hz TO
200
s/DIV
1658 G08
100kHz
PI
N
FU
N
CTIO
N
S
U
U
U
CLK (Pin 1): The TTL Level Input for the Serial Interface
Clock.
D
IN
(Pin 2): The TTL Level Input for the Serial Interface
Data. Data on the D
IN
pin is latched into the shift register
on the rising edge of the serial clock and is loaded MSB
first. The LTC1658 requires a 16-bit word to be loaded in.
The last two bits are don't cares.
CS/LD (Pin 3): The TTL Level Input for the Serial Inter-
face Enable and Load Control. When CS/LD is low the
CLK signal is enabled, so the data can be clocked in.
When CS/LD is pulled high, data is loaded from the shift
register into the DAC register, updating the DAC output.
D
OUT
(Pin 4): Output of the Shift Register Which Becomes
Valid on the Rising Edge of the Serial Clock.
GND (Pin 5): Ground.
REF (Pin 6): Reference Input. There is a gain of one from
this pin to the output. When tied to V
CC
the output will
swing from GND to V
CC
. The output can only swing to
within it's offset specification of V
CC
(see Applicatons
Information).
V
OUT
(Pin 7): Buffered Rail-to-Rail DAC Output.
V
CC
(Pin 8): Positive Supply Input. 2.7V
V
CC
5.5V.
1LSB/DIV
6
LTC1658
TI I G DIAGRA
W U
W
B12
B13
MSB
t
1
t
6
t
9
BX
DUMMY
BX
DUMMY
B0
LSB
B11
t
7
t
2
t
4
t
3
t
8
CLK
D
IN
D
OUT
CS/LD
t
5
1658 TD
B13
PREVIOUS WORD
B13
CURRENT WORD
B11
B12
BX
BX
DEFI ITIO S
U
U
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (
V
OUT
LSB)/LSB
Where
V
OUT
is the measured voltage difference between
two adjacent codes.
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
Gain Error: Gain error is the difference between the output
of a DAC from its ideal full-scale value after offset error has
been adjusted.
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code which guarantees the output will be greater
than zero. The INL error at a given input code is calculated
as follows:
INL = [V
OUT
V
OS
(V
FS
V
OS
)(code/16383)]/LSB
Where V
OUT
is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = V
REF
/16384
Resolution (n): Defines the number of DAC output states
(2
n
) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (V
OS
): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
7
LTC1658
OPERATIO
U
Serial Interface
The data on the D
IN
input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded first. The
DAC register loads the data from the shift register when
CS/LD is pulled high. The clock is disabled internally when
CS/LD is high. Note: CLK must be low before CS/LD is
pulled low to avoid an extra internal clock pulse. The input
word must be 16 bits wide. The last two bits are don't
cares.
The buffered output of the 16-bit shift register is available
on the D
OUT
pin which swings from GND to V
CC
.
Multiple LTC1658s may be daisy-chained together by
connecting the D
OUT
pin to the D
IN
pin of the next chip
while the clock and CS/LD signals remain common to all
chips in the daisy chain. The serial data is clocked to all of
the chips then the CS/LD signal is pulled high to update all
of them simultaneously.
Voltage Output
The LTC1658 rail-to-rail buffered output can source or sink
5mA over the entire operating temperature range while
pulling to within 400mV of the positive supply voltage or
ground. The output swings to within a few millivolts of ei-
ther supply rail when unloaded and has an equivalent out-
put resistance of 40
, at 5V V
CC
, when driving a load to the
rails. The output can drive 1000pF without going into os-
cillation.
The output swings from 0V to the voltage at the REF pin,
i.e., there is a gain of 1 from REF to V
OUT
. Please note, if
REF is tied to V
CC
the output can only swing to (V
CC
V
OS
).
See Applications Information.
8
LTC1658
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Similarly, limiting can occur near full scale when the REF
pin is tied to V
CC
. If V
REF
= V
CC
and the DAC full-scale error
(FSE) is positive, the output for the highest codes limits at
V
CC
as shown in Figure 1c. No full-scale limiting can occur
if V
REF
is less than V
CC
FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V
REF
= V
CC
1658 F01
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
8192
0
16383
INPUT CODE
OUTPUT
VOLTAGE
(a)
V
REF
= V
CC
V
REF
= V
CC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
9
LTC1658
An Optoisolated 4mA to 20mA Process Controller
CLK
D
IN
CS/LD
1
F
IN
OUT
Q1
2N3440
R
S
10
I
OUT
V
LOOP
3.8V TO 30V
V
CC
REF
V
OUT
FROM
OPTO-
ISOLATED
INPUTS
LTC1658
1658 TA04
LT
1121-3.3
3.01k
1%
+
+
LT1077
1k
20k
237k
1%
5k
60.4k
1%
OPTOISOLATORS
500
3.3V
3.6k
4N28
CLK
D
IN
CS/LD
CLK
D
IN
CS/LD
This circuit shows how to use an LTC1658 to make an
optoisolated digitally controlled 4mA to 20mA process
controller. The controller circuitry, including the
optoisolation, is powered by the loop voltage that can have
a wide range of 3.8V to 30V. The 3.3V output of the
LT1121-3.3 is used for the 4mA offset current and V
OUT
is
used for the digitally controlled 0mA to 16mA current. R
S
is a sense resistor and the op amp modulates the transis-
tor Q1 to provide the 4mA to 20mA current through this
resistor. The potentiometers allow for offset and full-scale
adjustment. The control circuitry dissipates well under the
4mA budget at zero-scale.
TYPICAL APPLICATIO S
U
10
LTC1658
A 14-Bit Analog Input/Output Channel for a PC
D
OUT
10
11
1
2
3
4
8
7
6
5
V
CC
V
OUT
REF
GND
CLK
D
IN
CS/LD
D
OUT
U2
LTC1658
ANALOG
OUTPUT
2
4
3
5
1
6
Q
CLR
Q
D
PR
CK
U3
1/2 74HC74
5V
5V
3
SELECT
TX
RTS
DTR
CTS
4
1
2
6
2
4
U4
LT1021-5
12
10
11
9
13
8
Q
CLR
Q
D
PR
CK
U3
1/2 74HC74
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
V
SS
BUSY
CONVST
RD
SHDN
DGND
D
OUT
A
IN
+
A
IN
V
REF
V
REFCOMP
AGND
EXTCLKIN
SCLK
CLKOUT
U1
LTC1417
510
510
510
510
10
F
1
F
1
F
D1
DIFFERENTIAL
INPUT
D2
D6
D5
D3
D4
1
F
51k
9
D
IN
8
5
6
51k
SCLK
13
12
51k
C4
150
F
C3
0.1
F
5V
C5
47
F
1658 TA05
1658 TA05
5V
TYPICAL APPLICATIO S
U
11
LTC1658
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
N
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1
2
3
4
0.150 0.157**
(3.810 3.988)
8
7
6
5
0.189 0.197*
(4.801 5.004)
0.228 0.244
(5.791 6.197)
0.016 0.050
0.406 1.270
0.010 0.020
(0.254 0.508)
45
0
8
TYP
0.008 0.010
(0.203 0.254)
SO8 0996
0.053 0.069
(1.346 1.752)
0.014 0.019
(0.355 0.483)
0.004 0.010
(0.101 0.254)
0.050
(1.270)
TYP
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
N8 1197
0.100
0.010
(2.540
0.254)
0.065
(1.651)
TYP
0.045 0.065
(1.143 1.651)
0.130
0.005
(3.302
0.127)
0.020
(0.508)
MIN
0.018
0.003
(0.457
0.076)
0.125
(3.175)
MIN
1
2
3
4
8
7
6
5
0.255
0.015*
(6.477
0.381)
0.400*
(10.160)
MAX
0.009 0.015
(0.229 0.381)
0.300 0.325
(7.620 8.255)
0.325
+0.035
0.015
+0.889
0.381
8.255
(
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
MSOP (MS8) 1197
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
0.021
0.006
(0.53
0.015)
0
6
TYP
SEATING
PLANE
0.007
(0.18)
0.040
0.006
(1.02
0.15)
0.012
(0.30)
REF
0.006
0.004
(0.15
0.102)
0.034
0.004
(0.86
0.102)
0.0256
(0.65)
TYP
1
2
3
4
0.192
0.004
(4.88
0.10)
8
7 6
5
0.118
0.004*
(3.00
0.102)
0.118
0.004**
(3.00
0.102)
12
LTC1658
LINEAR TECHNOLOGY CORPORATION 1998
1658f LT/TP 0299 4K PRINTED IN USA
TYPICAL APPLICATIO
N
U
14-Bit, 3V to 5V Single Supply, Voltage Output DAC
D
IN
CLK
CS/LD
D
OUT
P
0.1
F
OUTPUT
0V TO REF
V
CC
REF
V
OUT
GND
LTC1658
TO NEXT DAC FOR
DAISY-CHAINING
2.7V TO 5.5V
1658 TA03
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear-tech.com
PART NUMBER
DESCRIPTION
COMMENTS
LTC1257
Single 12-Bit V
OUT
DAC, Full Scale: 2.048V, V
CC
: 4.75V to 15.75V,
5V to 15V Single Supply, Complete V
OUT
DAC in
Reference Can Be Overdriven Up to 12V, i.e., FS
MAX
= 12V
SO-8 Package
LTC1446/LTC1446L
Dual 12-Bit V
OUT
DACs in SO-8 Package
LTC1446: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1446L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1448
Dual 12-Bit V
OUT
DAC, V
CC
: 2.7V to 5.5V
Output Swings from GND to REF. REF Input
Can Be Tied to V
CC
LTC1450/LTC1450L
Single 12-Bit V
OUT
DACs with Parallel Interface
LTC1450: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1450L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1451
Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, V
CC
: 4.5V to 5.5V,
5V, Low Power Complete V
OUT
DAC in SO-8 Package
Internal 2.048V Reference Brought Out to Pin
LTC1452
Single Rail-to-Rail 12-Bit V
OUT
Multiplying DAC, V
CC
: 2.7V to 5.5V
Low Power, Multiplying V
OUT
DAC with Rail-to-Rail
Buffer Amplifier in SO-8 Package
LTC1453
Single Rail-to-Rail 12-Bit V
OUT
DAC, Full Scale: 2.5V, V
CC
: 2.7V to 5.5V
3V, Low Power, Complete V
OUT
DAC in SO-8 Package
LTC1454/LTC1454L
Dual 12-Bit V
OUT
DACs in SO-16 Package with Added Functionality
LTC1454: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1454L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1456
Single Rail-to-Rail Output 12-Bit DAC with Clear Pin,
Low Power, Complete V
OUT
DAC in SO-8
Full Scale: 4.095V, V
CC
: 4.5V to 5.5V
Package with Clear Pin
LTC1458/LTC1458L
Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: V
CC
= 4.5V to 5.5V, V
OUT
= 0V to 4.095V
LTC1458L: V
CC
= 2.7V to 5.5V, V
OUT
= 0V to 2.5V
LTC1659
Single Rail-to-Rail 12-Bit V
OUT
DAC in 8-Pin MSOP, V
CC
: 2.7V to 5.5V
Low Power, Multiplying V
OUT
DAC in MS8 Package.
Output Swings from GND to REF. REF Input Can Be
Tied to V
CC
.
References
LT1019
Precision Voltage Reference
Ultralow Drift 5ppm/
C, Initial Accuracy: 0.05%
LT1634
Micropower Precision Reference
Low Drift 10ppm/
C, Initial Accuracy: 0.05%
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