LTC1664

Micropower Quad

10-Bit DAC

January 2000

The LTC

1664 integrates four accurate, serially addres-

sable 10-bit digital-to-analog converters (DACs) in a tiny
16-pin Narrow SSOP package. Each buffered DAC draws
just 59

A total supply current, yet is capable of supplying

DC output currents in excess of 5mA and reliably driving
capacitive loads of up to 1000pF. Sleep mode further
reduces total supply current to 1

Linear Technology's proprietary, inherently monotonic
voltage interpolation architecture provides excellent lin-
earity while allowing for an exceptionally small external
form factor.

Ultralow supply current, power-saving Sleep mode and
extremely compact size make the LTC1664 ideal for
battery-powered applications, while its ease of use, high
performance and wide supply range make it an excellent
choice as a general purpose converter.

Tiny: 4 DACs in the Board Space of an SO-8

Micropower: 59

A per DAC Plus

A Sleep Mode for Extended Battery Life

Wide 2.7V to 5.5V Supply Range

Rail-to-Rail Voltage Outputs Drive 1000pF

Reference Range Includes Supply for Ratiometric
0V-to-V

Output

Reference Input Has Constant Impedance over All
Codes--Eliminates External Reference Buffer

Individually Addressable DACs

Differential Nonlinearity:

0.75LSB Max

Pin-Compatible Octal Version Available (LTC1660)

Mobile Communications

Remote Industrial Devices

Automatic Calibration for Manufacturing

Portable Battery-Powered Instruments

Trim/Adjust Applications

GND

OUT A

OUT B

REF

CS/LD

SCK

OUT D

OUT C

CLR

OUT

1664 BD

10-BIT

DAC A

10-BIT

DAC D

10-BIT

DAC B

10-BIT

DAC C

ADDRESS
DECODER

CONTROL

LOGIC

SHIFT REGISTER

CODE

256

512

768

1023

LSB

1664 G08

0.8

0.6

0.4

0.2

0.4

0.6

0.8

= 5V

REF

= 4.096V

LTC1664 Differential Nonlinearity (DNL)

, LTC and LT are registered trademarks of Linear Technology Corporation.

Final Electrical Specifications

APPLICATIO S

FEATURES

DESCRIPTIO

BLOCK DIAGRA

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1664

BSOLUTE

ORDER PART

NUMBER

PACKAGE/ORDER I FOR ATIO

JMAX

= 125

= 150

C/W (GN)

JMAX

= 125

= 100

C/W (N)

Consult factory for Military grade parts.

(Note 1)

to GND .............................................. 0.2V to 7.5V

Logic Inputs to GND ................................ 0.2V to 7.5V
V

OUT A

, V

OUT B

...V

OUT D

REF to GND ................................. 0.2V to (V

+ 0.2V)

Maximum Junction Temperature ......................... 125

Operating Temperature Range

LTC1664C ............................................. 0

C to 70

LTC1664I ........................................... 40

C to 85

Storage Temperature Range ................ 65

C to 150

Lead Temperature (Soldering, 10 sec)................ 300

LTC1664CGN
LTC1664CN
LTC1664IGN
LTC1664IN

GN PART MARKING

1664
1664I

TOP VIEW

GN PACKAGE

16-LEAD PLASTIC SSOP

N PACKAGE

16-LEAD PDIP

GND

OUT A

OUT B

OUT C

OUT D

REF

CS/LD

SCK

CLR

OUT

ELECTRICAL C

HARA TERISTICS

The

denotes specifications which apply over the full operating temperature range, otherwise specifications

are at T

= 25

C. V

= 2.7V to 5.5V, V

REF

, V

OUT

unloaded, unless otherwise noted.

SYMBOL

PARAMETER

CONDITONS

MIN

TYP

MAX

UNITS

Accuracy

Resolution

Bits

Monotonicity

REF

0.1V (Note 2, 4)

Bits

DNL

Differential Nonlinearity

REF

0.1V (Note 2, 4)

0.2

0.75

LSB

INL

Integral Nonlinearity

REF

0.1V (Note 2, 4)

0.6

2.5

LSB

Offset Error

(Note 7)

Temperature Coefficient

FSE

Full-Scale Error

= 5V, V

REF

= 4.096V (Note 4)

LSB

Full-Scale Error Temperature Coefficient

PSR

Power Supply Rejection

REF

= 2.5V

0.18

LSB/V

Reference Input

Input Voltage Range

Resistance

Not in Sleep Mode

130

Capacitance

(Note 6)

REF

Reference Current

Sleep Mode

0.001

Power Supply

Positive Supply Voltage

For Specified Performance

2.7

5.5

Supply Current

= 5V (Note 3)

236

380

= 3V (Note 3)

186

290

Sleep Mode (Note 3)

LTC1664

ELECTRICAL C

HARA TERISTICS

TI I G CHARACTERISTICS

The

denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T

= 25

C. (See Figure 1)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

The

denotes specifications which apply over the full operating temperature range, otherwise specifications

are at T

= 25

C. V

= 2.7V to 5.5V, V

REF

, V

OUT

unloaded, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

= 4.5V to 5.5V

Valid to SCK Setup

Valid to SCK Hold

SCK High Time

(Note 6)

SCK Low Time

(Note 6)

CS/LD Pulse Width

(Note 6)

LSB SCK High to CS/LD High

(Note 6)

CS/LD Low to SCK High

(Note 6)

OUT

Propagation Delay

LOAD

= 15pF (Note 6)

SCK Low to CS/LD Low

(Note 6)

CLR Pulse Width

(Note 6)

100

CS/LD High to SCK Positive Edge

(Note 6)

SCK Frequency

Continuous Square Wave (Note 6)

5.00

MHz

Continuous 23% Duty Cycle Pulse (Note 6)

7.69

MHz

Gated Square Wave (Note 6)

16.7

MHz

= 2.7V to 5.5V

Valid to SCK Setup

(Note 6)

Valid to SCK Hold

(Note 6)

SCK High Time

(Note 6)

SCK Low Time

(Note 6)

CS/LD Pulse Width

(Note 6)

100

DC Performance

Short-Circuit Current Low

OUT

= 0V, V

= 5.5V, V

REF

= 5.1V,

100

Code = Full Scale (Note 4)

Short-Circuit Current High

OUT

= V

= 5.5V, V

REF

= 5.1V, Code = 0 (Note 4)

120

AC Performance

Voltage Output Slew Rate

Rising (Notes 4, 5)

0.60

Falling (Notes 4, 5)

0.25

Voltage Output Settling Time

0.5LSB (Notes 4, 5)

Capacitive Load Driving

1000

Digital I/O

Digital Input High Voltage

= 2.7V to 5.5V

2.4

= 2.7V to 3.6V

2.0

Digital Input Low Voltage

= 4.5V to 5.5V

0.8

= 2.7V to 5.5V

0.6

Digital Output High Voltage

OUT

= 1mA, D

OUT

Only

Digital Output Low Voltage

OUT

= 1mA, D

OUT

Only

0.4

Digital Input Leakage

= GND to V

Digital Input Capacitance

(Note 6)

LTC1664

Supply Current vs Temperature

TEMPERATURE (

55 35 15

85 105 125

SUPPLY CURRENT (

1664 G06

250

240

230

220

210

200

190

180

170

160

150

= 5.5V

= 4.5V

= 3.6V

= 2.7V

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

LSB SCK High to CS/LD High

(Note 6)

CS/LD Low to SCK High

(Note 6)

100

OUT

Propagation Delay

LOAD

= 15pF (Note 6)

150

SCK Low to CS/LD Low

(Note 6)

CLR Pulse Width

(Note 6)

120

CS/LD High to SCK Positive Edge

(Note 6)

SCK Frequency

Continuous Square Wave (Note 6)

3.85

MHz

Continuous 28% Duty Cycle Pulse

5.55

MHz

Gated Square Wave

MHz

TYPICAL PERFOR A CE CHARACTERISTICS

TI I G CHARACTERISTICS

The

denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T

= 25

C. (See Figure 1)

Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.

Note 2: Nonlinearity and monotonicity are defined from code 20 to code
1023. See Applications Information.

Note 3: Digital inputs at 0V or V

Note 4: Load is 10k

in parallel with 100pF.

Note 5: V

= V

REF

= 5V. DAC switched between 0.1V

and 0.9V

i.e., codes 102 and 922.

Note 6: Guaranteed by design and not subject to test.

Note 7: Measured at code 20.

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

CODE

256

512

768

1023

LSB

1664 G07

2.5

2.0

1.5

1.0

0.5

1.0

1.5

2.0

2.5

= 5V

REF

= 4.096V

CODE

256

512

768

1023

LSB

1664 G08

0.8

0.6

0.4

0.2

0.4

0.6

0.8

= 5V

REF

= 4.096V

LTC1664

TYPICAL PERFOR A CE CHARACTERISTICS

Large-Signal Step Response

TIME (

100

OUT

(V)

1664 G05

10% TO
90% STEP

= V

REF

= 5V

OUT

(mV)

1664 G03

1400

1200

1000

800

600

400

200

125

REF

= 4.096V

OUT

< 1LSB

CODE = 1023

OUT

(mA) (Sourcing)

Minimum V

OUT

Load Current (Output Sinking)

OUT

(mA) (Sinking)

OUT

(mV)

1664 G04

1400

1200

1000

800

600

400

200

125

= 5V

CODE = 0

OUT

(mA)

OUT

(V)

1664 G01

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

= 4.5V

= 5V

= 5.5V

REF

= V

CODE = 512

SINK

SOURCE

OUT

(mA)

12 15

OUT

(V)

1664 G02

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

= 2.7V

= 3V

= 3.6V

REF

= V

CODE = 512

SINK

SOURCE

Load Regulation vs Output Current

OUT

(mA)

OUT

(LSB)

1.5

0.5

1.5

1664 G09

= V

REF

= 5V

CODE = 512

SINK

SOURCE

OUT

(

500

OUT

(LSB)

1.5

0.5

1.5

1664 G10

SINK

SOURCE

= V

REF

= 3V

CODE = 512

Minimum Supply Headroom vs
Load Current (Output Sourcing)

Midscale Output Voltage
vs Load Current

LTC1664

CTIO

GND (Pin 1): System Ground.

OUT A

to V

OUT D

(Pins 25): DAC Analog Voltage Outputs.

The output range is

1023
1024

REF

REF (Pin 6): Reference Voltage Input. 0V

REF

CS/LD (Pin 7): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on D

into the register. When CS/LD is pulled high, SCK is
disabled and data is loaded from the shift register into the
specified DAC register(s), updating the analog output(s).
CMOS and TTL compatible.

SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL
compatible.

(Pin 9): Serial Interface Data Input. Data on the D

is shifted into the 16-bit register on the rising edge of SCK.
CMOS and TTL compatible.

OUT

(Pin 10): Serial Interface Data Output. Data appears

on D

OUT

16 positive SCK edges after being applied to D

May be tied to D

of another serial device for daisy-chain

operaton. CMOS and TTL compatible.

CLR (Pin 11): Asynchronous Clear Input. All internal shift
and DAC registers are cleared to zero at the falling edge of
the CLR signal, forcing the analog outputs to zero scale.
CMOS and TTL compatible.

NC (Pins 1215): Make no electrical connection to these
pins.

(Pin 16): Supply Voltage Input. 2.7V

5.5V.

LTC1664

A3 A2 A1

Address/Control

A0 D9 D8 D7 D6 D5 D4 D3 D2 D1

X1 X0

Input Code

Don't

Care

Table 1. LTC1664 Input Word

OPERATIO

Transfer Function

The transfer function is

OUT IDEAL

REF

(

)

1024

where k is the decimal equivalent of the binary DAC input
code and V

REF

is the voltage at REF (Pin 6).

Power-On Reset

The LTC1664 clears the outputs to zero scale when power
is first applied, making system initialization consistent and
repeatable.

Power Supply Sequencing

The voltage at REF (Pin 6) should be kept within the range
0.2V

REF

+ 0.2V (see Absolute Maximum

Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V

(Pin 16) is in transition.

Serial Interface

Referring to Figure 2: With CS/LD held low, data on the D

input is shifted into the 16-bit shift register on the positive
edge of SCK. The 4-bit DAC address, A3-A0, is loaded first
(see Table 2), then the 10-bit input code, D9-D0, ordered
MSB-to-LSB in each case. Two don't-care bits, X1-X0, are
loaded last. When the full 16-bit input word has been
shifted in, CS/LD is pulled high, loading the DAC register
with the word and causing the addressed DAC output(s)
to update. The clock is disabled internally when CS/LD is
high. Note: SCK must be low before CS/LD is pulled low.

The buffered serial output of the shift register is available
on the D

OUT

pin, which swings from GND to V

. Data

appears on D

OUT

16 positive SCK edges after being applied

to D

Multiple LTC1664's can be controlled from a single 3-wire
serial port (i.e., SCK, D

and CS/LD) by using the included

"daisy-chain" facility. A series of

m chips is configured by

connecting each D

OUT

(except the last) to D

of the next

chip, forming a single 16

m-bit shift register. The SCK and

CS/LD signals are common to all chips in the chain. In use,
CS/LD is held low while

m 16-bit words are clocked to D

of the first chip; CS/LD is then pulled high, updating all of
them simultaneously.

Sleep Mode

DAC address 1110

is reserved for the special Sleep

instruction (see Table 2). In this mode, the digital interface
stays active while the analog circuits are disabled; static
power consumption is thus virtually eliminated. The refer-
ence input and analog outputs are set in a high impedance
state and all DAC settings are retained in memory so that
when Sleep mode is exited, the outputs of DACs not
updated by the Wake command are restored to their last
active state.

Sleep mode is initiated by performing a load sequence to
address 1110

(the DAC input word D9-D0 is ignored).

Once in Sleep mode, a load sequence to any other address
(including "No Change" addresses 0000

and 1001-1101

)

causes the LTC1664 to Wake. It is possible to keep one or
more chips of a daisy chain in continuous Sleep mode by
giving the Sleep instruction to these chips each time the
active chips in the chain are updated.

LTC1664

OPERATIO

Table 2. DAC Address/Control Functions

ADDRESS/CONTROL

DAC STATUS

SLEEP STATUS

No Change

Wake

Load DAC A

Wake

Load DAC B

Wake

Load DAC C

Wake

Load DAC D

Wake

Reserved

No Change

Sleep

Load

ALL DACs

Wake

with Same

10-Bit Code

OUT

SCK

CS/LD

INPUT WORD W

INPUT CODE

DON'T CARE

1664 F02

(ENABLE SCK)

(UPDATE OUTPUT)

ADDRESS/CONTROL

INPUT WORD W

Figure 2. LTC1664 Register Loading Sequence

LTC1664

Voltage Outputs

Each of the four rail-to-rail output amplifiers contained in
these parts can source or sink up to 5mA. The outputs
swing to within a few millivolts of either supply rail when
unloaded and have an equivalent output resistance of 85

when driving a load to the rails. The output amplifiers are
stable driving capacitive loads up to 1000pF.

A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. A 1

load can be successfully driven by inserting a 20

resis-

tor; a 2.2

F load needs only a 10

resistor. In either case,

larger values of resistance, capacitance or both may be
safely substituted for the values given.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output DAC, the output is limited
to voltages within the supply range.

If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 3b.

Similarly, limiting can occur near full scale when the REF
pin is tied to V

. If V

REF

= V

and the DAC full-scale error

(FSE) is positive, the output for the highest codes limits at
V

as shown in Figure 3c. No full-scale limiting can occur

if V

REF

is less than V

FSE.

Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.

OPERATIO

LTC1664

A Low Power Dual Trim Circuit with Coarse/Fine Adjustment

OUT2

OUT1

COARSE

0.1

3.3V

COARSE

FINE

1664 TA01

GND

OUT A

OUT B

REF

CS/LD

SCK

3-WIRE

SERIAL

INTERFACE

OUT D

OUT C

CLR

TO OTHER
LTC1664s

OUT

DAC A

DAC D

DAC B

DAC C

ADDRESS
DECODER

CONTROL

LOGIC

SHIFT REGISTER

0.1

3.3V

LTC1664

U2A

1490

LTC1258-2.5

0.1

U2B

LT1490

R2 >> R1
V

OUT 1

= V

OUT A

Example: For R1 = 110

and R2 = 11k,

OUT 1

= V

OUT A

+ 0.01 V

OUT B

))

R1
R2

OUT B

Similarly V

OUT 2

TYPICAL APPLICATIO

LTC1664

TYPICAL APPLICATIO

A 4-Channel Bipolar Output Voltage Circuit Configuration

1664 TA02

GND

OUT A

OUT B

REF

CS/LD

CLK

3-WIRE

SERIAL

INTERFACE

OUT D

OUT C

CLR

OUT

DAC A

DAC D

DAC B

DAC C

ADDRESS
DECODER

CONTROL

LOGIC

SHIFT REGISTER

LTC1664

OUT B

U2B

LT1491

OUT A

0.1

U2A

LT1491

0.1

OUT C

U2C

LT1491

OUT D

U2D

LT1491

CODE

512

1023

OUT X

+4.99V

LTC1664

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

GN Package

16-Lead Plastic SSOP (Narrow 0.150)

(LTC DWG # 05-08-1641)

GN16 (SSOP) 1098

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0.229 0.244

(5.817 6.198)

0.150 0.157**

(3.810 3.988)

16 15 14 13

0.189 0.196*

(4.801 4.978)

12 11 10 9

0.016 0.050

(0.406 1.270)

0.015

0.004

(0.38

0.10)

TYP

0.007 0.0098

(0.178 0.249)

0.053 0.068

(1.351 1.727)

0.008 0.012

(0.203 0.305)

0.004 0.0098

(0.102 0.249)

0.0250

(0.635)

BSC

0.009

(0.229)

REF

LTC1664

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

N Package

16-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

N16 1098

0.255

0.015*

(6.477

0.381)

0.770*

(19.558)

MAX

0.020

(0.508)

MIN

0.125

(3.175)

MIN

0.130

0.005

(3.302

0.127)

0.065

(1.651)

TYP

0.045 0.065

(1.143 1.651)

0.018

0.003

(0.457

0.076)

0.100

(2.54)

BSC

0.009 0.015

(0.229 0.381)

0.300 0.325

(7.620 8.255)

0.325

+0.035
0.015

+0.889
0.381

8.255

(

)

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

LTC1664

LINEAR TECHNOLOGY CORPORATION 2000

1664i LT/TP 0100 4K · PRINTED IN THE USA

TYPICAL APPLICATIO

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear-tech.com

PART NUMBER

DESCRIPTION

COMMENTS

LTC1665/LTC1660

Octal 8/10-Bit V

OUT

DAC in 16-Pin Narrow SSOP

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

LTC1661

Dual 10-Bit V

OUT

DAC in 8-Lead MSOP Package

= 2.7V to 5.5V Micropower, Rail-to-Rail Output

LTC1663

Single 10-Bit V

OUT

DAC with 2-Wire Interface in SOT-23 Package

= 2.7V to 5.5V, Internal Reference, 60

LTC1446/LTC1446L

Dual 12-Bit V

OUT

DACs in SO-8 Package with Internal Reference

LTC1446: V

= 4.5V to 5.5V, V

OUT

= 0V to 4.095V

LTC1446L: V

= 2.7V to 5.5V, V

OUT

= 0V to 2.5V

LTC1448

Dual 12-Bit V

OUT

DAC in SO-8 Package

= 2.7V to 5.5V, External Reference Can Be Tied to V

LTC1454/LTC1454L

Dual 12-Bit V

OUT

DACs in SO-16 Package with Added Functionality

LTC1454: V

= 4.5V to 5.5V, V

OUT

= 0V to 4.095V

LTC1454L: V

= 2.7V to 5.5V, V

OUT

= 0V to 2.5V

LTC1458/LTC1458L

Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality

LTC1458: V

= 4.5V to 5.5V, V

OUT

= 0V to 4.095V

LTC1458L: V

= 2.7V to 5.5V, V

OUT

= 0V to 2.5V

LTC1590

Dual 12-Bit I

OUT

DAC in SO-16 Package

= 4.5V to 5.5V, 4-Quadrant Multiplication

LTC1659

Single Rail-to-Rail 12-Bit V

OUT

DAC in 8-Lead MSOP Package

Low Power Multiplying V

OUT

DAC. Output Swings from

: 2.7V to 5.5V

GND to REF. REF Input Can Be Tied to V

LT1460

Micropower Precision Series Reference, 2.5V, 5V, 10V Versions

0.075% Max, 10ppm/

C Max, Only 130

A Supply Current

RELATED PARTS

A Pin Driver V

and V

Adjustment Circuit for ATE Applications

DAC A

CLR

REF

U1 LTC1664

0.1

= V

(FROM MAIN DAC)

10V

50k

GND

1664 TA03

DAC B

0.1

50k

U2A

LT1368

0.1

LOGIC
DRIVE

PIN
DRIVER

DAC C

DAC D

CS/LD

SCK

U2B

LT1368

OUT

CODE A

512
512
512

CODE B

1023

512

250mV

+ 250mV

= V

= 2.5V

For Resistor Values Shown:
Adjustment Range =

250mV

Adjustment Step Size = 500

= V

)

= V

)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC1664C

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC1664C