1
LTC1669
1669f
10-Bit Rail-to-Rail
Micropower DAC with I
2
C Interface
The LTC
1669 is a 10-bit voltage output DAC with true
buffered rail-to-rail output voltage capability. It operates
from a single supply with a range of 2.7V to 5.5V. The
reference for the DAC is selectable between the supply
voltage or an internal bandgap reference. Selecting the
internal bandgap reference will set the full-scale output
voltage range to 2.5V. Selecting the supply as the refer-
ence sets the output voltage range to the supply voltage.
The part features a simple 2-wire serial interface compat-
ible with I
2
C that allows communication between many
devices. The internal data registers are double buffered to
allow for simultaneous update of several devices at once.
The DAC can be put in low current power-down mode for
use in power conscious systems.
Power-on reset ensures the DAC output is at 0V when
power is initially applied, and all internal registers are
cleared. The LTC1669 is pin-for-pin compatible with the
LTC1663.
s
Micropower 10-Bit DAC in SOT-23
s
Low Operating Current: 60
A
s
Ultralow Power Shutdown Mode: 12
A
s
2-Wire Serial Interface Compatible
with I
2
C
TM
s
Selectable Internal Reference or Ratiometric to V
CC
s
Maximum DNL Error: 0.75LSB
s
8 User Selectable Addresses (MSOP Package)
s
Single 2.7V to 5.5V Operation
s
Buffered True Rail-to-Rail Voltage Output
s
Power-On Reset
s
1.5V V
IL
and 2.1V V
IH
for SDA and SCL
s
Small 5-Lead SOT-23 and 8-Lead MSOP Packages
s
Digital Calibration
s
Offset/Gain Adjustment
s
Industrial Process Control
s
Automatic Test Equipment
s
Arbitrary Function Generators
s
Battery-Powered Data Conversion Products
, LTC and LT are registered trademarks of Linear Technology Corporation.
10-BIT
DAC LATCH
INPUT
LATCH
2-WIRE INTERFACE
SDA
AD0
(6)
MSOP
PACKAGE
ONLY
(2)
(3)
AD1
AD2
SCL
1 (1)
5 (4)
GND
2 (7)
V
OUT
3 (8)
1669 BD
V
CC
1.25V
4 (5)
BANDGAP
REFERENCE
REFERENCE
SELECT
COMMAND
LATCH
NOTE: PIN NUMBERS IN PARENTHESES REFER TO THE MSOP PACKAGE
10-BIT BUFFERED V
OUT
DAC
I
2
C is a trademark of Philips Electronics N.V.
Differential Nonlinearity (DNL)
CODE
0
1.0
ERROR (LSB)
0.8
0.4
0.2
0
1.0
0.4
156
512
640
1669 G02
0.6
0.6
0.8
0.2
28
384
768 896 1024
V
REF
= V
CC
= 5V
T
A
= 25
C
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
BLOCK DIAGRA
W
2
LTC1669
1669f
ORDER PART
NUMBER
A
U
G
W
A
W
U
W
A
R
BSOLUTE
XI
TI
S
W
U
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
T
JMAX
= 125
C,
JA
= 150
C/W
1
2
3
4
SDA
AD1
AD2
SCL
8
7
6
5
V
OUT
GND
AD0
V
CC
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
LTC1669CMS8
LTC1669IMS8
V
CC
to GND .............................................. 0.3V to 7.5V
SDA, SCL .................................................. 0.3V to 7.5V
AD0, AD1, AD2 (MSOP Only) ...... 0.3V to (V
CC
+ 0.3V)
V
OUT
............................................ 0.3V to (V
CC
+ 0.3V)
Operating Temperature Range
LTC1669C .............................................. 0
C to 70
C
LTC1669I ........................................... 40
C to 85
C
Storage Temperature Range ................ 65
C to 150
C
Lead Temperature (Soldering, 10 sec)................. 300
C
S5 PART MARKING
LTC1669CS5
LTC1669-1CS5
ELECTRICAL C
C
HARA TERISTICS
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
CC
= 2.7V to 5.5V, V
CC
set as reference, V
OUT
unloaded,
unless otherwise noted.
(Note 1)
SDA 1
GND 2
TOP VIEW
S5 PACKAGE
5-LEAD PLASTIC SOT-23
V
OUT
3
5 SCL
4 V
CC
T
JMAX
= 125
C,
JA
= 250
C/W
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC
Resolution
q
10
Bits
Monotonicity
(Note 2)
q
10
Bits
DNL
Differential Nonlinearity
Guaranteed Monotonic (Note 2)
q
0.2
0.75
LSB
INL
Integral Nonlinearity
(Note 2)
q
0.5
2.5
LSB
V
OS
Offset Error
Measured at Code 20
q
10
30
mV
V
OSTC
Offset Error Temperature Coefficient
15
V/
C
FSE
Full-Scale Error
Reference Set to V
CC
q
3
15
LSB
Reference Set to Internal Bandgap
q
3
15
LSB
V
OUT
DAC Output Span
Reference Set to V
CC
0 to V
CC
V
Reference Set to Internal Bandgap
0 to 2.5
V
V
FSTC
Full-Scale Voltage Temperature Coefficient
Reference Set to V
CC
30
V/
C
Reference Set to Internal Bandgap
50
V/
C
PSRR
Power Supply Rejection Ratio
Reference Set to Internal Bandgap,
0.4
LSB/V
Code = 1023
Power Supply
V
CC
Positive Supply Voltage
q
2.7
5.5
V
I
CC
Supply Current
V
CC
= 3V (Note 3)
q
60
100
A
V
CC
= 5V (Note 3)
q
75
125
A
I
SD
Supply Current in Shutdown Mode
(Note 3)
q
12
24
A
Op Amp DC Performance
Short-Circuit Current (Sourcing)
V
OUT
Shorted to GND, Input Code = 1023
q
25
100
mA
Short-Circuit Current (Sinking)
V
OUT
Shorted to V
CC
, Input Code = 0
q
30
120
mA
Consult LTC Marketing for parts specified with wider operating temperature ranges.
LTAHV
LTAHX
LTAHW
LTAHR
LTAHT
LTAHU
LTC1669-8CMS8
LTC1669-8IMS8
3
LTC1669
1669f
ELECTRICAL C
C
HARA TERISTICS
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
CC
= 2.7V to 5.5V, V
CC
set as reference, V
OUT
unloaded,
unless otherwise noted.
The
q
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
C. V
CC
= 2.7V to 5.5V, V
CC
set as reference, V
OUT
unloaded, unless otherwise noted.
TI I G CHARACTERISTICS
U
W
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity and monotonicity are defined from code 20 to code
1003 (full scale). See Applications Information.
Note 3: Digital inputs at 0V or V
CC
.
Note 4: Load is 10k
in parallel with 100pF.
Note 5: V
CC
= V
REF
= 5V. DAC switched between 0.1V
FS
and 0.9V
FS
,
i.e., codes k = 102 and k = 922.
Note 6: All values are referenced to V
IH
and V
IL
levels.
Note 7: Guaranteed by design and not subject to test.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance to GND
Input Code = 0, V
CC
= 5V
65
Input Code = 0, V
CC
= 3V
150
In Shutdown Mode
500
k
Output Impedance to V
CC
Input Code = 1023, V
CC
= 5V
80
Input Code = 1023, V
CC
= 3V
120
AC Performance
Voltage Output Slew Rate
Rising (Notes 4, 5)
0.75
V/
s
Falling (Notes 4, 5)
0.25
V/
s
Voltage Output Settling Time
To
0.5LSB (Notes 4, 5)
30
s
Digital Feedthrough
0.75
nV s
Digital-to-Analog Glitch Impulse
1LSB Change Around Major Carry
70
nV s
Digital Inputs SCL, SDA
V
IH
High Level Input Voltage
q
2.1
V
V
IL
Low Level Input Voltage
q
1.5
V
V
LTH
Logic Threshold Voltage
1.8
V
I
LEAK
Digital Input Leakage
V
CC
= 5.5V and 0V, V
IN
= GND to V
CC
q
1
A
C
IN
Digital Input Capacitance
(Note 7)
q
10
pF
Digital Output SDA
V
OL
Digital Output Low Voltage
I
PULLUP
= 3mA
q
0.4
V
Address Inputs AD0, AD1, AD2 (MSOP Only)
I
UP
Address Pin Pull-Up Current
V
IN
= 0V
q
0.5
1.5
A
V
IH
High Level Input Voltage
q
V
CC
0.3
V
V
IL
Low Level Input Voltage
q
0.8
V
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
Timing Characteristics (Notes 6, 7)
f
SCL
Clock Operating Frequency
q
100
kHz
t
BUF
Bus Free Time Between Stop and Start Condition
q
4.7
s
t
HD, STA
Hold Time After (Repeated) Start Condition
q
4
s
t
SU, STA
Repeated Start Condition Setup Time
q
4.7
s
t
SU, STO
Stop Condition Setup Time
q
4
s
t
HD, DAT (IN)
Data Hold Time (Input)
q
0
ns
t
HD, DAT (OUT)
Data Hold Time (Output)
q
225
500
3450
ns
t
SU, DAT
Data Setup Time
q
250
ns
t
LOW
Clock Low Period
q
4.7
s
t
HIGH
Clock High Period
q
4
s
t
f
Clock, Data Fall Time
q
20
300
ns
t
r
Clock, Data Rise Time
q
20
1000
ns
4
LTC1669
1669f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Source and Sink Current
Capability with V
CC
= 5V
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Large-Signal Step Response
Midscale Glitch
CODE
0
1.0
ERROR (LSB)
0.8
0.4
0.2
0
1.0
0.4
156
512
640
1669 G01
0.6
0.6
0.8
0.2
28
384
768 896 1024
V
REF
= V
CC
= 5V
T
A
= 25
C
CODE
0
1.0
ERROR (LSB)
0.8
0.4
0.2
0
1.0
0.4
156
512
640
1669 G02
0.6
0.6
0.8
0.2
28
384
768 896 1024
V
REF
= V
CC
= 5V
T
A
= 25
C
OUTPUT CURRENT SOURCE/SINK (mA)
0
1
3
OUTPUT VOLTAGE (V)
3.0
4.0
5.0
4.5
3.5
2.5
1.5
0.5
8
1669 G03
2.0
1.0
0
2
4
6
5
7
9
10
DAC CODE = 1023
DAC CODE = 0
T
A
= 25
C
5
5
0
4
3
2
V
OUT
(VOLTS)
SDA
(VOLTS)
1
0
1669 G04
CODE = 990
CODE = 32
5
s/DIV
V
CC
= 5V
R
L
= 4.7k
C
L
= 100pF
T
A
= 25
C
5V
0V
V
OUT
10mV/DIV
SDA
1669 G05
2
s/DIV
V
CC
= 5V
R
L
= 4.7k
C
L
= 100pF
T
A
= 25
C
CODE = 512 TO 511
Load Regulation vs Output Current
Load Regulation vs Output Current
I
OUT
(mA)
4
1.0
V
OUT
(LSB)
0.8
0.4
0.2
0
1.0
0.4
2
0
1
1669 G06
0.6
0.6
0.8
0.2
3
1
2
3
4
V
CC
= V
REF
= 5V
V
OUT
= 2.5V
CODE = 512
T
A
= 25
C
SOURCE
SINK
I
OUT
(mA)
1.0
1.0
V
OUT
(LSB)
0.8
0.4
0.2
0
1.0
0.4
0.6 0.4
0
0.2
1669 G07
0.6
0.6
0.8
0.2
0.8
0.2
0.6
0.4
0.8 1.0
V
CC
= V
REF
= 3V
V
OUT
= 1.5V
CODE = 512
T
A
= 25
C
SOURCE
SINK
TEMPERATURE (
C)
60
OFFSET ERROR VOLTAGE (mV)
5
4
3
2
1
0
1
2
3
4
5
20
20
40
1669 G08
40
0
60
80
100
TEMPERATURE (
C)
60
OUTPUT VOLTAGE (V)
2.510
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2.490
20
20
40
1669 G09
40
0
60
80
100
REFERENCE SET TO
INTERNAL BANDGAP
Offset Error Voltage vs
Temperature
Full-Scale Output Voltage vs
Temperature
5
LTC1669
1669f
V
CC
(Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V
V
CC
5.5V. Also used as the reference voltage input when the
part is programmed to use V
CC
as the reference.
AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to
either V
CC
or GND to modify the corresponding bit of the
LTC1669's slave address.
GND (Pin 7, Pin 2 on SOT-23): System Ground.
V
OUT
(Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered
rail-to-rail DAC output.
PI
N
FU
N
CTIO
N
S
U
U
U
SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional
Pin. Data is shifted into the SDA pin and acknowledged by
the SDA pin. High impedance pin while data is shifted in.
Open-drain N-channel output during acknowledgment.
Requires a pull-up resistor or current source to V
CC
.
AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to
either V
CC
or GND to modify the corresponding bit of the
LTC1669's slave address.
AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to
either V
CC
or GND to modify the corresponding bit of the
LTC1669's slave address.
SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin. Data
is shifted into the SDA pin at the rising edges of the clock.
This high impedance pin requires a pull-up resistor or
current source to V
CC
.
DEFI
N
ITIO
N
S
U
U
zero. The INL error at a given input code is calculated as
follows:
INL = [V
OUT
V
OS
(V
FS
V
OS
)(code/1023)]/LSB
Where V
OUT
is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = V
REF
/1024
Resolution (n): Defines the number of DAC output states
(2
n
) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (V
OS
): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (
V
OUT
LSB)/LSB
Where
V
OUT
is the measured voltage difference between
two adjacent codes.
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
Full-Scale Error (FSE): The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code that guarantees the output will be greater than
6
LTC1669
1669f
TI I G DIAGRA
U
W
W
Typical LTC1669 Input Waveform--Programming DAC Output for Full Scale (AD2 to AD0 Set High)
ACK
ACK
123
ADDRESS
456789
123456789
123456789
123456789
FULL-SCALE
VOLTAGE
ZERO-SCALE
VOLTAGE
1669 TA02
0
1
001110
0
1
0
0
AD2
AD1
AD0
WR
X
X
X
X
X
000
XX
X
X
X
B
G
S
D
S
Y
11111111
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXX
1
1
XXXXXX
D
9
D
8
ACK
STOP
START
SDA
SCL
V
OUT
NOTE: X = DON'T CARE
ACK
COMMAND
LS DATA
MS DATA
t
SU, DAT
t
HD, STA
t
HD, DAT
SDA
SCL
t
SU, STA
t
HD, STA
t
SU, STO
1663 TD
t
BUF
t
LOW
t
HIGH
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
t
r
t
f
7
LTC1669
1669f
Serial Digital Interface
The LTC1669 communicates with a host (master) using
the standard 2-wire interface. The Timing Diagram shows
the timing relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be high when the bus is not
in use. External pull-up resistors or current sources, such
as the LTC1694 SMBus/I
2
C Accelerator, are required on
these lines.
The LTC1669 is a receive-only (slave) device. The master
can communicate with the LTC1669 using the Quick
Command, Send Byte or Write Word protocols as ex-
plained later.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA
from high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while SCL
is high. The bus is then free for communication with
another SMBus device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge re-
lated clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
line during the Acknowledge clock pulse so that it remains
a stable LOW during the HIGH period of this clock pulse.
Write Word Protocol
The master initiates communication with the LTC1669
with a START condition and a 7-bit address followed by the
Write Bit (Wr) = 0. The LTC1669 acknowledges and the
master delivers the command byte. The LTC1669 ac-
knowledges and latches the command byte into the com-
mand byte input register. The master then delivers the
least significant data byte. Again the LTC1669 acknowl-
edges and the data is latched into the least significant data
byte input register. The master then delivers the most
significant data byte. The LTC1669 acknowledges once
more and latches the data into the most significant data
byte input register. Lastly, the master terminates the
communication with a STOP condition. On the reception
of the STOP condition, the LTC1669 transfers the input
register information to output registers and the DAC
output is updated.
Slave Address (MSOP Package Only)
The LTC1669 can respond to one of eight 7-bit addresses.
The first 4 bits (MSBs) have been factory programmed to
0100. The first 4 bits of the LTC1669-8 have been factory
programmed to 0011. The three address bits, AD2, AD1
and AD0 are programmed by the user and determine the
LSBs of the slave address, as shown in the table below:
LTC1669
LTC-1669-8
AD2
AD1
AD0
0100 xxx
0011 xxx
L
L
L
0100 000
0011 000
L
L
H
0100 001
0011 001
L
H
L
0100 010
0011 010
L
H
H
0100 011
0011 011
H
L
L
0100 100
0011 100
H
L
H
0100 101
0011 101
H
H
L
0100 110
0011 110
H
H
H
0100 111
0011 111
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Write Word Protocol Used by the LTC1669
Command Byte
A
Slave Address
A
Wr
LSData Byte
A
MSData Byte
A
P
S
8
1
7
1
1
8
1
8
1669 TA03
1
1
1
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition
8
LTC1669
1669f
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
Slave Address (SOT-23 Package)
The slave address for the SOT-23 package has been
factory programmed to be "0100 000" (LTC1669) and
"0100 001" (LTC1669-1). If another address is required,
please consult the factory.
Command Byte
7
6
5
4
3
2
1
0
X
X
X
X
X
BG
SD
SY
SY
1
Allows update on Acknowledge of SYNC Address only
0
Update on Stop condition only (Power-On Default)
SD
1
Puts the device in power-down mode
0
Puts the device in standard operating mode
(Power-On Default)
BG
1
Selects the internal bandgap reference
0
Selects the supply as the reference (Power-On Default)
X
X
Don't Care
The stop condition normally initiates the update of the
DAC's output latches. Simultaneous update of more than
one DAC or other devices on the bus can be achieved by
reissuing new start bit, address, command and data bytes
before issuing a final stop condition (which will update all
the devices). An alternate way to achieve simultaneous
LTC1669 updates is to override the stop condition update
by setting the "SY" bit of the command byte. Setting this
bit sets the device to update the DAC output latches only
at the reception of a SYNC address quick command. The
actual update occurs on the rising edge of SCL during the
Acknowledge. In this way, all devices can update on the
reception of the SYNC address quick command instead of
the STOP condition.
A Shutdown (SD) bit = HIGH will put the device in a low
power state but retain all data latch information. Shutdown
will occur at the reception of a STOP condition. This way
shutdown could be synchronized to other devices. The
output impedance of the DAC will go to a high impedance
state (
500k
to GND).
The Bandgap (BG) bit when set to "0" selects the DAC
supply voltage as its voltage reference. The full-scale
output of the DAC with this setting is equal to the supply
voltage. When the BG bit is set to "1," the internal bandgap
reference (
1.25V) is selected as the DAC's reference. The
full-scale output voltage for this setting is 2.5V.
Data Bytes
Least Significant Data Byte
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Most Significant Data Byte
7
6
5
4
3
2
1
0
X
X
X
X
X
X
D9
D8
X = Don't care
Send Byte Protocol
The Send Byte protocol used on the LTC1669 is actually a
subset of the Write Word protocol described previously.
The Send Byte protocol can only be used to send the
command byte information to the LTC1669.
Command Byte
A
Slave Address
A
Wr
P
S
8
1
1
7
1
1
1669 TA04
1
S = Start Condition, Wr = Write Bit, A = Acknowledge, P = Stop Condition
The Send Byte protocol is also used whenever the Write
Word protocol is interrupted for any reason. Reception of
a START or STOP condition after the Acknowledge of the
command byte, but before the Acknowledge of the last
data byte, will cause both data bytes to be ignored and the
command byte to be accepted.
Reception of a START or STOP condition before the
Acknowledge of the command byte will cause the inter-
rupted command byte to be ignored.
9
LTC1669
1669f
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
SYNC Address/Quick Command
In addition to the slave address, the LTC1669 has an
address that can be shared by other devices so that they
may be updated synchronously. The address is called to
the SYNC address and uses the quick command protocol.
The SYNC Address is 1111 110
Ack
Stop
Start
1111 110
SY/CLR
1
1
7
1
1669 TA05
1
SYNC Address
SY/CLR
1
Update output latches on rising edge of SCL during
Acknowledge of SYNC Address
0
Clear all internal latches on rising edge of SCL during
Acknowledge of SYNC Address
The SY/CLR bit set high only has meaning when the "SY"
bit of the command byte was previously set HIGH. On the
otherhand, the SY/CLR bit set LOW will always clear the
part, independent of the state of the "SY" bit in the
command byte.
Voltage Output
The output amplifier contained in the LTC1669 can source
or sink up to 5mA. The output stage swings to within a few
millivolts of either supply rail when unloaded and has an
equivalent output resistance of 85
when driving a load to
the rails. The output amplifier is stable driving capacitive
loads up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance greater
than 1000pF. For example, a 0.1
F load can be driven by
the LTC1669 if a 110
series resistance is used. The phase
margin of the resulting circuit is 45
and increases mono-
tonically from this point if larger values of resistance, ca-
pacitance or both are substituted for the values given.
Rail-to-Rail Output Considerations
As in any rail-to-rail device, the output is limited to
voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Similarly, limiting can occur near full scale when V
CC
is
used as the reference. If V
REF
= V
CC
and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at V
CC
as shown in Figure 1c. No full-scale limiting
can occur if the internal reference is used.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Internal Reference
In applications where a predictable output is required that
is independent of supply voltage, the LTC1669 has a user-
selectable internal reference. Selecting the internal refer-
ence will set the full-scale output voltage to 2.5V. This can
be useful in applications where the supply voltage is
poorly regulated.
Using the LT
1460 Micropower Series Reference as a
Power Supply for the LTC1669
In applications where the advantages of using the internal
reference are required but the full-scale range needs to be
greater than 2.5V, an external series reference can be
used. The LT1460 is ideal for use as a power supply for the
LTC1669 and can provide 3V, 3.3V and 5V full-scale
output voltage ranges. The LT1460 provides accuracy,
noise immunity and extended supply range to the LTC1669
when the LTC1669 is operated ratiometric to V
CC
. Since
both parts are available in SOT-23 packages, the PC board
space for this application is extremely small. See Figure 2.
10
LTC1669
1669f
APPLICATIO
N
S I
N
FOR
M
ATIO
N
W
U
U
U
1669 F01
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
512
0
1023
INPUT CODE
OUTPUT
VOLTAGE
(a)
V
REF
= V
CC
V
REF
= V
CC
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V
REF
= V
CC
IN
0.1
F
1
5 (4)
1 (1)
2
4 (5)
2 (7)
LTC1669 PIN NUMBERS IN PARENTHESES
REFER TO MSOP PACKAGE
3 (8)
3
3.9V TO 20V
3V
OUT
TO
P
SCL
1669 F02
V
CC
GND
SDA
OUT
LTC1669
0V
V
OUT
3V
GND
LT1460S3-3
0.01
F
+
Figure 2. LT1460 As Power Supply for the LTC1669
11
LTC1669
1669f
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
PACKAGE DESCRIPTIO
N
U
MSOP (MS8) 0603
0.53
0.152
(.021
.006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 0.38
(.009 .015)
TYP
0.127
0.076
(.005
.003)
0.86
(.034)
REF
0.65
(.0256)
BSC
0
6
TYP
DETAIL "A"
DETAIL "A"
GAUGE PLANE
1
2
3
4
4.90
0.152
(.193
.006)
8
7 6 5
3.00
0.102
(.118
.004)
(NOTE 3)
3.00
0.102
(.118
.004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 3.45
(.126 .136)
0.889
0.127
(.035
.005)
RECOMMENDED SOLDER PAD LAYOUT
0.42
0.038
(.0165
.0015)
TYP
0.65
(.0256)
BSC
1.50 1.75
(NOTE 4)
2.80 BSC
0.30 0.45 TYP
5 PLCS (NOTE 3)
DATUM `A'
0.09 0.20
(NOTE 3)
S5 TSOT-23 0302
PIN ONE
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 0.90
1.00 MAX
0.01 0.10
0.20 BSC
0.30 0.50 REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
12
LTC1669
1669f
RELATED PARTS
TYPICAL APPLICATIO
N
U
Program Up to 16 Control Outputs Per BUS and Place Them Where They Are Needed
PART NUMBER
DESCRIPTION
COMMENTS
LTC1694
SMBus/I
2
C Accelerator
Dual SMBus Accelerator with Active AC and DC Pull-Up Current Sources
LTC1694-1
SMBus/I
2
C Accelerator
Dual SMBus Accelerator with Active AC Pull-Up Current Only
DACs
LTC1659
Single Rail-to-Rail 12-Bit V
OUT
DAC in
Low Power Multiplying V
OUT
DAC. Output Swings from
8-Lead MSOP Package. V
CC
= 2.7V to 5.5V
GND to REF. REF Input Can Be Tied to V
CC
. 3-Wire Interface.
LTC1660/LTC1664
Octal/Quad 10-Bit V
OUT
DACs in 16-Pin Narrow SSOP
V
CC
= 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface.
LTC1661
Dual 10-Bit V
OUT
in 8-Lead MSOP Package
V
CC
= 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface.
LTC1663
10-Bit V
OUT
in SOT-23, SMBUS Interface
Pin-for-Pin Compatible with LTC1669
ADCs
LTC1285/LTC1288
8-Pin SO, 3V Micropower ADCs
1- or 2-Channel, Autoshutdown
LTC1286/LTC1298
8-Pin SO, 5V Micropower ADCs
1- or 2-Channel, Autoshutdown
LINEAR TECHNOLOGY CORPORATION 2003
LT/TP 1103 1K PRINTED IN THE USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear.com
+
SCL
AD0
AD1
AD2
LTC1669CMS8
V
CC
V
OUT
CONTROL
OUTPUT 0
0V
V
OUT0
< V
CC
0.1
F
0.1
F
1
2
5
7
5
8
7
7
5
8
8
5
4
4
1
6
2
3
GND
+
SCL
AD0
AD1
AD2
LTC1669CMS8
V
CC
V
OUT
CONTROL
OUTPUT 1
0V
V
OUT1
< V
CC
0.1
F
GND
+
SCL
AD0
AD1
AD2
LTC1669-8CMS8
V
CC
V
OUT
CONTROL
OUTPUT 15
0V
V
OUT15
< V
CC
0.1
F
GND
1669 TA06
SMBus 1
LTC1694
SMBus 2
GND
V
CC
V
CC
= 2.7V TO 5.5V
TO OTHER I
2
C
DEVICES
+
SCL
P
SDA
SDA
1
4
6
2
3
SDA
1
4
6
2
3
SDA
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