1861 Layout
1
LTC1861L
1861li
Power, 3V, 12-Bit, 150ksps
2-Channel ADC in MSOP
October 2002
Single 3V Supply, 150ksps, 12-Bit Sampling ADC
Supply Current vs Sampling Frequency
The LTC
1861L is a 12-bit A/D converter that is offered in
MSOP and SO-8 packages and operates on a single 3V
supply. At 150ksps, the supply current is only 450
A. The
supply current drops at lower speeds because the
LTC1861L automatically powers down to a typical supply
current of 500nA between conversions. This 12-bit
switched capacitor successive approximation ADC in-
cludes a sample-and-hold. The LTC1861L offers a soft-
ware-selectable 2-channel MUX. An adjustable reference
pin is provided on the MSOP version.
The 4-wire serial I/O, MSOP or SO-8 package and
extremely high sample rate-to-power ratio make this ADC
an ideal choice for compact, low power, high speed
systems.
This ADC can be used in ratiometric applications or with
external references. The high impedance analog inputs
and the ability to operate with reduced spans down to 1V
full scale, allow direct connection to signal sources in
many applications, eliminating the need for external gain
stages.
s
12-Bit 150ksps ADC in MSOP Package
s
Single 3V Supply
s
Low Supply Current: 450
A (Typ)
s
Auto Shutdown Reduces Supply Current
to 10
A at 1ksps
s
SPI/MICROWIRE
TM
Compatible Serial I/O
s
High Speed Upgrade to LTC1288
s
Pin Compatible with 16-Bit LTC1865L
, LTC and LT are registered trademarks of Linear Technology Corporation.
s
High Speed Data Acquisition
s
Portable or Compact Instrumentation
s
Low Power Battery-Operated Instrumentation
s
Isolated and/or Remote Data Acquisition
MICROWIRE is a trademark of National Semiconductor Corporation.
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
Final Electrical Specifications
TYPICAL APPLICATIO
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1861L TA01
ANALOG
INPUTS
0V TO 3V
3V
1
F
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
CONV
SCK
SDO
SDI
V
REF
V
CC
AGND
DGND
LTC1861L
CH0
CH1
SAMPLING FREQUENCY (kHz)
0.01
SUPPLY CURRENT (
A)
1000
100
10
1
0.1
100
1861L TA02
0.1
1
10
1000
V
CC
= 2.7V
CONV LOW = 1.5
s
T
A
= 25
C
2
LTC1861L
1861li
Power Dissipation .............................................. 400mW
Operating Temperature Range
LTC1861LC ............................................ 0
C to 70
C
LTC1861LI ........................................ 40
C to 85
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec)................. 300
C
Supply Voltage (V
CC
) ................................................. 7V
Ground Voltage Difference
AGND, DGND (MSOP Package) .......................
0.3V
Analog Input ............... (GND 0.3V) to (V
CC
+ 0.3V)
Digital Input ................................ (GND 0.3V) to 7V
Digital Output .............. (GND 0.3V) to (V
CC
+ 0.3V)
(Notes 1, 2)
ORDER PART
NUMBER
MS PART MARKING
ABSOLUTE AXI U RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
LTC1861LCMS
LTC1861LIMS
LTD4
LTD5
Consult LTC Marketing for parts specified with wider operating temperature ranges.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
q
12
Bits
No Missing Codes Resolution
q
12
Bits
INL
(Note 3)
q
1
LSB
Transition Noise
0.13
LSB
RMS
Gain Error
q
20
mV
Offset Error
q
2
5
mV
Analog Input Range
+CH GND or (CH)
q
0
V
REF
V
Absolute Input Range
+CH Input
0.05
V
CC
+ 0.05
V
CH Input
0.05
V
CC
/2
V
V
REF
Input Range
MSOP
1
V
CC
V
Analog Input Leakage Current
(Note 4)
q
1
A
C
IN
Input Capacitance
In Sample Mode
12
pF
During Conversion
5
pF
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25
C.
V
CC
= 2.7V, V
REF
= 2.5V (MSOP) or V
REF
= V
CC
(SO), f
SCK
= f
SCK(MAX)
as defined in Recommended Operating Conditions, unless
otherwise noted.
CO VERTER A D ULTIPLEXER CHARACTERISTICS
U
W
U
ORDER PART
NUMBER
S8 PART MARKING
LTC1861LCS8
LTC1861LIS8
1861L
1861LI
T
JMAX
= 150
C,
JA
= 210
C/W
T
JMAX
= 150
C,
JA
= 175
C/W
1
2
3
4
5
CONV
CH0
CH1
AGND
DGND
10
9
8
7
6
V
REF
V
CC
SCK
SDO
SDI
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
1
2
3
4
8
7
6
5
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
CONV
CH0
CH1
GND
V
CC
SCK
SDO
SDI
3
LTC1861L
1861li
The
q
denotes specifications which apply
over the full operating temperature range, otherwise specifications are T
A
= 25
C. V
CC
= 2.7V, V
REF
= 2.5V (MSOP) or V
REF
= V
CC
(SO),
unless otherwise noted.
The
q
denotes specifications which apply over the full operating temperature range,
otherwise specifications are T
A
= 25
C. V
CC
= 3V, V
REF
= 3V, f
SAMPLE
= 150kHz, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SNR
Signal-to-Noise Ratio
72
dB
S/(N + D) Signal-to-Noise Plus Distortion Ratio
1kHz Input Signal
72
dB
THD
Total Hamonic Distortion Up to 5th Harmonic 1kHz Input Signal
86
dB
Full Power Bandwidth
10
MHz
Full Linear Bandwidth
S/(N + D)
68dB
30
kHz
DY
A
IC ACCURACY
U
W
DIGITAL A D DC ELECTRICAL CHARACTERISTICS
U
The
q
denotes specifications which apply over the
full operating temperature range, otherwise specifications are T
A
= 25
C.
RECO
E
DED OPERATI
G CO DITIO
S
U
U
U
U
W
W
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
Supply Voltage
2.7
3.6
V
f
SCK
Clock Frequency
q
DC
8
MHz
t
CYC
Total Cycle Time
12 SCK + t
CONV
s
t
SMPL
Analog Input Sampling Time
10
SCK
t
suCONV
Setup Time CONV
Before First SCK
,
60
ns
(See Figure 1)
t
hDI
Holdtime SDI After SCK
30
ns
t
suDI
Setup Time SDI Stable Before SCK
30
ns
t
WHCLK
SCK High Time
f
SCK
= f
SCK(MAX)
45%
1/f
SCK
t
WLCLK
SCK Low Time
f
SCK
= f
SCK(MAX)
45%
1/f
SCK
t
WHCONV
CONV High Time Between Data
t
CONV
s
Transfer Cycles
t
WLCONV
CONV Low Time During Data Transfer
12
SCK
t
hCONV
Hold Time CONV Low After Last SCK
26
ns
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
V
CC
= 3.3V
q
1.9
V
V
IL
Low Level Input Voltage
V
CC
= 2.7V
q
0.45
V
I
IH
High Level Input Current
V
IN
= V
CC
q
2.5
A
I
IL
Low Level Input Current
V
IN
= 0V
q
2.5
A
V
OH
High Level Output Voltage
V
CC
= 2.7V, I
O
= 10
A
q
2.3
2.60
V
V
CC
= 2.7V, I
O
= 360
A
q
2.1
2.45
V
V
OL
Low Level Output Voltage
V
CC
= 2.7V, I
O
= 400
A
q
0.3
V
I
OZ
Hi-Z Output Leakage
CONV = V
CC
q
3
A
I
SOURCE
Output Source Current
V
OUT
= 0V
6.5
mA
I
SINK
Output Sink Current
V
OUT
= V
CC
6.5
mA
I
REF
Reference Current (MSOP)
CONV = V
CC
q
0.001
3
A
f
SMPL
= f
SMPL(MAX)
q
0.01
0.1
mA
I
CC
Supply Current
CONV = V
CC
After Conversion
q
0.5
10
A
f
SMPL
= f
SMPL(MAX)
q
0.45
1
mA
P
D
Power Dissipation
f
SMPL
= f
SMPL(MAX)
1.22
mW
4
LTC1861L
1861li
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: Integral nonlinearity is defined as deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 4: Channel leakage current is measured while the part is in sample
mode.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
CONV
Conversion Time (See Figure 1)
q
3.7
4.66
s
f
SMPL(MAX)
Maximum Sampling Frequency
q
150
kHz
t
dDO
Delay Time, SCK
to SDO Data Valid
C
LOAD
= 20pF
45
55
ns
q
60
ns
t
dis
Delay Time, CONV
to SDO Hi-Z
q
55
120
ns
t
en
Delay Time, CONV
to SDO Enabled
C
LOAD
= 20pF
q
35
120
ns
t
hDO
Time Output Data Remains
C
LOAD
= 20pF
q
5
15
ns
Valid After SCK
t
r
SDO Rise Time
C
LOAD
= 20pF
25
ns
t
f
SDO Fall Time
C
LOAD
= 20pF
12
ns
TI I G CHARACTERISTICS
U
W
U
U
U
PI FU CTIO S
(MSOP Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is finished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to AGND.
AGND (Pin 4): Analog Ground. AGND should be tied
directly to an analog ground plane.
DGND (Pin 5): Digital Ground. DGND should be tied
directly to an analog ground plane.
SDI (Pin 6): Digital Data Input. The A/D configuration
word is shifted into this input.
SDO (Pin 7): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 8): Shift Clock Input. This clock synchronizes the
serial data transfer.
V
CC
(Pin 9): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
(SO-8 Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is left
high after the A/D conversion is finished, the part powers
down. A logic low on this input enables the SDO pin,
allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
SDI (Pin 5): Digital Data Input. The A/D configuration
word is shifted into this input.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 7): Shift Clock Input. This clock synchronizes the
serial data transfer.
V
CC
(Pin 8): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane. V
REF
is tied internally to this pin.
V
REF
(Pin 10): Reference Input. The reference input de-
fines the span of the A/D converter and must be kept free
of noise with respect to AGND.
The
q
denotes specifications which apply over the full operating temperature
range, otherwise specifications are T
A
= 25
C. V
CC
= 2.7V, V
REF
= 2.5V (MSOP) or V
REF
= V
CC
(SO), f
SCK
= f
SCK(MAX)
as defined in
Recommended Operating Conditions, unless otherwise noted.
5
LTC1861L
1861li
BLOCK DIAGRA
W
CONVERT
CLK
BIAS AND
SHUTDOWN
DATA IN
DATA OUT
12-BITS
SERIAL
PORT
12-BIT
SAMPLING
ADC
V
CC
CONV SDI
SCK
SDO
V
REF
(MSOP ONLY)
GND
CH1
CH0
+
1861 BD
Load Circuit for t
dDO
, t
r
, t
f
, t
dis
and t
en
Voltage Waveforms for SDO Rise and Fall Times, t
r
, t
f
Voltage Waveforms for SDO Delay Time, t
dDO
and t
hDO
Voltage Waveforms for t
en
SDO
3k
20pF
TEST POINT
V
CC
t
dis
WAVEFORM 2, t
en
t
dis
WAVEFORM 1
1860 TC01
SCK
SDO
V
IL
t
dDO
t
hDO
V
OH
V
OL
1860 TC02
1860 TC03
CONV
SDO
t
en
SDO
t
r
t
f
1860 TC04
V
OH
V
OL
TEST CIRCUITS
Voltage Waveforms for t
dis
SDO
WAVEFORM 1
(SEE NOTE 1)
V
IH
t
dis
90%
10%
SDO
WAVEFORM 2
(SEE NOTE 2)
CONV
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
1860 TC05
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