1
LTC1879
1879f
1.2A Synchronous
Step-Down Regulator with
15
A Quiescent Current
s
Cellular Telephones
s
Portable Computers
s
Wireless Modems
, LTC and LT are registered trademarks of Linear Technology Corporation.
High Efficiency Step-Down Converter
s
High Efficiency: Up to 95%
s
Low Quiescent Current: Only 15
A with No Load
s
550kHz Constant Frequency Operation
s
2.65V to 10V Input Voltage Range
s
V
OUT
from 0.8V to V
IN
, I
OUT
to 1.2A
s
True PLL Frequency Locking from 350kHz to 750kHz
s
Power Good Output Voltage Monitor
s
Low Dropout Operation: 100% Duty Cycle
s
Burst Mode
or Pulse Skipping Operation
s
Current Mode Operation for Excellent Line and Load
Transient Response
s
Shutdown Mode Draws < 1
A Supply Current
s
2% Output Voltage Accuracy
s
Overcurrent and Overtemperature Protected
s
Available in 16-Lead SSOP Package
The LTC
1879 is a high efficiency monolithic synchro-
nous buck regulator using a constant frequency, current
mode architecture. Operating supply current is only 15
A
with no load and drops to < 1
A in shutdown. The input
supply voltage range of 2.65V to 10V makes the LTC1879
ideally suited for both single and dual Li-Ion battery-pow-
ered applications. 100% duty cycle provides low dropout
operation, extending battery life in portable systems.
The switching frequency is internally set to 550kHz, allow-
ing the use of small surface mount inductors and capaci-
tors. For noise sensitive applications, the LTC1879 can be
externally synchronized from 350kHz to 750kHz. Burst
Mode operation is inhibited during synchronization or
when the SYNC/MODE pin is pulled low.
The internal synchronous rectifier switch increases effi-
ciency and eliminates the need for an external Schottky
diode. Low output voltages are easily supported with a
0.8V feedback reference voltage. The LTC1879 is available
in a 16-lead SSOP package.
Burst Mode is a registered trademark of Linear Technology Corporation.
Efficiency vs Output Load Current
RUN/SS
SYNC/MODE
PGOOD
I
TH
2
15
14
4
PV
IN
SWP
SWN
PGND
V
FB
8, 9
5, 12
6, 11
7, 10
3
SV
IN
13
LTC1879
28.0k
C
IN
: TAIYO YUDEN CERAMIC LMK325BJ106MN
C
OUT
: TDK CERAMIC C4532X5ROJ476M
L1: TOKO A921CY6R2M
*V
OUT
CONNECTED TO V
IN
(MINUS SWITCH AND L1 VOLTAGE DROP) FOR 2.65V < V
IN
< 3.1V
1879 TA01a
1
220pF
150k
80.6k
C
OUT
47
F
V
OUT
*
3.1V
L1
6.2
H
SGND
47pF
C
IN
10
F
V
IN
2.65V TO 10V
OUPUT CURRENT (mA)
EFFICIENCY (%)
100
90
80
70
60
50
40
30
0.1
10
100
1879 TA01b
1
1000
Burst Mode OPERATION
V
OUT
= 3.1V
L = 6.2
H
V
IN
= 7.2V
V
IN
= 10V
V
IN
= 3.6V
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
2
LTC1879
1879f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
VFB
Feedback Current
(Note 4)
q
8
60
nA
V
FB
Regulated Output Voltage
(Note 4) 0
C
T
A
85
C
0.784
0.80
0.816
V
(Note 4) 40
C
T
A
85
C
q
0.740
0.80
0.840
V
V
OVL
Overvoltage Trip Limit with Respect to V
FB
V
OVL
= V
OVL
V
FB
q
20
60
110
mV
V
UVL
Undervoltage Trip Limit with Respect to V
FB
V
UVL
= V
FB
V
UVL
q
20
60
110
mV
V
FB
/V
FB
Reference Voltage Line Regulation
V
IN
= 2.65V to 10V (Note 4)
0.05
0.25
%/V
V
LOADREG
Output Voltage Load Regulation
Measured in Servo Loop, V
ITH
= 0.9V to 1.2V
q
0.1
0.6
%
Measured in Servo Loop, V
ITH
= 1.6V to 1.2V
q
0.1
0.6
%
V
IN
Input Voltage Range
q
2.65
10
V
I
Q
Input DC Bias Current
(Note 5)
Pulse Skipping Mode
2.65V < V
IN
< 10V, V
SYNC/MODE
= 0V, I
OUT
= 0A
270
365
A
Burst Mode Operation
V
SYNC/MODE
= V
IN
, I
OUT
= 0A
15
22
A
Shutdown
V
RUN
= 0V, V
IN
= 10V
0
1
A
f
SYNC
SYNC Capture Range
350
750
kHz
f
OSC
Oscillator Frequency
V
FB
0.7V
495
550
605
kHz
V
FB
= 0V
80
kHz
I
PLLLPF
Phase Detector Output Current
Sinking Capability
f
PLLIN
< f
OSC
q
3
10
20
A
Sourcing Capability
f
PPLIN
> f
SOC
q
3
10
20
A
R
PFET
R
DS(ON)
of P-Channel FET
I
SW
= 100mA, V
IN
= 5V
0.35
0.45
R
NFET
R
DS(ON)
of N-Channel FET
I
SW
= 100mA, V
IN
= 5V
0.37
0.5
I
PK
Peak Inductor Current
V
FB
= 0.7V, Duty Cycle < 35%, V
IN
= 5V
1.8
2.2
2.7
A
I
LSW
SW Leakage
V
RUN
= 0V, V
SW
= 0V or 10V, V
IN
= 10V
0.01
2.5
A
V
SYNC/MODE
SYNC/MODE Threshold
q
0.2
1.0
1.5
V
I
SYNC/MODE
SYNC/MODE Leakage Current
0.01
1
A
(Note 1)
ORDER PART
NUMBER
LTC1879EGN
T
JMAX
= 125
C,
JA
= 140
C/ W,
JC
= 40
C/ W
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25
C.
V
IN
= 5V unless otherwise noted.
ABSOLUTE
M
AXI
M
U
M
RATINGS
W
W
W
U
PACKAGE/ORDER I
N
FOR
M
ATIO
N
W
U
U
ELECTRICAL CHARACTERISTICS
Input Supply Voltage ................................ 0.3V to 11V
I
TH
, PLL_LPF Voltages ............................. 0.3V to 2.7V
RUN/SS, V
FB
Voltages ............................... 0.3V to V
IN
SYNC/MODE Voltage ................................. 0.3V to V
IN
(V
PVIN
V
SWP
) Voltage ............................. 0.3V to 11V
V
SWN
Voltage ............................................ 0.3V to 11V
P-Channel Switch Source Current (DC) .................... 2A
N-Channel Switch Sink Current (DC) ........................ 2A
Peak Switching Sink and Source Current ................. 3A
Operating Ambient Temperature Range
(Note 2) ............................................. 40
C to 85
C
Junction Temperature (Notes 3, 6) ...................... 125
C
Storage Temperature Range ................ 65
C to 150
C
Lead Temperature (Soldering, 10 sec)................. 300
C
TOP VIEW
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SGND
RUN/SS
V
FB
I
TH
SWP1
SWN1
PGND1
PV
IN1
PLL_LPF
SYNC/MODE
PGOOD
SV
IN
SWP2
SWN2
PGND2
PV
IN2
GN PART
MARKING
1879
Consult LTC Marketing for parts specified with wider operating temperature ranges.
3
LTC1879
1879f
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25
C.
V
IN
= 5V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
V
RUN
RUN Threshold
V
RUN
Ramping Up
q
0.2
0.7
1.5
V
I
RUN
RUN Input Current
V
RUN
= 0V
0.01
1
A
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC1879E is guaranteed to meet specified performance from
0
C to 70
C. Specifications over the 40
C to 85
C operating ambient
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
LTC1879: T
J
= T
A
+ (P
D
140
C/W)
Note 4: The LTC1879 is tested in a feedback loop which servos V
FB
to the
balance point for the error amplifier (V
ITH
= 1.2V)
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125
C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
R
DS(ON)
vs Temperature
Oscillator Frequency
vs Temperature
Oscillator Frequency
vs Supply Voltage
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
DC Supply Current
vs Temperature
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
R
DS(ON)
vs Input Voltage
TEMPERATURE (
C)
50
25
0
25
50
75
100
125
R
DS(ON)
(
)
1879 G01
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
IN
= 5V
V
IN
= 5V
V
IN
= 10V
V
IN
= 10V
SYNCHRONOUS SWITCH
MAIN SWITCH
TEMPERATURE (
C)
50
25
0
25
50
75
100
125
FREQUENCY (kHz)
1879 G02
595
575
555
535
515
495
V
IN
= 5V
SUPPLY VOLTAGE (V)
2
4
6
8
10
OSCILLATOR FREQUENCY (kHz)
1879 G03
600
590
580
570
560
550
540
530
520
510
500
TEMPERATURE (
C)
50
0
50
100
125
SUPPLY CURRENT (
A)
1879 G04
300
250
200
150
100
50
0
PULSE SKIPPING MODE
Burst Mode OPERATON
V
IN
= 5V
DC Supply Current
vs Input Voltage
INPUT VOLTAGE (V)
0
0
DC SUPPLY CURRENT (
A)
50
100
150
200
250
300
2
4
6
8
1879 G05
10
PULSE SKIPPING MODE
Burst Mode OPERATION
INPUT VOLTAGE (V)
2
0
R
DS(ON)
(
)
0.1
0.2
0.3
0.4
4
6
8
10
1879 G06
0.5
0.6
3
5
7
9
SYNCHRONOUS
SWITCH
MAIN
SWITCH
4
LTC1879
1879f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Switch Leakage vs Temperature
Efficiency vs Output Current
Efficiency vs Input Voltage
Efficiency vs Output Current
TEMPERATURE (
C)
50
0
SWITCH LEAKAGE (
A)
2
6
8
10
20
14
0
50
75
1879 G07
4
16
18
12
25
25
100
125
V
IN
= 10V
MAIN SWITCH
SYNCHRONOUS
SWITCH
INPUT VOLTAGE (V)
0
SWITCH LEAKAGE (nA)
30
40
50
8
1879 G08
20
10
25
35
45
15
5
0
2
4
6
10
RUN = 0V
T
A
= 25
C
SYNCHRONOUS SWITCH
MAIN SWITCH
Switch Leakage vs Input Voltage
Output Voltage vs Load Current
LOAD CURRENT (mA)
0
2.41
OUTPUT VOLTAGE (V)
2.42
2.44
2.45
2.46
2.51
2.48
400
800 1000
1879 G09
2.43
2.49
2.50
2.47
200
600
1200 1400 1600
PULSE SKIPPING MODE
V
IN
= 5V
L = 6.2
H
Reference Voltage
vs Temperature
TEMPERATURE (
C)
50
25
0
25
50
75
100
125
REFERENCE VOLTAGE (mV)
1879 G10
804
803
802
801
800
799
798
797
796
795
794
V
IN
= 6V
OUTPUT CURRENT (mA)
EFFICIENCY (%)
100
90
80
70
60
50
40
30
0.1
10
100
1879 G11
1
1000
V
IN
= 10V
V
IN
= 3.6V
V
OUT
= 1.8V
L = 6.2
H
Burst Mode OPERATION
V
IN
= 5V
V
IN
= 7.2V
OUTPUT CURRENT (mA)
EFFICIENCY (%)
100
90
80
70
60
50
40
30
0.1
10
100
1879 G12
1
1000
V
IN
= 10V
V
IN
= 3.6V
V
OUT
= 2.5V
L = 6.2
H
Burst Mode OPERATION
V
IN
= 7.2V
V
IN
= 5V
Efficiency vs Output Current
OUTPUT CURRENT (mA)
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
0
0.1
10
100
1879 G13
1
1000
V
OUT
= 3.1V
L = 6.2
H
Burst Mode OPERATION
PULSE SKIPPING MODE
V
IN
= 4.2V
V
IN
= 4.2V
V
IN
= 7.2V
V
IN
= 7.2V
INPUT VOLTAGE (V)
2
70
80
100
8
1879 G14
60
0.1mA
1mA
100mA
10mA
50
4
6
10
40
30
90
EFFICIENCY (%)
V
OUT
= 2.5V
L = 6.2
H
Burst Mode OPERATION
5
LTC1879
1879f
Load Step
(Pulse Skipping Mode)
Pulse Skipping Mode Operation
Burst Mode Operation
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
I
L
200mA/DIV
V
OUT
20mV/DIV
SW
5V/DIV
V
OUT
100mV/DIV
I
L
1A/DIV
I
L
200mA/DIV
V
OUT
50mV/DIV
SW
5V/DIV
50
s/DIV
1879 G16
V
IN
= 5V
C
IN
= 20
F
V
OUT
= 2.5V
C
OUT
= 47
F
L = 4.7
H
I
LOAD
= 50mA to 1200mA
2.5
s/DIV
1879 G17
V
IN
= 5V
C
IN
= 20
F
V
OUT
= 2.5V
C
OUT
= 47
F
L = 4.7
H
I
LOAD
= 15mA
25
s/DIV
1879 G18
V
IN
= 5V
C
IN
= 20
F
V
OUT
= 2.5V
C
OUT
= 47
F
L = 4.7
H
I
LOAD
= 15mA
Load Step (Burst Mode Operation)
V
OUT
100mV/DIV
I
L
1A/DIV
50
s/DIV
1879 G15
V
IN
= 5V
C
IN
= 20
F
V
OUT
= 2.5V
C
OUT
= 47
F
L = 4.7
H
I
LOAD
= 50mA to 1200mA
Soft-Start with Shorted Output
I
VIN
500mA/DIV
RUN/SS
1V/DIV
5ms/DIV
1879 G19
V
IN
= 5V
C
IN
= 20
F
V
OUT
= 0V
C
OUT
= 47
F
L = 4.7
H
I
LOAD
= 0A
6
LTC1879
1879f
U
U
U
PI FU CTIO S
SGND (Pin 1): Signal Ground Pin.
RUN/SS (Pin 2): Combination of Soft-Start and Run
Control Inputs. Forcing this pin below 0.7V shuts down the
device. In shutdown all functions are disabled and device
draws zero supply current. For the proper operation of the
part, force this pin above 2.5V. Do not leave this pin
floating. Soft-start can be accomplished by raising the
voltage on this pin gradually with an RC circuit.
V
FB
(Pin 3): Feedback Pin. Receives the feedback voltage
from an external resistor divider across the output.
I
TH
(Pin 4): Error Amplifier Compensation Point. The
current output increases with this control voltage. Nomi-
nal voltage range for this pin is 0.5V to 1.8V.
SWP1, SWP2 (Pins 5, 12): Upper Switch Nodes. These
pins connect to the drains of the internal main PMOS
switches and should always be connected together
externally.
SWN1, SWN2 (Pins 6, 11): Lower Switch Nodes. These
pins connect to the drains of the internal synchronous
NMOS switches and should always be connected together
externally.
PGND1, PGND2 (Pins 7, 10): Power Ground Pins. Ground
pins for the internal drivers and switches. These pins
should always be tied together.
PV
IN1
, PV
IN2
(Pins 8, 9): Power Supply Pins for the
Internal Drivers and Switches. These pins should always
be tied together.
SV
IN
(Pin 13): Signal Power Supply Pin.
PGOOD (Pin 14): Power Good Indicator Pin. Power good
is an open-drain logic output. The PGOOD pin is pulled to
ground when the voltage on the V
FB
pin is not within
7.5% of its nominally regulated potential. This pin re-
quires a pull-up resistor for power good indication. Power
good indication works in all modes of operation.
SYNC/MODE (Pin 15): External Clock Synchronization
and Mode Select Input. To synchronize, apply an external
clock with a frequency between 350kHz and 750kHz. To
select Burst Mode operation, tie pin to SV
IN
. Grounding
this pin selects pulse skipping mode. Do not leave this pin
floating.
PLL_LPF (Pin 16): Output of the Phase Detector and
Control Input of Oscillator. Connect a series RC lowpass
network from this pin to ground if externally synchronized.
If unused, this pin may be left open.
7
LTC1879
1879f
BLOCK DIAGRA
W
+
+
+
+
+
EA
I
TH
BURST
SLEEP
EN
SLEEP
0.8V
0.86V
0.6V
V
FB
SV
IN
FREQ
SHIFT
SLOPE
COMP
OSC
VCO
AND
OSC
X
BURST DEFEAT
Y
Y = "0" ONLY WHEN X IS A CONSTANT "1"
RUN/SS
SYNC/MODE
PLL_LPF
S
R
RS LATCH
Q
0.45V
Q
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
THERMAL
SHUTDOWN
ANTI-
SHOOT-
THROUGH
OVDET
OV
+
RCMP
+
0.74V
UVDET
PGOOD
SHUTDOWN
SGND
SOFT-START
0.8V REF
SV
IN
+
I
COMP
2.9
PGND
7, 10
6, 11
8, 9
TOP
MOSFET
BOTTOM
MOSFET
1879 BD
SWN
PV
IN
SV
IN
0.8V
14
1
4
16
15
3
2
13
5, 12
SWP
8
LTC1879
1879f
OPERATIO
U
Main Control Loop
The LTC1879 uses a constant frequency, current mode
step-down architecture. Both the top MOSFET and syn-
chronous bottom MOSFET switches are internal. During
normal operation, the internal top power MOSFET is
turned on each cycle when the oscillator sets the RS latch,
and turned off when the current comparator, I
COMP
, resets
the RS latch. The peak inductor current at which I
COMP
turns the top MOSFET off is controlled by the voltage on
the I
TH
pin, which is the output of error amplifier EA. When
the load current increases, it causes a slight decrease in
the feedback voltage, V
FB
, relative to the 0.8V internal
reference, which, in turn, causes the I
TH
voltage to in-
crease until the average inductor current matches the new
load current. While the top MOSFET is off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse direction or the next clock cycle begins.
Comparator OVDET guards against transient overshoots
> 7.5% by turning the main switch off and keeping it off
until the fault is removed.
Burst Mode Operation
The LTC1879 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
tie the SYNC/MODE pin to SV
IN
or connect it to a logic high
(V
SYNC/MODE
> 1.5V). To disable Burst Mode operation
and enable PWM pulse skipping mode, connect the SYNC/
MODE pin to SGND. In this mode, the efficiency is lower at
light loads but becomes comparable to Burst Mode opera-
tion when the output load exceeds 100mA. The advantage
of pulse skipping mode is lower output ripple.
When the converter is in Burst Mode operation, the peak
current of the inductor is set to approximately 400mA,
even though the voltage at the I
TH
pin indicates a lower
value. The voltage at the I
TH
pin drops when the inductor's
average current is greater than the load requirement. As
the I
TH
voltage drops below approximately 0.45V, the
BURST comparator trips, turning off both power MOSFETs.
The I
TH
pin is then disconnected from the output of the EA
amplifier and held 0.65V above ground.
In sleep mode, both power MOSFETs are held off and the
internal circuitry is partially turned off, reducing the quies-
cent current to 15
A. The load current is now being
supplied from the output capacitor. When the output
voltage drops, the I
TH
pin reconnects to the output of the
EA amplifier and the top MOSFET is again turned on and
this process repeats.
Soft-Start/Run Function
The RUN/SS pin provides a soft-start function and a
means to shut down the LTC1879. Soft-start reduces the
input current surge by gradually increasing the regulator's
maximum output current. This pin can also be used for
power supply sequencing.
Pulling the RUN/SS pin below 0.7V shuts down the
LTC1879, which then draws < 1
A current from the sup-
ply. This pin can be driven directly from logic circuits as
shown in Figure 1. It is recommended that this pin is driven
to V
IN
during normal operation. Note that there is no
current flowing out of this pin. Soft-start action is accom-
plished by connecting an external RC network to the RUN/
SS pin as shown in Figure 1. The LTC1879 actively pulls
the RUN/SS pin to ground under low input supply voltage
conditions.
(Refer to Block Diagram)
Figure 1. RUN/SS Pin Interfacing
3.3V OR 5V
V
IN
RUN/SS
D1*
0.32V
R
SS
C
SS
*ZETEX BAT54
1879 F01
9
LTC1879
1879f
Power Good Indicator
The power good function monitors the output voltage in all
modes of operation. Its open-drain output is pulled low
when the output voltage is not within
7.5% of its nomi-
nally regulated voltage. The feedback voltage is filtered
before it is fed to a power good window comparator in
order to prevent false tripping of the power good signal
during fast transients. The window comparator monitors
the output voltage even in Burst Mode operation. In
shutdown mode, open drain is actively pulled low to
indicate that the output voltage is invalid.
Short-Circuit Protection
When the output is shorted to ground, the frequency of
the oscillator is reduced to about 80kHz, 1/7 the nominal
frequency. This frequency foldback ensures that the in-
ductor current has more time to decay, thereby preventing
runaway. The oscillator's frequency will progressively
increase to 550kHz (or to the synchronized frequency)
when V
FB
rises above 0.3V.
Frequency Synchronization
The LTC1879 can be synchronized to an external clock
source connected to the SYNC/MODE pin. The turn-on of
the top MOSFET is synchronized to the rising edge of the
external clock.
When the LTC1879 is clocked by an external source, Burst
Mode operation is disabled. In this synchronized mode,
when the output load current is very low, current compara-
tor, I
COMP
, may remain tripped for several cycles and force
the main switch to stay off for the same number of cycles.
Increasing the output load slightly allows constant fre-
quency PWM operation to resume.
Frequency synchronization is inhibited when the feedback
voltage V
FB
is below 0.6V. This prevents the external clock
from interfering with the frequency foldback for short-
circuit protection.
Low Dropout Operation
When the input supply voltage decreases toward the
output voltage in a buck regulator, the duty cycle in-
creases toward the maximum on-time. Further reduction
of the supply voltage forces the main switch to remain on
for more than one cycle until it reaches 100% duty cycle.
The output voltage will then be determined by the input
voltage minus the voltage drop across the top MOSFET
and the inductor.
Low Supply Operation
The LTC1879 is designed to operate down to an input
supply voltage of 2.65V although the maximum allowable
output current is reduced at this low voltage. Figure 2
shows the reduction in the maximum output current as a
function of input voltage.
Another important detail to remember is that at low input
supply voltages, the R
DS(ON)
of the P-channel switch
increases. Therefore, the user should calculate the power
dissipation when the LTC1879 is used at 100% duty cycle
with low supply voltage (see Thermal Considerations in
the Applications Information section).
Figure 2. Maximum Output Current vs Input Voltage
OPERATIO
U
(Refer to Block Diagram)
INPUT VOLTAGE (V)
2
MAXIMUM OUTPUT CURRENT (mA)
1200
1400
1600
8
1879 F02
1000
800
4
3
6
9
5
7
10
600
400
1800
V
OUT
= 1.8V
V
OUT
= 3.1V
V
OUT
= 2.5V
10
LTC1879
1879f
OPERATIO
U
Slope Compensation and Inductor Peak Current
Slope compensation is required in order to prevent sub-
harmonic oscillation at high duty cycles. It is accom-
plished by internally adding a compensating ramp to the
inductor current signal at duty cycles in excess of 40%. As
a result, the maximum inductor peak current is reduced for
duty cycles > 40%. This is shown in the decrease of the
inductor peak current as a function of duty cycle graph in
Figure 3.
Figure 3. Maximum Inductor Peak Current vs Duty Cycle
APPLICATIO S I FOR ATIO
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The basic LTC1879 application circuit is shown on the first
page of this data sheet. External component selection is
driven by the load requirement and begins with the selec-
tion of L followed by C
IN
and C
OUT
.
Inductor Value Calculation
The inductor selection will depend on the operating fre-
quency of the LTC1879. The internal nominal frequency is
550kHz, but can be externally synchronized from 350kHz
to 750kHz.
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. However, oper-
ating at a higher frequency results in lower efficiency
because of increased switching losses.
The inductor value has a direct effect on ripple current. The
ripple current
I
L
decreases with higher inductance or
frequency and increases with higher input voltages.
=
( )( )
I
f L
V
V
V
L
OUT
OUT
IN
1
1
(1)
Accepting larger values of
I
L
allows the use of smaller
inductors, but results in higher output voltage ripple.
A reasonable starting point for setting ripple current is
I
L
= 0.3(I
MAX
).
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately
500mA. Lower inductor values (higher
I
L
) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
Inductor Selection
The inductor should have a saturation current rating
greater than the peak inductor current set by the current
comparator of LTC1879. Also, consideration should be
given to the resistance of the inductor. Inductor conduc-
tion losses are directly proportional to the DC resistance
of the inductor. Manufacturers sometimes provide maxi-
mum current ratings based on the allowable losses in the
inductor.
Suitable inductors are available from Coilcraft, Cooper,
Dale, Sumida, Toko, Murata, Panasonic and other manu-
facturers.
DUTY CYCLE (%)
0
MAXIMUM INDUCTOR PEAK CURRENT (mA)
2400
2200
2000
1800
1600
1400
1200
1000
20
40
60
80
1879 F03
100
V
IN
= 5V
11
LTC1879
1879f
C
IN
and C
OUT
Selection
In continuous mode, the source current of the top MOSFET
is a trapezoidal waveform of duty cycle V
OUT
/V
IN
. To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current must be used. The
maximum RMS input capacitor current is given by:
I
I
V
V
V
V
RMS CIN
OMAX
OUT
IN
OUT
IN
(
)
/
(
)
[
]
1 2
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst-case condition is com-
monly used for design because even significant devia-
tions do not offer much relief. Note that the capacitor
manufacturer's ripple current ratings are often based on
2000 hours of life. This makes it advisable to further
derate the capacitor, or choose a capacitor rated at a
higher temperature than required. Several capacitors may
also be paralleled to meet size or height requirements in
the design. Always consult the manufacturer if there are
any questions.
Depending on how the LTC1879 circuit is powered up,
you may need to check for input voltage transients. Input
voltage transients may be caused by input voltage steps
or by connecting the circuit to an already powered up
source such as a wall adapter. The sudden application of
input voltage will cause a large surge of current in the
input leads that will store energy in the parasitic induc-
tance of the leads. This energy will cause the input voltage
to swing above the DC level of the input power source and
it may exceed the maximum voltage rating of the input
capacitor and LTC1879.
The easiest way to suppress input voltage transients is to
add a small aluminum electrolytic capacitor in parallel
with the low ESR input capacitor. The selected capacitor
needs to have the right amount of ESR in order to critically
dampen the resonant circuit formed by the input lead
inductance and the input capacitor. The typical values of
ESR will fall in the range of 0.5
to 2
and capacitance
will fall in the range of 5
F to 50
F.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment is satisfied, the capacitance is adequate for filtering.
The output ripple
V
OUT
is determined by:
+
V
I ESR
fC
OUT
L
OUT
1
8
where f = operating frequency, C
OUT
= output capacitance
and
I
L
= ripple current in the inductor. The output ripple
is highest at maximum input voltage since
I
L
increases
with input voltage. For the LTC1879, the general rule for
proper operation is:
ESR
COUT
< 0.125
The choice of using a smaller output capacitance in-
creases the output ripple voltage due to the frequency
dependent term but can be compensated for by using
capacitor(s) of very low ESR to maintain low ripple volt-
age. The I
TH
pin compensation components can be opti-
mized to provide stable high performance transient
response regardless of the output capacitor selected.
Manufacturers such as Taiyo Yuden, AVX, Kemet and
Sanyo should be considered for low ESR, high perfor-
mance capacitors. The POSCAP solid electrolytic chip
capacitor available from Sanyo is an excellent choice for
output bulk capacitors due to its low ESR/size ratio. Once
the ESR requirement for C
OUT
has been met, the RMS
current rating generally far exceeds the I
RIPPLE(P-P)
requirement.
Output Voltage Programming
The output voltage is set by a resistor divider according to
the following formula:
V
V
R
R
OUT
=
+
0 8
1
1
2
.
(2)
The external resistor divider is connected to the output,
allowing remote voltage sensing as shown in Figure 4.
APPLICATIO S I FOR ATIO
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LTC1879
1879f
APPLICATIO S I FOR ATIO
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If the external frequency (V
SYNC/MODE
) is greater than
550kHz, the center frequency, current is sourced continu-
ously, pulling up the PLL_LPF pin. When the external
frequency is less than 550kHz, current is sunk continu-
ously, pulling down the PLL_LPF pin. If the external and
internal frequencies are the same but exhibit a phase
difference, the current sources turn on for an amount of
time corresponding to the phase difference. Thus the
voltage on the PLL_LPF pin is adjusted until the phase and
frequency of the external and internal oscillators are
identical. At this stable operating point the phase com-
parator output is open and the filter capacitor C
LP
holds the
voltage.
The loop filter components C
LP
and R
LP
smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
= 10k and C
LP
is 2200pF to
0.01
F. When not synchronized to an external clock, the
internal connection to the VCO is disconnected. This
disallows setting the internal oscillation frequency by a DC
voltage on the V
PLLLPF
pin.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% (
1 +
2 +
3 + ...)
Figure 5. Relationship Between Oscillator Frequency
and Voltage at PLL_LPF Pin
Figure 6. Phase-Locked Loop Block Diagram
Phase-Locked Loop and Frequency Synchronization
The LTC1879 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the MOSFET turn-on to be locked to the rising edge
of an external frequency source. The frequency range of
the voltage-controlled oscillator is 350kHz to 750kHz. The
phase detector used is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector will not
lock up on input frequencies close to the harmonics of the
VCO center frequency. The PLL hold-in range
f
H
is equal
to the capture range,
f
H
=
f
C
=
200kHz.
The output of the phase detector is a pair of complemen-
tary current sources charging or discharging the external
filter network on the PLL_LPF pin. The relationship be-
tween the voltage on the PLL_LPF pin and operating
frequency is shown in Figure 5. A simplified block diagram
is shown in Figure 6.
Figure 4. Setting the LTC1879 Output Voltage
V
FB
LTC1879
0.8V
V
OUT
10V
SGND
R2
1879 F04
R1
V
PLLLPF
(V)
0
OSC FREQUECNY (kHz)
1000
900
800
700
600
500
400
300
200
100
0
1879 F05
0.5
1
1.5
2
DIGITAL
PHASE/
FREQUENCY
DETECTOR
SYNC/
MODE
PLL_LPF
2.4V
C
LP
1879 F06
R
LP
VCO
13
LTC1879
1879f
Where
1,
2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC1879 circuits: supply quiescent currents and
I
2
R losses. The supply quiescent current loss dominates
the efficiency loss at very low load current whereas the I
2
R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 7.
1. The supply quiescent current is due to two compo-
nents: the DC bias current as given in the Electrical
Characteristics and the internal main switch and syn-
chronous switch gate charge currents. The gate charge
current results from switching the gate capacitance of
the internal power MOSFET switches. Each time the
gate is switched from high to low to high again, a
packet of charge dQ moves from PV
IN
to ground. The
resulting dQ/dt is the current out of PV
IN
that is typically
larger than the DC bias current. In continuous mode,
I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate
charges of the internal top and bottom switches. Both
the DC bias and gate charge losses are proportional to
supply voltage and thus their effects will be more
pronounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches R
SW
and external inductor R
L
. In
continuous mode the average output current flowing
through inductor L is "chopped" between the main
switch and the synchronous switch. Thus, the series
resistance looking into SW pins is a function of both top
and bottom MOSFET R
DS(ON)
and the duty cycle (DC) as
follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses, MOSFET switching losses and inductor core losses
generally account for less than 2% total additional loss.
Thermal Considerations
In most applications, the LTC1879 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC1879 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150
C, both power switches
will be turned off and the SW nodes will become high
impedance.
To avoid the LTC1879 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. Normally,
some iterative calculation is required to determine a rea-
sonably accurate value. The temperature rise is given by:
T
R
= P
JA
where P is the power dissipated by the regulator and
JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature is given by:
T
J
= T
A
+ T
R
APPLICATIO S I FOR ATIO
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Figure 7. Power Lost vs Load Current
LOAD CURRENT (mA)
0.1
0.0001
0.001
0.01
0.1
1
POWER LOST (W)
1
10
100
1000
1879 F07
V
IN
= 6V
V
OUT
= 3.3V
L = 6.8
H
Burst Mode OPERATION
14
LTC1879
1879f
where T
A
is the ambient temperature. Because the power
transistor R
DS(ON)
is a function of temperature, it is
usually necessary to iterate 2 to 3 times through the
equations to achieve a reasonably accurate value for the
junction temperature.
As an example, consider the LTC1879 in dropout at an
input voltage of 5V, a load current of 0.8A and an ambient
temperature of 70
C. From the typical performance graph
of switch resistance, the R
DS(ON)
of the P-channel switch
at 70
C is 0.38
. Therefore, power dissipated by the IC is:
P = I
2
R
DS(ON)
= 0.243W
For the SSOP package, the
JA
is 140
C/W. Thus the
junction temperature of the regulator is:
T
J
= 70
C + (0.243)(140) = 104
C
However, at this temperature, the R
DS(ON)
is actually
0.42
.
Therefore:
T
J
= 70
C + (0.269)(140) = 108
C
which is below the maximum junction temperature of
125
C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (
I
LOAD
ESR), where ESR is the effective series
resistance of C
OUT
.
I
LOAD
also begins to charge or
discharge C
OUT
, generating a feedback error signal. The
regulator loop then acts to return V
OUT
to its steady-state
value. During this recovery time, V
OUT
can be monitored
for overshoot or ringing that would indicate a stability
problem. The I
TH
pin can be used for external compensa-
tion as shown in Figure 9. (The capacitor, C
C2
, is typically
needed for noise decoupling.)
A second, more severe transient is caused by switching in
loads with large (> 1
F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 C
LOAD
).
Thus, a 10
F capacitor charging to 3.3V would require a
250
s rise time, limiting the charging current to about
130mA.
APPLICATIO S I FOR ATIO
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LTC1879
1879f
APPLICATIO S I FOR ATIO
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PC Board Layout Checklist
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. Figure 8 is a
sample of PC board layout for the design example shown
in Figure 9. A 4-layer PC board is used in this design.
Several guidelines are followed in this layout:
1. In order to minimize switching noise and improve
output load regulation, the PGND pins of the LTC1879
should be connected directly to 1) the negative terminal
of the output decoupling capacitors, 2) the negative
terminal of the input capacitor and 3) vias to the ground
plane immediately adjacent to Pins 1, 7 and 10. The
ground trace on the top layer of the PC board should be
as wide and short as possible to minimize series resis-
tance and inductance.
2. Beware of ground loops in multiple layer PC boards. Try
to maintain one central ground node on the board and
use the input capacitor to avoid excess input ripple for
high output current power supplies. If the ground is to
be used for high DC currents, choose a path away from
the small-signal components.
3. The high di/dt loop from the top terminal of the input
capacitor, through the power MOSFETs and back to the
input capacitor should be kept as tight as possible to
reduce inductive ringing. Excess inductance can cause
increased stress on the power MOSFET and increase
noise on the input. If low ESR ceramic capacitors are
used to reduce input noise, place these capacitors close
to the DUT in order to keep the series inductance to a
minimum.
4. Place the small-signal components away from high
frequency switching nodes. In the layout shown in
Figure 8, all of the small-signal components have been
placed on one side of the IC and all of the power
components have been placed on the other.
5. For optimum load regulation and true sensing, the top
of the output resistor divider should connect indepen-
dently to the top of the output capacitor (Kelvin connec-
tion), staying away from any high dV/dt traces. Place
the divider resistors near the LTC1879 in order to keep
the high impedance FB node short.
Figure 8. Typical Application and Suggested Layout (Topside Only)
DUT
R
SVIN
R
PL
PGND
V
OUT
V
IN
C
OUT
C
IN2
C
IN1
L1
R
PG
C
PL
C
C2
R
C
C
C1
R
FB2
R
SS
C
SS
R
FB1
VIA CONNECTION TO R
FB1
VIAS TO GND PLANE
VIAS TO GND PLANE
1879 F08
16
LTC1879
1879f
APPLICATIO S I FOR ATIO
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Design Example
As a design example, assume the LTC1879 is used in a
dual lithium-ion battery-powered cellular phone applica-
tion. The V
IN
will be operating from a maximum of 8.4V
down to about 2.65V. The load current requirement is a
maximum of 0.7A but most of the time it will be on standby
mode, requiring only 2mA. Efficiency at both low and high
load currents is important. Output voltage is 2.5V. With
this information we can calculate L using equation (1),
L
f
I
V
V
V
L
OUT
OUT
IN
=
( )
( )
1
1
(3)
Substituting V
OUT
= 2.5V, V
IN
= 8.4V,
I
L
= 210mA and
f = 550kHz in equation (3) gives:
L
V
kHz
mA
V
V
H
=
=
2 5
550
210
1
2 5
8 4
15 2
.
.
.
.
An 15
H inductor works well for this application. For good
efficiency choose a 1.5A inductor with less than 0.125
series resistance.
C
IN
will require an RMS current rating of at least 0.35A at
temperature and C
OUT
will require an ESR of less than
0.125
. In most applications, the requirements for these
capacitors are fairly similar.
For the feedback resistors, choose R2 = 412k. R1 can then
be calculated from equation (2) to be:
R
V
R
k use
k
OUT
1
0 8
1
2
875 5
887
=
=
.
. ,
Figure 9 shows the complete circuit along with its effi-
ciency curve.
17
LTC1879
1879f
Figure 9a. Dual Lithium-Ion/8V Wall Adapter to 2.5V/0.7A Regulator from Design Example
APPLICATIO S I FOR ATIO
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Figure 9b. Efficiency vs Output Current for Design Example
5
12
6
11
3
1
1879 F09a
SWP
SWP
SWN
SWN
V
FB
I
TH
R
C
150k
PLL_LPF
RUN/SS
PGOOD
SGND
8
9
PV
IN
PV
IN
7
10
PGND
PGND
SYNC/MODE
R
SVIN
10
LTC1879
L1
15
H
V
OUT
2.5V
0.7A
V
IN
2.65V TO 8.4V
GND
R1
887k
R2
412k
C
IN1
10
F
C
OUT
47
F
15
13
14
2
16
4
SV
IN
C
SVIN
0.1
F
C
C1
47pF
BOLD LINES INDICATE HIGH CURRENT PATHS
C
C2
220pF
C
IN1
, C
IN2
: TAIYO YUDEN CERAMIC JMK316BJ106ML
C
OUT
: TDK CERAMIC C4532X5R0J476M
L1: TOKO A921CY-150M
V
OUT
: 0.7A IS THE MAXIMUM OUTPUT CURRENT
R
SS
1M
R
PG
100k
C
SS
0.1
F
C
IN2
10
F
OUTPUT CURRENT (mA)
70
EFFICIENCY (%)
80
100
0.1
10
100
1000
1879 F09b
60
1
90
V
IN
= 3.6V
V
OUT
= 2.5V
L = 15
H
18
LTC1879
1879f
TYPICAL APPLICATIO
U
Dual Li-Ion to 1.8V/1A Regulator Using All Ceramic Capacitors
5
12
6
11
3
1
1879 TA02
SWP
SWP
SWN
SWN
V
FB
I
TH
R
C
150k
PLL_LPF
RUN/SS
PGOOD
SGND
8
9
PV
IN
PV
IN
7
10
PGND
PGND
SYNC/MODE
R
SVIN
10
LTC1879
L1
8.2
H
V
OUT
1.8V
1A
V
IN
3V TO 8.4V
GND
C
IN1
10
F
C
OUT
47
F
15
13
14
2
16
4
SV
IN
C
SVIN
0.1
F
C
C1
47pF
BOLD LINES INDICATE HIGH CURRENT PATHS
C
C2
220pF
C
IN1
, C
IN2
: TAIYO YUDEN CERAMIC LMK325BJ106MN
C
OUT
: TDK CERAMIC C4532X5R0J476M
L1: TOKO A916CY-8R2M
V
OUT
: 1A IS THE MAXIMUM OUTPUT CURRENT
R
SS
1M
R
PG
100k
C
SS
0.1
F
C
IN2
10
F
R1
523k
R2
412k
OUTPUT CURRENT (mA)
60
EFFICIENCY (%)
80
100
50
70
90
0.1
10
100
1000
1879 TA04
40
1
V
IN
= 3.6V
V
IN
= 7.2V
V
IN
= 5V
V
OUT
= 1.8V
Burst Mode OPERATION
Efficiency vs Output Current
19
LTC1879
1879f
PACKAGE DESCRIPTIO
N
U
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
GN16 (SSOP) 0502
1
2
3
4
5
6
7
8
.229 .244
(5.817 6.198)
.150 .157**
(3.810 3.988)
16 15 14 13
.189 .196*
(4.801 4.978)
12 11 10 9
.016 .050
(0.406 1.270)
.015
.004
(0.38
0.10)
45
0
8
TYP
.007 .0098
(0.178 0.249)
.053 .068
(1.351 1.727)
.008 .012
(0.203 0.305)
.004 .0098
(0.102 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 .165
.0250 TYP
.0165
.0015
.045
.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
20
LTC1879
1879f
LINEAR TECHNOLOGY CORPORATION 2001
LT/TP 0303 2K PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear.com
TYPICAL APPLICATIO
U
5-Cell NiMH to 3.3V/0.25A ZETA Regulator Using All Ceramic Capacitors
5
12
6
11
3
1
1879 TA03
SWP
SWP
SWN
SWN
V
FB
I
TH
R
C
150k
PLL_LPF
RUN/SS
PGOOD
SGND
8
9
PV
IN
PV
IN
7
10
PGND
PGND
SYNC/MODE
R
SVIN
10
LTC1879
L1
4.7
H
L1
V
OUT
3.3V
0.25A
V
IN
2.8V TO 7.5V
GND
C
IN1
10
F
C
OUT
47
F
15
13
14
2
16
4
SV
IN
C
SVIN
0.1
F
C
C1
47pF
BOLD LINES INDICATE HIGH CURRENT PATHS
C
C2
220pF
C
C
: TAIYO YUDEN CERAMIC LMK325BJ106MN
C
IN1
, C
IN2
: TAIYO YUDEN CERAMIC LMK325BJ106MN
C
OUT
: TDK CERAMIC C4532X5R0J476M
L1: COILTRONICS CTX5-4
R
SS
1M
R
PG
100k
C
SS
0.1
F
C
IN2
10
F
C
C
10
F
R1
1.3M
R2
412k
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ThinSOT is a trademark of Linear Technology Corporation.
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