LTC2410
1
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
The LTC
2410 is a 2.7V to 5.5V micropower 24-bit
differential
analog to digital converter with an inte-
grated oscillator, 2ppm INL and 0.16ppm RMS noise. It
uses delta-sigma technology and provides single cycle
settling time for multiplexed applications. Through a
single pin, the LTC2410 can be configured for better than
110dB input differential mode rejection at 50Hz or 60Hz
2%, or it can be driven by an external oscillator for a user
defined rejection frequency. The internal oscillator re-
quires no external frequency setting components.
The converter accepts any external differential reference
voltage from 0.1V to V
CC
for flexible ratiometric and
remote sensing measurement configurations. The full-
scale differential input range is from 0.5V
REF
to 0.5V
REF
.
The reference common mode voltage, V
REFCM
, and the
input common mode voltage, V
INCM
, may be indepen-
dently set anywhere within the GND to V
CC
range of the
LTC2410. The DC common mode input rejection is better
than 140dB.
The LTC2410 communicates through a flexible 3-wire
digital interface which is compatible with SPI and
MICROWIRE
TM
protocols.
s
Direct Sensor Digitizer
s
Weight Scales
s
Direct Temperature Measurement
s
Gas Analyzers
s
Strain-Gage Transducers
s
Instrumentation
s
Data Acquisition
s
Industrial Process Control
s
6-Digit DVMs
, LTC and LT are registered trademarks of Linear Technology Corporation.
s
Differential Input and Differential Reference with
GND to V
CC
Common Mode Range
s
2ppm INL, No Missing Codes
s
2.5ppm Full-Scale Error
s
0.1ppm Offset
s
0.16ppm Noise
s
Single Conversion Settling Time for Multiplexed
Applications
s
Internal Oscillator--No External Components
Required
s
110dB Min, 50Hz/60Hz Notch Filter
s
24-Bit ADC in Narrow SSOP-16 Package
(SO-8 Footprint)
s
Single Supply 2.7V to 5.5V Operation
s
Low Supply Current (200
A) and Auto Shutdown
s
Fully Differential Version of LTC2400
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
24-Bit No Latency
TM
ADC
with Differential Input and
Differential Reference
April 2000
Final Electrical Specifications
No Latency
is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
V
CC
F
O
REF
+
REF
SCK
IN
+
IN
SDO
GND
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
0.5V
REF
TO 0.5V
REF
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
3-WIRE
SPI INTERFACE
1
F
2.7V TO 5.5V
LTC2410
2410 TA01
V
CC
LTC2410
IN
+
REF
+
V
CC
REF
V
CC
GND
F
O
IN
1
F
SDO
3-WIRE
SPI INTERFACE
SCK
2410 TA02
CS
12
3
2
1, 7, 8
9, 10,
15, 16
14
5
6
4
13
11
BRIDGE
IMPEDANCE
100
TO10k
TYPICAL APPLICATIO S
U
LTC2410
2
ABSOLUTE AXI U
RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
ELECTRICAL CHARACTERISTICS
(Notes 1, 2)
ORDER PART NUMBER
Consult factory for Military grade parts.
Supply Voltage (V
CC
) to GND ....................... 0.3V to 7V
Analog Input Pins Voltage
to GND .................................... 0.3V to (V
CC
+ 0.3V)
Reference Input Pins Voltage
to GND .................................... 0.3V to (V
CC
+ 0.3V)
Digital Input Voltage to GND ........ 0.3V to (V
CC
+ 0.3V)
Digital Output Voltage to GND ..... 0.3V to (V
CC
+ 0.3V)
Operating Temperature Range
LTC2410C ............................................... 0
C to 70
C
LTC2410I ............................................ 40
C to 85
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec).................. 300
C
T
JMAX
= 125
C,
JA
= 95
C/W
LTC2410CGN
LTC2410IGN
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
0.1V
V
REF
V
CC
, 0.5 V
REF
V
IN
0.5 V
REF
, (Note 5)
q
24
Bits
Integral Nonlinearity
REF
+
= 2.5V, REF
= GND, V
INCM
= 1.25V, (Note 6)
q
1
ppm of V
REF
5V
V
CC
5.5V, REF
+
= 5V, REF
= GND, V
INCM
= 2.5V, (Note 6)
q
2
14
ppm of V
REF
Offset Error
2.5V
REF
+
V
CC
, REF
= GND,
q
0.5
2.5
V
GND
IN
+
= IN
V
CC
, (Note 14)
Offset Error Drift
2.5V
REF
+
V
CC
, REF
= GND,
10
nV/
C
GND
IN
+
= IN
V
CC
Positive Full-Scale Error
2.5V
REF
+
V
CC
, REF
= GND,
q
2.5
12
ppm of V
REF
IN
+
= 0.75REF
+
, IN
= 0.25 REF
+
Positive Full-Scale Error Drift
2.5V
REF
+
V
CC
, REF
= GND,
0.04
ppm of V
REF
/
C
IN
+
= 0.75REF
+
, IN
= 0.25 REF
+
Negative Full-Scale Error
2.5V
REF
+
V
CC
, REF
= GND,
q
2.5
12
ppm of V
REF
IN
+
= 0.25 REF
+
, IN
= 0.75 REF
+
Negative Full-Scale Error Drift
2.5V
REF
+
V
CC
, REF
= GND,
0.04
ppm of V
REF
/
C
IN
+
= 0.25 REF
+
, IN
= 0.75 REF
+
Total Unadjusted Error
REF
+
= 2.5V, REF
= GND, V
INCM
= 1.25V
5
ppm of V
REF
5V
V
CC
5.5V, REF
+
= 5V, REF
= GND, V
INCM
= 2.5V
10
ppm of V
REF
Output Noise
5V
V
CC
5.5V, REF
+
= 5V, V
REF
= GND,
0.8
V
RMS
GND
IN
= IN
+
5V, (Note 13)
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. (Notes 3, 4)
GN PART MARKING
2410
2410I
TOP VIEW
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
V
CC
REF
+
REF
IN
+
IN
GND
GND
GND
GND
F
O
SCK
SDO
CS
GND
GND
LTC2410
3
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IN
+
Absolute/Common Mode IN
+
Voltage
q
GND 0.3V
V
CC
+ 0.3V
V
IN
Absolute/Common Mode IN
Voltage
q
GND 0.3V
V
CC
+ 0.3V
V
V
IN
Input Differential Voltage Range
q
V
REF
/2
V
REF
/2
V
(IN
+
IN
)
REF
+
Absolute/Common Mode REF
+
Voltage
q
0.1
V
CC
V
REF
Absolute/Common Mode REF
Voltage
q
GND
V
CC
0.1V
V
V
REF
Reference Differential Voltage Range
q
0.1
V
CC
V
(REF
+
REF
)
C
S
(IN
+
)
IN
+
Sampling Capacitance
18
pF
C
S
(IN
)
IN
Sampling Capacitance
18
pF
C
S
(REF
+
)
REF
+
Sampling Capacitance
18
pF
C
S
(REF
)
REF
Sampling Capacitance
18
pF
I
DC_LEAK
(IN
+
)
IN
+
DC Leakage Current
CS = V
CC
, IN
+
= GND
q
10
1
10
nA
I
DC_LEAK
(IN
)
IN
DC Leakage Current
CS = V
CC
, IN
= GND
q
10
1
10
nA
I
DC_LEAK
(REF
+
)
REF
+
DC Leakage Current
CS = V
CC
, REF
+
= 5V
q
10
1
10
nA
I
DC_LEAK
(REF
)
REF
DC Leakage Current
CS = V
CC
, REF
= GND
q
10
1
10
nA
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. (Note 3)
Input Common Mode Rejection DC
2.5V
REF
+
V
CC
, REF
= GND,
q
130
140
dB
GND
IN
= IN
+
5V
Input Common Mode Rejection
2.5V
REF
+
V
CC
, REF
= GND,
q
140
dB
60Hz
2%
GND
IN
= IN
+
5V, (Note 7)
Input Common Mode Rejection
2.5V
REF
+
V
CC
, REF
= GND,
q
140
dB
50Hz
2%
GND
IN
= IN
+
5V, (Note 8)
Input Normal Mode Rejection
(Note 7)
q
110
140
dB
60Hz
2%
Input Normal Mode Rejection
(Note 8)
q
110
140
dB
50Hz
2%
Reference Common Mode
2.5V
REF
+
V
CC
, GND
REF
2.5V,
q
130
140
dB
Rejection DC
V
REF
= 2.5V, IN
= IN
+
= GND
Power Supply Rejection, DC
REF
+
= 2.5V, REF
= GND, IN
= IN
+
= GND
100
dB
Power Supply Rejection, 60Hz
2%
REF
+
= 2.5V, REF
= GND, IN
= IN
+
= GND, (Note 7)
110
dB
Power Supply Rejection, 50Hz
2%
REF
+
= 2.5V, REF
= GND, IN
= IN
+
= GND, (Note 8)
110
dB
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CO VERTER CHARACTERISTICS
U
A ALOG I PUT A
U
D REFERE CE
U
U
U
LTC2410
4
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
Supply Voltage
q
2.7
5.5
V
I
CC
Supply Current
Conversion Mode
CS = 0V (Note 12)
q
200
300
A
Sleep Mode
CS = V
CC
(Note 12)
q
20
30
A
The
q
denotes specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
C. (Note 3)
The
q
denotes specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25
C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
2.7V
V
CC
5.5V
q
2.5
V
CS, F
O
2.7V
V
CC
3.3V
2.0
V
V
IL
Low Level Input Voltage
4.5V
V
CC
5.5V
q
0.8
V
CS, F
O
2.7V
V
CC
5.5V
0.6
V
V
IH
High Level Input Voltage
2.7V
V
CC
5.5V (Note 9)
q
2.5
V
SCK
2.7V
V
CC
3.3V (Note 9)
2.0
V
V
IL
Low Level Input Voltage
4.5V
V
CC
5.5V (Note 9)
q
0.8
V
SCK
2.7V
V
CC
5.5V (Note 9)
0.6
V
I
IN
Digital Input Current
0V
V
IN
V
CC
q
10
10
A
CS, F
O
I
IN
Digital Input Current
0V
V
IN
V
CC
(Note 9)
q
10
10
A
SCK
C
IN
Digital Input Capacitance
10
pF
CS, F
O
C
IN
Digital Input Capacitance
(Note 9)
10
pF
SCK
V
OH
High Level Output Voltage
I
O
= 800
A
q
V
CC
0.5V
V
SDO
V
OL
Low Level Output Voltage
I
O
= 1.6mA
q
0.4V
V
SDO
V
OH
High Level Output Voltage
I
O
= 800
A (Note 10)
q
V
CC
0.5V
V
SCK
V
OL
Low Level Output Voltage
I
O
= 1.6mA (Note 10)
q
0.4V
V
SCK
I
OZ
Hi-Z Output Leakage
q
10
10
A
SDO
DIGITAL I PUTS A D DIGITAL OUTPUTS
U
U
POWER REQUIRE E TS
W
U
LTC2410
5
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: V
CC
= 2.7 to 5.5V unless otherwise specified.
V
REF
= REF
+
REF
, V
REFCM
= (REF
+
+ REF
)/2;
V
IN
= IN
+
IN
, V
INCM
= (IN
+
+ IN
)/2.
Note 4: F
O
pin tied to GND or to V
CC
or to external conversion clock
source with f
EOSC
= 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: F
O
= 0V (internal oscillator) or f
EOSC
= 153600Hz
2%
(external oscillator).
Note 8: F
O
= V
CC
(internal oscillator) or f
EOSC
= 128000Hz
2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is f
ESCK
and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance C
LOAD
= 20pF.
Note 11: The external oscillator is connected to the F
O
pin. The external
oscillator frequency, f
EOSC
, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
F
O
= 0V or F
O
= V
CC
.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
f
EOSC
External Oscillator Frequency Range
q
2.56
2000
kHz
t
HEO
External Oscillator High Period
q
0.25
390
s
t
LEO
External Oscillator Low Period
q
0.25
390
s
t
CONV
Conversion Time
F
O
= 0V
q
130.86
133.53
136.20
ms
F
O
= V
CC
q
157.03
160.23
163.44
ms
External Oscillator (Note 11)
q
20510/f
EOSC
(in kHz)
ms
f
ISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
19.2
kHz
External Oscillator (Notes 10, 11)
f
EOSC
/8
kHz
D
ISCK
Internal SCK Duty Cycle
(Note 10)
q
45
55
%
f
ESCK
External SCK Frequency Range
(Note 9)
q
2000
kHz
t
LESCK
External SCK Low Period
(Note 9)
q
250
ns
t
HESCK
External SCK High Period
(Note 9)
q
250
ns
t
DOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
q
1.64
1.67
1.70
ms
External Oscillator (Notes 10, 11)
q
256/f
EOSC
(in kHz)
ms
t
DOUT_ESCK
External SCK 32-Bit Data Output Time
(Note 9)
q
32/f
ESCK
(in kHz)
ms
t
1
CS
to SDO Low Z
q
0
200
ns
t2
CS
to SDO High Z
q
0
200
ns
t3
CS
to SCK
(Note 10)
q
0
200
ns
t4
CS
to SCK
(Note 9)
q
50
ns
t
KQMAX
SCK
to SDO Valid
q
220
ns
t
KQMIN
SDO Hold After SCK
(Note 5)
q
15
ns
t
5
SCK Set-Up Before CS
q
50
ns
t
6
SCK Hold After CS
q
50
ns
The
q
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TI I G CHARACTERISTICS
W
U
LTC2410
6
GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple
ground pins internally connected for optimum ground
current flow and V
CC
decoupling. Connect each one of
these pins to a ground plane through a low impedance
connection.
V
CC
(Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 1) with a 10
F tantalum capacitor in parallel with
0.1
F ceramic capacitor as close to the part as possible.
REF
+
(Pin 3), REF
(Pin 4): Differential Reference Input.
The voltage on these pins can have any value between GND
and V
CC
as long as the reference positive input, REF
+
, is
maintained more positive than the reference negative
input, REF
, by at least 0.1V.
IN
+
(Pin 5), IN
(Pin 6): Differential Analog Input. The
voltage on these pins can have any value between
GND 0.3V and V
CC
+ 0.3V. Within these limits the
converter bipolar input range (V
IN
= IN
+
IN
) extends
from 0.5 (V
REF
) to 0.5 (V
REF
). Outside this input range
the converter produces unique overrange and underrange
output codes.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
CC
) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
F
O
(Pin 14): Frequency Control Pin. Digital input that
controls the ADC's notch frequencies and conversion
time. When the F
O
pin is connected to V
CC
(F
O
= V
CC
), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the F
O
pin is connected
to GND (F
O
= OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When F
O
is driven by an external clock signal with a frequency f
EOSC
,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency f
EOSC
/2560.
PI FU CTIO S
U
U
U
LTC2410
7
TEST CIRCUITS
APPLICATIO S I FOR ATIO
W
U
U
U
FU CTIO AL BLOCK DIAGRA
U
U
W
Figure 1. LTC2410 State Transition Diagram
CONVERTER OPERATION
Converter Operation Cycle
The LTC2410 is a low power, delta-sigma analog-to-
digital converter with an easy to use 3-wire serial interface.
Its operation is made up of three states. The converter
operating cycle begins with the conversion, followed by
the low power sleep state and ends with the data output
(see Figure 1). The 3-wire interface consists of serial data
output (SDO), serial clock (SCK) and chip select (CS).
Initially, the LTC2410 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced by
an order of magnitude. The part remains in the sleep state
as long as CS is HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
AUTOCALIBRATION
AND CONTROL
DAC
DECIMATING FIR
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
ADC
GND
V
CC
IN
+
IN
SDO
SCK
REF
+
REF
CS
F
O
(INT/EXT)
2410 FD
+
+
1.69k
SDO
2410 TA04
Hi-Z TO V
OL
V
OH
TO V
OL
V
OL
TO Hi-Z
C
LOAD
= 20pF
V
CC
1.69k
SDO
2410 TA03
Hi-Z TO V
OH
V
OL
TO V
OH
V
OH
TO Hi-Z
C
LOAD
= 20pF
CONVERT
SLEEP
DATA OUTPUT
2410 F01
TRUE
FALSE CS = LOW
AND
SCK
LTC2410
8
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion just
performed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK). Data
is updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 32 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion and the cycle
repeats.
Through timing control of the CS and SCK pins, the
LTC2410 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50 or 60Hz
plus their harmonics. The filter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2410 incorporates a highly accurate on-
chip oscillator. This eliminates the need for external fre-
quency setting components such as crystals or oscilla-
tors. Clocked by the on-chip oscillator, the LTC2410
achieves a minimum of 110dB rejection at the line fre-
quency (50Hz or 60Hz
2%).
Ease of Use
The LTC2410 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2410 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation de-
scribed above. The advantage of continuous calibration is
extreme stability of offset and full-scale readings with re-
spect to time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2410 automatically enters an internal reset state
when the power supply voltage V
CC
drops below approxi-
mately 2.2V. This feature guarantees the integrity of the
conversion result and of the serial interface mode selec-
tion. (See the 2-wire I/O sections in the Serial Interface
Timing Modes section.)
When the V
CC
voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 0.5ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2410 starts a normal conversion cycle and
follows the succession of states described above. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
This converter accepts a truly differential external refer-
ence voltage. The absolute/common mode voltage speci-
fication for the REF
+
and REF
pins covers the entire range
from GND to V
CC
. For correct converter operation, the
REF
+
pin must always be more positive than the REF
pin.
The LTC2410 can accept a differential reference voltage
from 0.1V to V
CC
. The converter output noise is deter-
mined by the thermal noise of the front-end circuits, and
as such, its value in nanovolts is nearly constant with
reference voltage. A decrease in reference voltage will not
significantly improve the converter's effective resolution.
On the other hand, a reduced reference voltage will im-
prove the converter's overall INL performance. A reduced
reference voltage will also improve the converter perfor-
mance when operated with an external conversion clock
(external F
O
signal) at substantially higher output data
rates (see the Output Data Rate section).
APPLICATIO S I FOR ATIO
W
U
U
U
LTC2410
9
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN
+
and IN
input pins
extending from GND 0.3V to V
CC
+ 0.3V. Outside
these limits the ESD protection devices begin to turn on
and the errors due to input leakage current increase
rapidly. Within these limits the LTC2410 converts the
bipolar differential input signal, V
IN
= IN
+
IN
, from
FS = 0.5 V
REF
to +FS = 0.5 V
REF
where V
REF
=
REF
+
REF
. Outside this range the converter indicates the
overrange or the underrange condition using distinct
output codes.
Input signals applied to IN
+
and IN
pins may extend by
300mV below ground and above V
CC
. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN
+
and IN
pins without affecting the perfor-
mance of the device. In the physical layout, it is important
to maintain the parasitic capacitance of the connection
between these series resistors and the corresponding pins
as low as possible; therefore, the resistors should be
located as close as practical to the pins. The effect of the
series resistance on the converter accuracy can be evalu-
ated from the curves presented in the Input Current/
Reference Current sections. In addition, series resistors
will introduce a temperature dependent offset error due to
the input leakage current. A 1nA input leakage current will
develop a 1ppm offset error on a 5k resistor if V
REF
= 5V.
This error has a very strong temperature dependency.
Output Data Format
The LTC2410 serial output data stream is 32 bits long. The
first 3 bits represent status information indicating the sign
and conversion state. The next 24 bits are the conversion
result, MSB first. The remaining 5 bits are sub LSBs
beyond the 24-bit level that may be included in averaging
or discarded without loss of resolution. The third and
fourth bit together are also used to indicate an underrange
condition (the differential input voltage is below FS) or an
overrange condition (the differential input voltage is above
+FS).
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2410 Status Bits
Bit 31
Bit 30 Bit 29 Bit 28
Input Range
EOC
DMY
SIG
MSB
V
IN
0.5 V
REF
0
0
1
1
0V
V
IN
< 0.5 V
REF
0
0
1
0
0.5 V
REF
V
IN
< 0V
0
0
0
1
V
IN
< 0.5 V
REF
0
0
0
0
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on the
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 31st SCK and may be latched
APPLICATIO S I FOR ATIO
W
U
U
U
LTC2410
10
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN
+
and IN
pins is maintained
within the 0.3V to (V
CC
+ 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage V
IN
from FS = 0.5 V
REF
to
+FS = 0.5 V
REF
. For differential input voltages greater than
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below FS, the conversion result is clamped to the value
corresponding to FS 1LSB.
Frequency Rejection Selection (F
O
)
The LTC2410 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics for 50Hz
2% or 60Hz
2%. For 60Hz rejec-
tion, F
O
should be connected to GND while for 50Hz
rejection the F
O
pin should be connected to V
CC
.
The selection of 50Hz or 60Hz rejection can also be made
by driving F
O
to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
Table 2. LTC2410 Output Data Format
Differential Input Voltage
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
...
Bit 0
V
IN
*
EOC
DMY
SIG
MSB
V
IN
*
0.5 V
REF
**
0
0
1
1
0
0
0
...
0
0.5 V
REF
** 1LSB
0
0
1
0
1
1
1
...
1
0.25 V
REF
**
0
0
1
0
1
0
0
...
0
0.25 V
REF
** 1LSB
0
0
1
0
0
1
1
...
1
0
0
0
1
0
0
0
0
...
0
1LSB
0
0
0
1
1
1
1
...
1
0.25 V
REF
**
0
0
0
1
1
0
0
...
0
0.25 V
REF
** 1LSB
0
0
0
1
0
1
1
...
1
0.5 V
REF
**
0
0
0
1
0
0
0
...
0
V
IN
* < 0.5 V
REF
**
0
0
0
0
1
1
1
...
1
*The differential input voltage V
IN
= IN
+
IN
.
**The differential reference voltage V
REF
= REF
+
REF
.
Figure 3. Output Data Timing
APPLICATIO S I FOR ATIO
W
U
U
U
MSB
SIG
"0"
1
2
3
4
5
26
27
32
BIT 0
BIT 27
BIT 5
LSB
24
BIT 28
BIT 29
BIT 30
SDO
SCK
CS
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
2410 F03
Hi-Z
LTC2410
11
synchronized with an outside source, the LTC2410 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the F
O
pin and turns off the internal oscillator. The
frequency f
EOSC
of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The exter-
nal clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods t
HEO
and t
LEO
are observed.
While operating with an external conversion clock of a
frequency f
EOSC
, the LTC2410 provides better than 110dB
normal mode rejection in a frequency range f
EOSC
/2560
4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f
EOSC
/2560
is shown in Figure 4.
Whenever an external clock is not present at the F
O
pin the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2410
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of F
O
.
SERIAL INTERFACE PINS
The LTC2410 transmits the conversion results and re-
ceives the start of conversion command through a syn-
chronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Table 3. LTC2410 State Duration
State
Operating Mode
Duration
CONVERT
Internal Oscillator
F
O
= LOW
133ms, Output Data Rate
7.5 Readings/s
(60Hz Rejection)
F
O
= HIGH
160ms, Output Data Rate
6.2 Readings/s
(50Hz Rejection)
External Oscillator
F
O
= External Oscillator
20510/f
EOSC
s, Output Data Rate
f
EOSC
/20510 Readings/s
with Frequency f
EOSC
kHz
(f
EOSC
/2560 Rejection)
SLEEP
As Long As CS = HIGH Until CS = LOW and SCK
DATA OUTPUT
Internal Serial Clock
F
O
= LOW/HIGH
As Long As CS = LOW But Not Longer Than 1.67ms
(Internal Oscillator)
(32 SCK cycles)
F
O
= External Oscillator with
As Long As CS = LOW But Not Longer Than 256/f
EOSC
ms
Frequency f
EOSC
kHz
(32 SCK cycles)
External Serial Clock with
As Long As CS = LOW But Not Longer Than 32/f
SCK
ms
Frequency f
SCK
kHz
(32 SCK cycles)
Figure 4. LTC2410 Normal Mode Rejection When
Using an External Oscillator of Frequency f
EOSC
APPLICATIO S I FOR ATIO
W
U
U
U
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
EOSC
/2560(%)
12
8
4
0
4
8
12
NORMAL MODE REJECTION (dB)
2410 F04
80
85
90
95
100
105
110
115
120
125
130
135
140
LTC2410
12
APPLICATIO S I FOR ATIO
W
U
U
U
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 13) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2410 creates its own serial clock by
dividing the internal conversion clock by 8. In the External
SCK mode of operation, the SCK pin is used as input. The
internal or external SCK mode is selected on power-up and
then reselected every time a HIGH-to-LOW transition is
detected at the CS pin. If SCK is HIGH or floating at power-
up or during this transition, the converter enters the inter-
nal SCK mode. If SCK is LOW at power-up or during this
transition, the converter enters the external SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 12), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 11) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 11), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2410 will abort any serial data
transfer in progress and start a new conversion cycle
anytime a LOW-to-HIGH transition is detected at the CS
pin after the converter has entered the data output state
(i.e., after the first rising edge of SCK occurs with
CS = LOW).
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by F
O
. Tying a
capacitor to CS will reduce the output rate and power
dissipation by a factor proportional to the capacitor's
value, see Figures 12 to 14.
SERIAL INTERFACE TIMING MODES
The LTC2410's 3-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
operation. These include internal/external serial clock,
2- or 3-wire I/O, single cycle conversion and autostart. The
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (F
O
= LOW or F
O
= HIGH) or
an external oscillator connected to the F
O
pin. Refer to
Table 4 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
Table 4. LTC2410 Interface Timing Modes
Conversion
Data
Connection
SCK
Cycle
Output
and
Configuration
Source
Control
Control
Waveforms
External SCK, Single Cycle Conversion
External
CS and SCK
CS and SCK
Figures 5, 6
External SCK, 2-Wire I/O
External
SCK
SCK
Figure 7
Internal SCK, Single Cycle Conversion
Internal
CS
CS
Figures 8, 9
Internal SCK, 2-Wire I/O, Continuous Conversion
Internal
Continuous
Internal
Figure 10
Internal SCK, Autostart Conversion
Internal
C
EXT
Internal
Figure 11
LTC2410
13
APPLICATIO S I FOR ATIO
W
U
U
U
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. Independent of CS, the
device automatically enters the low power sleep state once
the conversion is complete.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. The device remains in the sleep state until the first
rising edge of SCK is seen while CS is LOW. Data is shifted
out the SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 32nd rising edge of SCK. On the 32nd falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
32nd falling edge of SCK, see Figure 6. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for sys-
tems not requiring all 32 bits of output data, aborting an
invalid conversion cycle or synchronizing the start of a
conversion.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V
CC
exceeds 2.2V. The level
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Figure 5. External Serial Clock, Single Cycle Operation
EOC
BIT 31
SDO
SCK
(EXTERNAL)
CS
TEST EOC
SUB LSB
MSB
SIG
BIT 0
LSB
BIT 5
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
SLEEP
DATA OUTPUT
CONVERSION
2410 F05
CONVERSION
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
Hi-Z
Hi-Z
Hi-Z
V
CC
TEST EOC
TEST EOC
V
CC
F
O
REF
+
REF
SCK
IN
+
IN
SDO
GND
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
0.5V
REF
TO 0.5V
REF
1
F
2.7V TO 5.5V
LTC2410
3-WIRE
SPI INTERFACE
LTC2410
14
APPLICATIO S I FOR ATIO
W
U
U
U
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion enters the low power sleep
state. On the falling edge of EOC, the conversion result is
loaded into an internal static shift register. The device
remains in the sleep state until the first rising edge of SCK.
Data is shifted out the SDO pin on each falling edge of SCK
enabling external circuitry to latch data on the rising edge
of SCK. EOC can be latched on the first rising edge of SCK.
On the 32nd falling edge of SCK, SDO goes HIGH (EOC = 1)
indicating a new conversion has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
EOCtest
after the falling edge of CS
(if EOC = 0) or t
EOCtest
after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of t
EOCtest
is 23
s
if the device is using its internal oscillator (F
0
= logic LOW
or HIGH). If F
O
is driven by an external oscillator of
Figure 6. External Serial Clock, Reduced Data Output Length
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
SDO
SCK
(EXTERNAL)
CS
DATA OUTPUT
CONVERSION
SLEEP
SLEEP
TEST EOC
TEST EOC
DATA OUTPUT
Hi-Z
Hi-Z
Hi-Z
CONVERSION
2410 F06
MSB
SIG
BIT 8
BIT 27
BIT 9
BIT 28
BIT 29
BIT 30
EOC
BIT 31
BIT 0
EOC
Hi-Z
V
CC
TEST EOC
V
CC
F
O
REF
+
REF
SCK
IN
+
IN
SDO
GND
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
1
F
2.7V TO 5.5V
LTC2410
LTC2410
15
APPLICATIO S I FOR ATIO
W
U
U
U
Figure 7. External Serial Clock, CS = 0 Operation
Figure 8. Internal Serial Clock, Single Cycle Operation
EOC
BIT 31
SDO
SCK
(EXTERNAL)
CS
MSB
SIG
BIT 0
LSB
24
BIT 5
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
SLEEP
DATA OUTPUT
CONVERSION
2410 F07
CONVERSION
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
V
CC
F
O
REF
+
REF
SCK
IN
+
IN
SDO
GND
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
1
F
2.7V TO 5.5V
LTC2410
SDO
SCK
(INTERNAL)
CS
MSB
SIG
BIT 0
LSB
24
BIT 5
TEST EOC
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
2410 F08
<t
EOCtest
V
CC
10k
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
Hi-Z
Hi-Z
Hi-Z
Hi-Z
V
CC
TEST EOC
V
CC
F
O
REF
+
REF
SCK
IN
+
IN
SDO
GND
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
1
F
2.7V TO 5.5V
LTC2410
LTC2410
16
APPLICATIO S I FOR ATIO
W
U
U
U
frequency f
EOSC
, then t
EOCtest
is 3.6/f
EOSC
. If CS is pulled
HIGH before time t
EOCtest
, the device remains in the sleep
state. The conversion result is held in the internal static
shift register.
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2410's internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2410's internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH
once the external driver goes Hi-Z. On the next CS falling
edge, the device will remain in the internal SCK timing
mode.
Figure 9. Internal Serial Clock, Reduced Data Output Length
SDO
SCK
(INTERNAL)
CS
> t
EOCtest
MSB
SIG
BIT 8
TEST EOC
TEST EOC
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
EOC
BIT 0
SLEEP
DATA OUTPUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DATA OUTPUT
CONVERSION
CONVERSION
SLEEP
2410 F09
<t
EOCtest
V
CC
10k
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
TEST EOC
V
CC
F
O
REF
+
REF
SCK
IN
+
IN
SDO
GND
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
1
F
2.7V TO 5.5V
LTC2410
LTC2410
17
APPLICATIO S I FOR ATIO
W
U
U
U
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0), SCK
will go LOW. Once CS goes HIGH (within the time period
defined above as t
EOCtest
), the internal pull-up is activated.
For a heavy capacitive load on the SCK pin, the internal
pull-up may not be adequate to return SCK to a HIGH level
before CS goes low again. This is not a concern under
normal conditions where CS remains LOW after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V
CC
exceeds 2.2V. An internal
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data output
cycle begins on the first rising edge of SCK and ends after
the 32nd rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used
to shift the conversion result into external circuitry. EOC
can be latched on the first rising edge of SCK and the last
bit of the conversion result can be latched on the 32nd
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
Figure 10. Internal Serial Clock, Continuous Operation
SDO
SCK
(INTERNAL)
CS
LSB
24
MSB
SIG
BIT 5
BIT 0
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
2410 F10
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
V
CC
F
O
REF
+
REF
SCK
IN
+
IN
SDO
GND
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
1
F
2.7V TO 5.5V
LTC2410
LTC2410
18
APPLICATIO S I FOR ATIO
W
U
U
U
Internal Serial Clock, Autostart Conversion
This timing mode is identical to the internal serial clock,
2-wire I/O described above with one additional feature.
Instead of grounding CS, an external timing capacitor is
tied to CS.
While the conversion is in progress, the CS pin is held
HIGH by an internal weak pull-up. Once the conversion is
complete, the device enters the low power sleep state and
an internal 25nA current source begins discharging the
capacitor tied to CS, see Figure 11. The time the converter
spends in the sleep state is determined by the value of the
external timing capacitor, see Figures 12 and 13. Once the
voltage at CS falls below an internal threshold (
1.4V), the
device automatically begins outputting data. The data
output cycle begins on the first rising edge of SCK and
ends on the 32nd rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
After the 32nd rising edge, CS is pulled HIGH and a new
conversion is immediately started. This is useful in appli-
cations requiring periodic monitoring and ultralow power.
Figure 14 shows the average supply current as a function
of capacitance on CS.
It should be noticed that the external capacitor discharge
current is kept very small in order to decrease the con-
verter power dissipation in the sleep state. In the autostart
mode the analog voltage on the CS pin cannot be observed
without disturbing the converter operation using a regular
oscilloscope probe. When using this configuration, it is
important to minimize the external leakage current at the
CS pin by using a low leakage external capacitor and
properly cleaning the PCB surface.
The internal serial clock mode is selected every time the
voltage on the CS pin crosses an internal threshold volt-
age. An internal weak pull-up at the SCK pin is active while
Figure 11. Internal Serial Clock, Autostart Operation
SDO
Hi-Z
Hi-Z
SCK
(INTERNAL)
CS
V
CC
GND
2410 F11
BIT 0
SIG
BIT 29
BIT 30
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
EOC
BIT 31
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
V
CC
F
O
REF
+
REF
SCK
IN
+
IN
SDO
GND
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
1
F
2.7V TO 5.5V
LTC2410
C
EXT
LTC2410
19
APPLICATIO S I FOR ATIO
W
U
U
U
CS is discharging; therefore, the internal serial clock
timing mode is automatically selected if SCK is floating. It
is important to ensure there are no external drivers pulling
SCK LOW while CS is discharging.
PRESERVING THE CONVERTER ACCURACY
The LTC2410 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line frequency perturba-
tions and so on. Nevertheless, in order to preserve the
extreme accuracy capability of this part, some simple
precautions are desirable.
Digital Signal Levels
The LTC2410's digital interface is easy to use. Its digital
inputs (F
O
, CS and SCK in External SCK mode of operation)
accept standard TTL/CMOS logic levels and the internal
hysteresis receivers can tolerate edge rates as slow as
100
s. However, some considerations are required to take
advantage of the exceptional accuracy and low supply
current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(V
CC
0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (F
O
, CS and SCK
in External SCK mode of operation) is within this range, the
LTC2410 power supply current may increase even if the
signal in question is at a valid logic level. For micropower
operation, it is recommended to drive all digital input
signals to full CMOS levels [V
IL
< 0.4V and V
OH
>
(V
CC
0.4V)].
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the LTC2410
pins may severely disturb the analog to digital conversion
process. Undershoot and overshoot can occur because of
the impedance mismatch at the converter pin when the
transition time of an external control signal is less than
twice the propagation delay from the driver to LTC2410.
For reference, on a regular FR-4 board, signal propagation
Figure 12. CS Capacitance vs t
SAMPLE
Figure 13. CS Capacitance vs Output Rate
Figure 14. CS Capacitance vs Supply Current
CAPACITANCE ON CS (pF)
1
5
6
7
1000
10000
2400 F12
4
3
10
100
100000
2
1
0
t
SAMPLE
(SEC)
V
CC
= 5V
V
CC
= 3V
CAPACITANCE ON CS (pF)
0
SAMPLE RATE (Hz)
3
4
5
1000
100000
2400 F13
2
1
0
10
100
10000
6
7
8
V
CC
= 5V
V
CC
= 3V
CAPACITANCE ON CS (pF)
1
0
SUPPLY CURRENT (
A
RMS
)
50
100
150
200
250
300
10
100
1000
10000
2400 F14
100000
V
CC
= 5V
V
CC
= 3V
LTC2410
20
APPLICATIO S I FOR ATIO
W
U
U
U
velocity is approximately 183ps/inch for internal traces
and 170ps/inch for surface traces. Thus, a driver gener-
ating a control signal with a minimum transition time of
1ns must be connected to the converter pin through a
trace shorter than 2.5 inches. This problem becomes
particularly difficult when shared control lines are used
and multiple reflections may occur. The solution is to
carefully terminate all transmission lines close to their
characteristic impedance.
Parallel termination near the LTC2410 pin will eliminate
this problem but will increase the driver power dissipation.
A series resistor between 27
and 56
placed near the
driver or near the LTC2410 pin will also eliminate this
problem without additional power dissipation. The actual
resistor value depends upon the trace impedance and
connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter's sensitivity to ground currents.
Particular attention must be given to the connection of the
F
O
signal when the LTC2410 is used with an external
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals may result into DC gain and INL
errors. A normal mode signal of this frequency at the
converter input terminals may result into a DC offset error.
Such perturbations may occur due to asymmetric capaci-
tive coupling between the F
O
signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the F
O
signal trace and the input/reference sig-
nals. When the F
O
signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formed by the F
O
connection trace, the termination and the
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the F
O
signal as well as the loop area for
the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2410 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltage and the differential reference voltage, these ca-
pacitors are switching between these four pins transfering
small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 15.
For a simple approximation, the source impedance R
S
driving an analog input pin (IN
+
, IN
, REF
+
or REF
) can be
considered to form, together with R
SW
and C
EQ
(see
Figure 15), a first order passive network with a time
constant
= (R
S
+ R
SW
) C
EQ
. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant
. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
When using the internal oscillator (F
O
= LOW or HIGH), the
LTC2410's front-end switched-capacitor network is clocked
at 76800Hz corresponding to a 13
s sampling period.
Thus, for settling errors of less than 1ppm, the driving
source impedance should be chosen such that
13
s/14
= 920ns. When an external oscillator of frequency f
EOSC
is
used, the sampling period is 2/f
EOSC
and, for a settling
error of less than 1ppm,
0.14/f
EOSC
.
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 15 shows the
mathematical expressions for the average bias currents
flowing through the IN
+
and IN
pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
LTC2410
21
APPLICATIO S I FOR ATIO
W
U
U
U
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 16. The C
PAR
capacitor
includes the LTC2410 pin capacitance (5pF typical) plus
the capacitance of the test fixture used to obtain the results
shown in Figures 17 and 18. A careful implementation can
bring the total input capacitance (C
IN
+ C
PAR
) closer to 5pF
thus achieving better performance than the one predicted
by Figures 17 and 18. For simplicity two distinct situations
can be considered.
Figure 15. LTC2410 Equivalent Analog Input Circuit
Figure 16. An RC Network at IN
+
and IN
Figure 18. FS Error vs R
SOURCE
at IN
+
or IN
(Small C
IN
)
Figure 17. +FS Error vs R
SOURCE
at IN
+
or IN
(Small C
IN
)
I IN
V
V
V
R
I IN
V
V
V
R
I REF
V
V
V
R
V
V
R
I REF
V
V
V
R
V
V
R
where
AVG
IN
INCM
REFCM
EQ
AVG
IN
INCM
REFCM
EQ
AVG
REF
INCM
REFCM
EQ
IN
REF
EQ
AVG
REF
INCM
REFCM
EQ
IN
REF
EQ
+
-
+
-
( )
=
+
-
( )
= -
+
-
( )
=
-
+
-
( )
= -
-
+
+
0 5
0 5
1 5
0 5
1 5
0 5
2
2
.
.
.
.
.
.
:
:
.
.
.
/
V
REF
REF
V
REF
REF
V
IN
IN
V
IN
IN
R
M
INTERNAL OSCILLATOR
Hz Notch F
LOW
R
M
INTERNAL OSCILLATOR
Hz Notch F
HIGH
R
f
EXTERNAL OSCILLATOR
REF
REFCM
IN
INCM
EQ
O
EQ
O
EQ
EOSC
=
-
=
+
=
-
=
-
=
=
(
)
=
=
(
)
=
(
)
+
-
+
-
+
-
+
-
2
2
3 61
60
4 32
50
0 555 10
12
V
REF
+
V
IN
+
V
CC
R
SW
(TYP)
20k
I
LEAK
I
LEAK
V
CC
I
LEAK
I
LEAK
V
CC
R
SW
(TYP)
20k
C
EQ
18pF
(TYP)
R
SW
(TYP)
20k
I
LEAK
I
IN
+
V
IN
I
IN
I
REF
+
I
REF
2410 F15
I
LEAK
V
CC
I
LEAK
I
LEAK
SWITCHING FREQUENCY
f
SW
= 76800Hz INTERNAL OSCILLATOR (F
O
= LOW OR HIGH)
f
SW
= 0.5 f
EOSC
EXTERNAL OSCILLATOR
V
REF
R
SW
(TYP)
20k
C
IN
2410 F16
V
INCM
+ 0.5V
IN
R
SOURCE
IN
+
LTC2410
C
PAR
20pF
C
IN
V
INCM
0.5V
IN
R
SOURCE
IN
C
PAR
20pF
R
SOURCE
(
)
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
+FS ERROR (ppm OF V
REF
)
2410 F17
50
40
30
20
10
0
V
CC
= 5V
REF
+
= 5V
REF
= GND
IN
+
= 5V
IN
= 2.5V
F
O
= GND
T
A
= 25
C
C
IN
= 0.01
F
C
IN
= 0.001
F
C
IN
= 100pF
C
IN
= 0pF
R
SOURCE
(
)
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
+FS ERROR (ppm OF V
REF
)
2410 F18
0
10
20
30
40
50
V
CC
= 5V
REF
+
= 5V
REF
= GND
IN
+
= GND
IN
= 2.5V
F
O
= GND
T
A
= 25
C
C
IN
= 0.01
F
C
IN
= 0.001
F
C
IN
= 100pF
C
IN
= 0pF
LTC2410
22
APPLICATIO S I FOR ATIO
W
U
U
U
For relatively small values of input capacitance (C
IN
<
0.01
F), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for C
IN
will deteriorate the converter offset and gain
performance without significant benefits of signal filtering
and the user is advised to avoid them. Nevertheless, when
small values of C
IN
are unavoidably present as parasitics
of input multiplexers, wires, connectors or sensors, the
LTC2410 can maintain its exceptional accuracy while
operating with relative large values of source resistance as
shown in Figures 17 and 18. These measured results may
be slightly different from the first order approximation
suggested earlier because they include the effect of the
actual second order input network together with the non-
linear settling process of the input amplifiers. For small C
IN
values, the settling on IN
+
and IN
occurs almost indepen-
dently and there is little benefit in trying to match the
source impedance for the two pins.
Larger values of input capacitors (C
IN
> 0.01
F) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When F
O
= LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 1.8M
which will
generate a gain error of approximately 0.28ppm for each
ohm of source resistance driving IN
+
or IN
. When F
O
=
HIGH (internal oscillator and 50Hz notch), the typical
differential input resistance is 2.16M
which will generate
a gain error of approximately 0.23ppm for each ohm of
source resistance driving IN
+
or IN
. When F
O
is driven by
an external oscillator with a frequency f
EOSC
(external
conversion clock operation), the typical differential input
resistance is 0.28 10
12
/f
EOSC
and each ohm of
source resistance driving IN
+
or IN
will result in
1.78 10
6
f
EOSC
ppm gain error. The effect of the source
resistance on the two input pins is additive with respect to
this gain error. The typical +FS and FS errors as a function
of the sum of the source resistance seen by IN
+
and IN
for
large values of C
IN
are shown in Figures 19 and 20.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN
+
and IN
and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the
converter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large C
IN
capacitor
values, it is advisable to carefully match the source imped-
ance seen by the IN
+
and IN
pins. When F
O
= LOW
(internal oscillator and 60Hz notch), every 1
mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.28ppm. When F
O
= HIGH (internal oscillator and 50Hz
notch), every 1
mismatch in source impedance trans-
forms a full-scale common mode input signal into a
differential mode input signal of 0.23ppm. When F
O
is
driven by an external oscillator with a frequency f
EOSC
,
every 1
mismatch in source impedance transforms a
full-scale common mode input signal into a differential
mode input signal of 1.78 10
6
f
EOSC
ppm. Figure 21
shows the typical offset error due to input common mode
voltage for various values of source resistance imbalance
between the IN
+
and IN
pins when large C
IN
values are
used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/
C) are
used for the external source impedance seen by IN
+
and
IN
, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications a one-time cali-
bration operation may be sufficient.
LTC2410
23
APPLICATIO S I FOR ATIO
W
U
U
U
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (
10nA max), results
in a small offset shift. A 100
source resistance will create
a 0.1
V typical and 1
V maximum offset voltage.
Reference Current
In a similar fashion, the LTC2410 samples the differential
reference pins REF
+
and REF
transfering small amount of
charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset but it may degrade the gain
and INL performance. The effect of this current can be
analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (C
REF
< 0.01
F), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C
REF
will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (C
REF
> 0.01
F) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance. When F
O
= LOW
(internal oscillator and 60Hz notch), the typical differential
reference resistance is 1.3M
which will generate a gain
error of approximately 0.38ppm for each ohm of source
resistance driving REF
+
or REF
. When F
O
= HIGH (internal
oscillator and 50Hz notch), the typical differential refer-
ence resistance is 1.56M
which will generate a gain error
of approximately 0.32ppm for each ohm of source resis-
tance driving REF
+
or REF
. When F
O
is driven by an
external oscillator with a frequency f
EOSC
(external conver-
sion clock operation), the typical differential reference
resistance is 0.20 10
12
/f
EOSC
and each ohm of source
resistance drving REF
+
or REF
will result in
2.47 10
6
f
EOSC
ppm gain error. The effect of the source
resistance on the two reference pins is additive with
respect to this gain error. The typical +FS and FS errors
for various combinations of source resistance seen by the
Figure 19. +FS Error vs R
SOURCE
at IN
+
or IN
(Large C
IN
)
Figure 20. FS Error vs R
SOURCE
at IN
+
or IN
(Large C
IN
)
Figure 21. Offset Error vs Common Mode Voltage
(V
INCM
= IN
+
= IN
) and Input Source Resistance Imbalance
(
R
IN
= R
SOURCEIN
+ R
SOURCEIN
) for Large C
IN
Values (C
IN
1
F)
R
SOURCE
(
)
0 100 200 300 400 500 600 700 800 900 1000
+FS ERROR (ppm OF V
REF
)
2410 F19
300
240
180
120
60
0
V
CC
= 5V
REF
+
= 5V
REF
= GND
IN
+
= 3.75V
IN
= 1.25V
F
O
= GND
T
A
= 25
C
C
IN
= 0.01
F
C
IN
= 0.1
F
C
IN
= 1
F, 10
F
R
SOURCE
(
)
0 100 200 300 400 500 600 700 800 900 1000
FS ERROR (ppm OF V
REF
)
2410 F20
0
60
120
180
240
300
V
CC
= 5V
REF
+
= 5V
REF
= GND
IN
+
= 1.25V
IN
= 3.75V
F
O
= GND
T
A
= 25
C
C
IN
= 0.01
F
C
IN
= 0.1
F
C
IN
= 1
F, 10
F
V
INCM
(V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
FS ERROR (ppm OF V
REF
)
2410 F21
120
100
80
60
40
20
0
20
40
60
80
100
120
F
O
= GND
T
A
= 25
C
R
SOURCEIN
= 500
C
IN
= 10
F
V
CC
= 5V
REF
+
= 5V
REF
= GND
IN
+
= IN
= V
INCM
A:
R
IN
= +400
B:
R
IN
= +200
C:
R
IN
= +100
D:
R
IN
= 0
E:
R
IN
= 100
F:
R
IN
= 200
G:
R
IN
= 400
A
B
C
D
E
F
G
LTC2410
24
APPLICATIO S I FOR ATIO
W
U
U
U
REF
+
and REF
pins and external capacitance C
REF
con-
nected to these pins are shown in Figures 22, 23, 24
and 25.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When F
O
= LOW (internal oscillator and 60Hz notch), every
100
of source resistance driving REF
+
or REF
translates
into about 1.34ppm additional INL error. When F
O
= HIGH
(internal oscillator and 50Hz notch), every 100
of source
resistance driving REF
+
or REF
translates into about
1.1ppm additional INL error. When F
O
is driven by an
external oscillator with a frequency f
EOSC
, every 100
of
source resistance driving REF
+
or REF
translates into
about 8.73 10
6
f
EOSC
ppm additional INL error.
Figure 26 shows the typical INL error due to the source
resistance driving the REF
+
or REF
pins when large C
REF
values are used. The effect of the source resistance on the
two reference pins is additive with respect to this INL error.
In general, matching of source impedance for the REF
+
and REF
pins does not help the gain or the INL error. The
user is thus advised to minimize the combined source
impedance driving the REF
+
and REF
pins rather than to
try to match it.
Figure 22. +FS Error vs R
SOURCE
at REF
+
or REF
(Small C
IN
)
Figure 23. FS Error vs R
SOURCE
at REF
+
or REF
(Small C
IN
)
Figure 24. +FS Error vs R
SOURCE
at REF
+
and REF
(Large C
REF
)
Figure 25. FS Error vs R
SOURCE
at REF
+
and REF
(Large C
REF
)
R
SOURCE
(
)
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
+FS ERROR (ppm OF V
REF
)
2410 F22
0
10
20
30
40
50
V
CC
= 5V
REF
+
= 5V
REF
= GND
IN
+
= 5V
IN
= 2.5V
F
O
= GND
T
A
= 25
C
C
REF
= 0.01
F
C
REF
= 0.001
F
C
REF
= 100pF
C
REF
= 0pF
R
SOURCE
(
)
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
FS ERROR (ppm OF V
REF
)
2410 F23
50
40
30
20
10
0
V
CC
= 5V
REF
+
= 5V
REF
= GND
IN
+
= GND
IN
= 2.5V
F
O
= GND
T
A
= 25
C
C
REF
= 0.01
F
C
REF
= 0.001
F
C
REF
= 100pF
C
REF
= 0pF
R
SOURCE
(
)
0 100 200 300 400 500 600 700 800 900 1000
+
FS ERROR (ppm OF V
REF
)
2410 F24
0
90
180
270
360
450
V
CC
= 5V
REF
+
= 5V
REF
= GND
IN
+
= 3.75V
IN
= 1.25V
F
O
= GND
T
A
= 25
C
C
REF
= 0.01
F
C
REF
= 0.1
F
C
REF
= 1
F, 10
F
R
SOURCE
(
)
0 100 200 300 400 500 600 700 800 900 1000
+FS ERROR (ppm OF V
REF
)
2410 F25
450
360
270
180
90
0
V
CC
= 5V
REF
+
= 5V
REF
= GND
IN
+
= 1.25V
IN
= 3.75V
F
O
= GND
T
A
= 25
C
C
REF
= 0.01
F
C
REF
= 0.1
F
C
REF
= 1
F, 10
F
LTC2410
25
APPLICATIO S I FOR ATIO
W
U
U
U
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
(50ppm/
C) are used for the external source impedance
seen by REF
+
and REF
, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(
10nA max), results in a small gain error. A 100
source
resistance will create a 0.05
V typical and 0.5
V maxi-
mum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2410 can pro-
duce up to 7.5 readings per second with a notch frequency
of 60Hz (F
O
= LOW) and 6.25 readings per second with a
notch frequency of 50Hz (F
O
= HIGH). The actual output
data rate will depend upon the length of the sleep and data
output phases which are controlled by the user and which
can be made insignificantly short. When operated with an
external conversion clock (F
O
connected to an external
oscillator), the LTC2410 output data rate can be increased
as desired. The duration of the conversion phase is 20510/
f
EOSC
. If f
EOSC
= 153600Hz, the converter behaves as if the
internal oscillator is used and the notch is set at 60Hz.
There is no significant difference in the LTC2410 perfor-
mance between these two operation modes.
An increase in f
EOSC
over the nominal 153600Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
First, a change in f
EOSC
will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent perfor-
mance degradation can be substantially reduced by rely-
ing upon the LTC2410's exceptional common mode rejec-
tion and by carefully eliminating common mode to differ-
ential mode conversion sources in the input circuit. The
user should avoid single-ended input filters and should
maintain a very high degree of matching and symmetry in
the circuits driving the IN
+
and IN
pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (C
IN
, C
REF
) are used, the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter perfor-
mance for any value of f
EOSC
. If small external input and/
or reference capacitors (C
IN
, C
REF
) are used, the effect of
the external source resistance upon the LTC2410 typical
performance can be inferred from Figures 17, 18, 22 and
23 in which the horizontal axis is scaled by 153600/f
EOSC
.
Third, an increase in the frequency of the external oscilla-
tor above 460800Hz (a more than 3
increase in the output
data rate) will start to decrease the effectiveness of the
internal autocalibration circuits. This will result in a pro-
gressive degradation in the converter accuracy and linear-
Figure 26. INL vs Differential Input Voltage (V
IN
= IN
+
IN
)
and Reference Source Resistance (R
SOURCE
at REF
+
and REF
for
Large C
REF
Values (C
REF
1
F)
V
INDIF
/V
REFDIF
0.5 0.40.30.20.1 0
0.1 0.2 0.3 0.4 0.5
INL (ppm OF V
REF
)
15
12
9
6
3
0
3
6
9
12
15
V
CC
= 5V
REF+ = 5V
REF = GND
V
INCM
= 0.5 (IN
+
+ IN
) = 2.5V
F
O
= GND
C
REF
= 10
F
T
A
= 25
C
R
SOURCE
= 1000
R
SOURCE
= 500
R
SOURCE
= 100
2410 F26
LTC2410
26
APPLICATIO S I FOR ATIO
W
U
U
U
ity. Typical measured performance curves for output data
rates up to 100 readings per second are shown in Fig-
ures 27, 28, 29, 30, 31, 32, 33 and 34. In order to obtain
the highest possible level of accuracy from this converter
at output data rates above 20 readings per second, the
user is advised to maximize the power supply voltage used
and to limit the maximum ambient operating temperature.
In certain circumstances, a reduction of the differential
reference voltage may be beneficial.
Input Bandwidth
The combined effect of the internal Sinc
4
digital filter and
of the analog and digital autocalibration circuits deter-
mines the LTC2410 input bandwidth. When the internal
oscillator is used with the notch set at 60Hz (F
O
= LOW),
the 3dB input bandwidth is 3.63Hz. When the internal
oscillator is used with the notch set at 50Hz (F
O
= HIGH),
the 3dB input bandwidth is 3.02Hz. If an external conver-
sion clock generator of frequency f
EOSC
is connected to the
F
O
pin, the 3dB input bandwidth is 0.236 10
6
f
EOSC
.
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled very
accurately by a first order filter with the pole located at the
3dB frequency. When the internal oscillator is used, the
shape of the LTC2410 input bandwidth is shown in Fig-
ure 35 for F
O
= LOW and F
O
= HIGH. When an external
oscillator of frequency f
EOSC
is used, the shape of the
LTC2410 input bandwidth can be derived from Figure 35,
F
O
= LOW curve in which the horizontal axis is scaled by
f
EOSC
/153600.
The conversion noise (800nV
RMS
typical for V
REF
= 5V)
can be modeled by a white noise source connected to a
noise free converter. The noise spectral density is
62.75nV
Hz for an infinite bandwidth source and
76.8nV
Hz for a single 0.5MHz pole source. From these
numbers, it is clear that particular attention must be given
to the design of external amplification circuits. Such
circuits face the simultaneous requirements of very low
bandwidth (just a few Hz) in order to reduce the output
referred noise and relatively high bandwidth (at least
500kHz) necessary to drive the input switched-capacitor
network. A possible solution is a high gain, low bandwidth
amplifier stage followed by a high bandwidth unity-gain
buffer.
Figure 27. Offset Error vs Output Data Rate and Temperature
Figure 28. +FS Error vs Output Data Rate and Temperature
Figure 29. FS Error vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
OFFSET ERROR (ppm OF V
REF
)
2410 F27
500
450
400
350
300
250
200
150
100
50
0
T
A
= 85
C
V
CC
= 5V
REF
+
= 5V
REF
= GND
V
INCM
= 2.5V
V
IN
= 0V
F
O
= EXTERNAL OSCILLATOR
T
A
= 25
C
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
+FS ERROR (ppm OF V
REF
)
2410 F28
7000
6000
5000
4000
3000
2000
1000
0
T
A
= 85
C
V
CC
= 5V
REF
+
= 5V
REF
= GND
IN
+
= 3.75V
IN
= 1.25V
F
O
= EXTERNAL OSCILLATOR
T
A
= 25
C
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
FS ERROR (ppm OF V
REF
)
2410 F29
0
1000
2000
3000
4000
5000
6000
7000
T
A
= 85
C
V
CC
= 5V
REF
+
= 5V
REF
= GND
IN
+
= 1.25V
IN
= 3.75V
F
O
= EXTERNAL OSCILLATOR
T
A
= 25
C
LTC2410
27
APPLICATIO S I FOR ATIO
W
U
U
U
Figure 30. Resolution (Noise
RMS
1LSB)
vs Output Data Rate and Temperature
Figure 31. Resolution (INL
RMS
1LSB)
vs Output Data Rate and Temperature
Figure 32. Offset Error vs Output
Data Rate and Reference Voltage
Figure 33. Resolution (Noise
RMS
1LSB) vs
Output Data Rate and Reference Voltage
Figure 34. Resolution (INL
MAX
1LSB) vs Output Data Rate and Reference Voltage
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
RESOLUTION (BITS)
2410 F30
24
23
22
21
20
19
18
17
16
15
14
13
12
T
A
= 85
C
V
CC
= 5V
REF
+
= 5V
REF
= GND
V
INCM
= 2.5V
V
IN
= 0V
F
O
= EXTERNAL OSCILLATOR
RESOLUTION = LOG
2
(V
REF
/NOISE
RMS
)
T
A
= 25
C
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
RESOLUTION (BITS)
2410 F31
22
20
18
16
14
12
10
8
T
A
= 85
C
V
CC
= 5V
REF
+
= 5V
REF
= GND
V
INCM
= 2.5V
2.5V < V
IN
< 2.5V
F
O
= EXTERNAL OSCILLATOR
RESOLUTION = LOG
2
(V
REF
/INL
MAX
)
T
A
= 25
C
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
OFFSET ERROR (ppm OF V
REF
)
2410 F32
250
225
200
175
150
125
100
75
50
25
0
V
REF
= 5V
V
CC
= 5V
REF
+
= GND
V
INCM
= 2.5V
V
IN
= 0V
F
O
= EXTERNAL OSCILLATOR
T
A
= 25
C
V
REF
= 2.5V
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
RESOLUTION (BITS)
2410 F33
24
23
22
21
20
19
18
17
16
15
14
13
12
V
REF
= 5V
V
CC
= 5V
REF
= GND
V
INCM
= 2.5V
V
IN
= 0V
F
O
= EXTERNAL OSCILLATOR
T
A
= 25
C
RESOLUTION = LOG
2
(V
REF
/NOISE
RMS
)
V
REF
= 2.5V
OUTPUT DATA RATE (READINGS/SEC)
0
10 20 30 40 50 60 70 80 90 100
RESOLUTION (BITS)
2410 F34
22
20
18
16
14
12
10
8
T
A
= 25
C
V
CC
= 5V
REF
= GND
V
INCM
= 0.5 REF
+
0.5V V
REF
< V
IN
< 0.5 V
REF
F
O
= EXTERNAL OSCILLATOR
V
REF
= 2.5V
V
REF
= 5V
RESOLUTION =
LOG
2
(V
REF
/INL
MAX
)
LTC2410
28
APPLICATIO S I FOR ATIO
W
U
U
U
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2410 significantly
simplifies antialiasing filter requirements.
The Sinc
4
digital filter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (f
S
). The
LTC2410's autocalibration circuits further simplify the
antialiasing requirements by additional normal mode sig-
nal filtering both in the analog and digital domain. Inde-
pendent of the operating mode, f
S
= 256 f
N
= 2048
f
OUTMAX
where f
N
in the notch frequency and f
OUTMAX
is
the maximum output data rate. In the internal oscillator
mode with a 50Hz notch setting, f
S
= 12800Hz and with a
60Hz notch setting f
S
= 15360Hz. In the external oscillator
mode, f
S
= f
EOSC
/10.
The combined normal mode rejection performance is
shown in Figure 36 for the internal oscillator with 50Hz
notch setting (F
O
= HIGH) and in Figure 37 for the internal
oscillator with 60Hz notch setting (F
O
= LOW) and for the
external oscillator mode. The regions of low rejection
occurring at integer multiples of f
S
have a very narrow
bandwidth. Magnified details of the normal mode rejection
curves are shown in Figure 38 (rejection near DC) and
Figure 39 (rejection at f
S
= 256f
N
) where f
N
represents the
notch frequency. These curves have been derived for the
external oscillator mode but they can be used in all
operating modes by appropriately selecting the f
N
value.
The user can expect to achieve in practice this level of
performance using the internal oscillator as it is demon-
strated by Figures 40 and 41. Typical measured values of
the normal mode rejection of the LTC2410 operating with
an internal oscillator and a 60Hz notch setting are shown
in Figure 40 superimposed over the theoretical calculated
curve. Similarly, typical measured values of the normal
mode rejection of the LTC2410 operating with an internal
oscillator and a 50Hz notch setting are shown in Figure 41
superimposed over the theoretical calculated curve.
As a result of these remarkable normal mode specifica-
tions, minimal (if any) antialias filtering is required in front
of the LTC2410. If passive RC components are placed in
Figure 35. Input Signal Bandwidth Using the Internal Oscillator
Figure 36. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch
Figure 37. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Notch or External Oscillator
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
INPUT SIGNAL ATTENUATION (dB)
2410 F35
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
F
O
= HIGH
F
O
= LOW
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
f
S
2f
S
3f
S
4f
S
5f
S
6f
S
7f
S
8f
S
9f
S
10f
S
11f
S
12f
S
INPUT NORMAL MODE REJECTION (dB)
2410 F36
0
10
20
30
40
50
60
70
80
90
100
110
120
F
O
= HIGH
F
O
= LOW OR
F
O
= EXTERNAL OSCILLATOR,
f
EOSC
= 10 f
S
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
f
S
INPUT NORMAL MODE REJECTION (dB)
2410 F37
0
10
20
30
40
50
60
70
80
90
100
110
120
2f
S
3f
S
4f
S
5f
S
6f
S
7f
S
8f
S
9f
S
10f
S
LTC2410
29
APPLICATIO S I FOR ATIO
W
U
U
U
Figure 38. Input Normal Mode Rejection
Figure 39. Input Normal Mode Rejection
Figure 40. Input Normal Mode Rejection vs Input Frequency
Figure 41. Input Normal Mode Rejection vs Input Frequency
INPUT SIGNAL FREQUENCY (Hz)
INPUT NORMAL MODE REJECTION (dB)
2410 F38
0
10
20
30
40
50
60
70
80
90
100
110
120
f
N
0
2f
N
3f
N
4f
N
5f
N
6f
N
7f
N
8f
N
INPUT SIGNAL FREQUENCY (Hz)
250f
N
252f
N
254f
N
256f
N
258f
N
260f
N
262f
N
INPUT NORMAL MODE REJECTION (dB)
2410 F39
0
10
20
30
40
50
60
70
80
90
100
110
120
INPUT FREQUENCY (Hz)
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210 225 240
NORMAL MODE REJECTION (dB)
2410 F40
0
20
40
60
80
100
120
V
CC
= 5V
REF
+
= 5V
REF
= GND
V
INCM
= 2.5V
V
IN(P-P)
= 5V
F
O
= GND
T
A
= 25
C
MEASURED DATA
CALCULATED DATA
INPUT FREQUENCY (Hz)
0
12.5
25
37.5
50
62.5
75
87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
NORMAL MODE REJECTION (dB)
2410 F41
0
20
40
60
80
100
120
V
CC
= 5V
REF
+
= 5V
REF
= GND
V
INCM
= 2.5V
V
IN(P-P)
= 5V
F
O
= 5V
T
A
= 25
C
MEASURED DATA
CALCULATED DATA
LTC2410
30
APPLICATIO S I FOR ATIO
W
U
U
U
front of the LTC2410, the input dynamic current should be
considered (see Input Current section). In cases where
large effective RC time constants are used, an external
buffer amplifier may be required to minimize the effects of
dynamic input current.
Traditional high order delta-sigma modulators, while pro-
viding very good linearity and resolution, suffer from po-
tential instabilities at large input signal levels. The propri-
etary architecture used for the LTC2410 third order modu-
lator resolves this problem and guarantees a predictable
stable behavior at input signal levels of up to 150% of full
scale. In many industrial applications, it is not uncommon
to have to measure microvolt level signals superimposed
over volt level perturbations and LTC2410 is eminently
suited for such tasks. When the perturbation is differential,
the specification of interest is the normal mode rejection
for large input signal levels. With a reference voltage
V
REF
= 5V, the LTC2410 has a full-scale differential input
range of 5V peak-to-peak. Figures 42 and 43 show mea-
surement results for the LTC2410 normal mode rejection
ratio with a 7.5V peak-to-peak (150% of full scale) input
signal superimposed over the more traditional normal mode
rejection ratio results obtained with a 5V peak-to-peak (full
scale) input signal. In Figure 42, the LTC2410 uses the
internal oscillator with the notch set at 60Hz (F
O
= LOW)
and in Figure 43 it uses the internal oscillator with the
notch set at 50Hz (F
O
= HIGH). It is clear that the LTC2410
rejection performance is maintained with no compromises
in this extreme situation. When operating with large input
signal levels, the user must observe that such signals do
not violate the device absolute maximum ratings.
Figure 42. Measured Input Normal Mode Rejection vs Input Frequency
Figure 43. Measured Input Normal Mode Rejection vs Input Frequency
INPUT FREQUENCY (Hz)
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210 225 240
NORMAL MODE REJECTION (dB)
2410 F3a
0
20
40
60
80
100
120
V
CC
= 5V
REF
+
= 5V
REF
= GND
V
INCM
= 2.5V
F
O
= GND
T
A
= 25
C
V
IN(P-P)
= 5V
V
IN(P-P)
= 7.5V
(150% OF FULL SCALE)
INPUT FREQUENCY (Hz)
0
NORMAL MODE REJECTION (dB)
2410 F4a
0
20
40
60
80
100
120
V
CC
= 5V
REF
+
= 5V
REF
= GND
V
INCM
= 2.5V
F
O
= 5V
T
A
= 25
C
V
IN(P-P)
= 5V
V
IN(P-P)
= 7.5V
(150% OF FULL SCALE)
12.5
25
37.5
50
62.5
75
87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
LTC2410
31
APPLICATIO S I FOR ATIO
W
U
U
U
SYNCHRONIZATION OF MULTIPLE LTC2410s
Since the LTC2410's absolute accuracy (total unadjusted
error) is 5ppm, applications utilizing multiple synchro-
nized ADCs are possible.
Simultaneous Sampling with Two LTC2410s
One such application is synchronizing multiple LTC2410s,
see Figure 44. The start of conversion is synchronized to
the rising edge of CS. In order to synchronize multiple
LTC2410s, CS is a common input to all the ADCs.
To prevent the converters from autostarting a new con-
version at the end of data output read, 31 or fewer SCK
clock signals are applied to the LTC2410 instead of 32 (the
32nd falling edge would start a conversion). The exact
timing and frequency for the SCK signal is not critical
since it is only shifting out the data. In this case, two
LTC2410's simultaneously start and end their conversion
cycles under the external control of CS.
Increasing the Output Rate Using Mulitple LTC2410s
A second application uses multiple LTC2410s to increase
the effective output rate by 4
, see Figure 45. In this case,
four LTC2410s are interleaved under the control of sepa-
rate CS signals. This increases the effective output rate
from 7.5Hz to 30Hz (up to a maximum of 60Hz). Addition-
ally, the one-shot output spectrum is unfolded allowing
further digital signal processing of the conversion results.
SCK and SDO may be common to all four LTC2410s. The
four CS rising edges equally divide one LTC2410 conver-
sion cycle (7.5Hz for 60Hz notch frequency). In order to
synchronize the start of conversion to CS, 31 or less SCK
clock pulses must be applied to each ADC.
Both the synchronous and 4
output rate applications use
the external serial clock and single cycle operation with
reduced data output length (see Serial Interface Timing
Modes section and Figure 6). An external oscillator clock
is applied commonly to the F
O
pin of each LTC2410 in
order to synchronize the sampling times. Both circuits
may be extended to include more LTC2410s.
Figure 44. Synchronous Conversion--Extendable
31 OR LESS CLOCK CYCLES
CS
SCK1
SCK2
2410 F44
SDO1
SDO2
31 OR LESS CLOCK CYCLES
LTC2410
#1
V
CC
REF
+
REF
IN
+
IN
GND
F
O
SCK
SDO
CS
SCK2
SCK1
CS
SDO1
SDO2
LTC2410
#2
V
CC
REF
+
REF
IN
+
IN
GND
F
O
SCK
SDO
CS
CONTROLLER
EXTERNAL OSCILLATOR
(153,600HZ)
V
REF
+
V
REF
LTC2410
32
APPLICATIO S I FOR ATIO
W
U
U
U
BRIDGE APPLICATIONS
Typical strain gauge based bridges deliver only 2mV/Volt
of excitation. As the maximum reference voltage of the
LTC2410 is 5V, remote sensing of applied excitation
without additional circuitry requires that excitation be
limited to 5V. This gives only 10mV full scale, which can
be resolved to 1 part in 10000 without averaging. For many
solid state sensors, this is still better than the sensor. For
example, averaging 64 samples however reduces the
noise level by a factor of eight, bringing the resolving
power to 1 part in 80000, comparable to better weighing
systems. Hysteresis and creep effects in the load cells are
typically much greater than this. Most applications that
require strain measurements to this level of accuracy are
measuring slowly changing phenomena, hence the time
required to average a large number of readings is usually
not an issue. For those systems that require accurate
measurement of a small incremental change on a signifi-
cant tare weight, the lack of history effects in the LTC2400
family is of great benefit.
For those applications that cannot be fulfilled by the
LTC2410 alone, compensating for error in external ampli-
fication can be done effectively due to the "no latency"
feature of the LTC2410. No latency operation allows
samples of the amplifier offset and gain to be interleaved
with weighing measurements. The use of correlated double
sampling allows suppression of 1/f noise, offset and
thermocouple effects within the bridge. Correlated double
sampling involves alternating the polarity of excitation and
dealing with the reversal of input polarity mathematically.
Alternatively, bridge excitation can be increased to as
much as
10V, if one of several precision attenuation
Figure 45. Actual Frequency Rate LTC2410 System
CS1
CS2
CS3
2410 F45
CS4
SCK
31 OR LESS
CLOCK PULSES
SDO
LTC2410
#1
SCK
SDO
CS1
CS2
CS3
CS4
LTC2410
#2
LTC2410
#3
LTC2410
#4
CONTROLLER
EXTERNAL OSCILLATOR
(153,600HZ)
V
REF
+
V
REF
V
CC
REF
+
REF
IN
+
IN
GND
F
O
SCK
SDO
CS
V
CC
REF
+
REF
IN
+
IN
GND
F
O
SCK
SDO
CS
V
CC
REF
+
REF
IN
+
IN
GND
F
O
SCK
SDO
CS
V
CC
REF
+
REF
IN
+
IN
GND
F
O
SCK
SDO
CS
LTC2410
33
APPLICATIO S I FOR ATIO
W
U
U
U
techniques is used to produce a precision divide operation
on the reference signal. Another option is the use of a
reference within the 5V input range of the LTC2410 and
developing excitation via fixed gain, or LTC1043 based
voltage multiplication, along with remote feedback in the
excitation amplifiers, as shown in Figures 34 and 35.
Figure 46 shows an example of a simple bridge connec-
tion. Note that it is suitable for any bridge application
where measurement speed is not of the utmost impor-
tance. For many applications where large vessels are
weighed, the average weight over an extended period of
time is of concern and short term weight is not readily
determined due to movement of contents, or mechanical
resonance. Often, large weighing applications involve load
cells located at each load bearing point, the output of
which can be summed passively prior to the signal pro-
cessing circuitry, actively with amplification prior to the
ADC, or can be digitized via multiple ADC channels and
summed mathematically. The mathematical summation
of the output of multiple LTC2410's provides the benefit of
a root square reduction in noise. The low power consump-
tion of the LTC2410 makes it attractive for multidrop
communication schemes where the ADC is located within
the load-cell housing.
A direct connection to a load cell is perhaps best incorpo-
rated into the load-cell body, as minimizing the distance to
the sensor largely eliminates the need for protection
devices, RFI suppression and wiring. The LTC2410 exhib-
its extremely low temperature dependent drift. As a result,
exposure to external ambient temperature ranges does
not compromise performance. The incorporation of any
amplification considerably complicates thermal stability,
as input offset voltages and currents, temperature coeffi-
cient of gain settling resistors all become factors.
The circuit in Figure 47 shows an example of a simple
amplification scheme. This example produces a differen-
tial output with a common mode voltage of 2.5V, as
determined by the bridge. The use of a true three amplifier
instrumentation amplifier is not necessary, as the LTC2410
has common mode rejection far beyond that of most
amplifiers. The LTC1051 is a dual autozero amplifier that
can be used to produce a gain of 15 before its input
referred noise dominates the LTC2410 noise. This ex-
ample shows a gain of 34, that is determined by a feedback
network built using a resistor array containing 8 individual
resistors. The resistors are organized to optimize tem-
perature tracking in the presence of thermal gradients. The
second LTC1051 buffers the low noise input stage from
the transient load steps produced during conversion.
The gain stability and accuracy of this approach is very
good, due to a statistical improvement in resistor match-
ing due to individual error contribution being reduced. A
gain of 34 may seem low, when compared to common
practice in earlier generations of load-cell interfaces, how-
ever the accuracy of the LTC2410 changes the rationale.
Achieving high gain accuracy and linearity at higher gains
may prove difficult, while providing little benefit in terms
of noise reduction.
At a gain of 100, the gain error that could result from
typical open-loop gain of 160dB is 1ppm, however,
worst-case is at the minimum gain of 116dB, giving a gain
error of 158ppm. Worst-case gain error at a gain of 34,
is 54ppm. The use of the LTC1051A reduces the worst-
case gain error to 33ppm. The advantage of gain higher
than 34, then becomes dubious, as the input referred
noise sees little improvement
1
and gain accuracy is poten-
tially compromised.
Note that this 4-amplifier topology has advantages over
the typical integrated 3-amplifier instrumentation ampli-
fier in that it does not have the high noise level common in
Figure 46. Simple Bridge Connection
REF
+
REF
SDO
SCK
IN
+
IN
CS
GND
V
REF
F
O
3
R1
12
4
350
BRIDGE
13
5
6
2410 F46
11
1, 7, 8, 9,
10, 15, 16
2
14
LTC2410
+
R2
R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS
LT1019
LTC2410
34
APPLICATIO S I FOR ATIO
W
U
U
U
the output stage that usually dominates when an instru-
mentation amplifier is used at low gain. If this amplifier is
used at a gain of 10, the gain error is only 10ppm and input
referred noise is reduced to 0.1
V
RMS
. The buffer stages
can also be configured to provide gain of up to 50 with high
gain stability and linearity.
Figure 48 shows an example of a single amplifier used to
produce single-ended gain. This topology is best used in
applications where the gain setting resistor can be made
to match the temperature coefficient of the strain gauges.
If the bridge is composed of precision resistors, with only
one or two variable elements, the reference arm of the
bridge can be made to act in conjunction with the feedback
resistor to determine the gain. If the feedback resistor is
incorporated into the design of the load cell, using resis-
tors which match the temperature coefficient of the load-
cell elements, good results can be achieved without the
need for resistors with a high degree of absolute accuracy.
The common mode voltage in this case, is again a function
of the bridge output. Differential gain as used with a 350
bridge is A
V
= 1+ R2/(R1+175
). Common mode gain is
half the differential gain. The maximum differential signal
that can be used is 1/4 V
REF
, as opposed to 1/2 V
REF
in the
2-amplifier topology above.
Remote Half Bridge Interface
As opposed to full bridge applications, typical half bridge
applications must contend with nonlinearity in the bridge
output, as signal swing is often much greater. Applications
include RTD's, thermistors and other resistive elements
that undergo significant changes over their span. For
single variable element bridges, the nonlinearity of the half
bridge output can be eliminated completely; if the refer-
ence arm of the bridge is used as the reference to the ADC,
as shown in Figure 49. The LTC2410 can accept inputs up
to 1/2 V
REF
. Hence, the reference resistor R1 must be at
least 2x the highest value of the variable resistor.
In the case of 100
platinum RTD's, this would suggest a
value of 800
for R1. Such a low value for R1 is not
advisable due to self-heating effects. A value of 25.5k is
shown for R1, reducing self-heating effects to acceptable
levels for most sensors.
The basic circuit shown in Figure 49 shows connections
for a full 4-wire connection to the sensor, which may be
located remotely. The differential input connections will
reject induced or coupled 60Hz interference, however, the
1
Input referred noise for A
V
= 34 for approximately 0.05
V
RMS
, whereas at a gain of 50, it would be
0.048
V
RMS
.
Figure 47. Using Autozero Amplifiers to Reduce Input Referred Noise
0.1
F
8
0.1
F
0.1
F
REF
+
REF
SDO
SCK
IN
+
IN
CS
GND
V
CC
F
O
3
12
5V
REF
4
350
BRIDGE
13
5
6
2410 F47
11
1, 7, 8, 9,
10, 15, 16
2
14
LTC2410
RN1 = 5k
8 RESISTOR ARRAY
U1A, U1B, U2A, U2B = 1/2 LTC1051
+
3
2
8
4
U1A
4
5V
+
6
5
RN1
1
16
15
2
6
11
7
1
14
3
7
10
4
13
8
9
5
12
U1B
+
3
2
U2A
5V
1
+
6
5
U2B
7
LTC2410
35
APPLICATIO S I FOR ATIO
W
U
U
U
reference inputs do not have the same rejection. If 60Hz or
other noise is present on the reference input, a low pass
filter is recommended as shown in Figure 50. Note that you
cannot place a large capacitor directly at the junction of R1
and R2, as it will store charge from the sampling process.
A better approach is to produce a low pass filter decoupled
from the input lines with a high value resistor (R3).
The use of a third resistor in the half bridge, between the
variable and fixed elements gives essentially the same
result as the two resistor version, but has a few benefits.
If, for example, a 25k reference resistor is used to set the
excitation current with a 100
RTD, the negative refer-
ence input is sampling the same external node as the
positive input, but may result in errors if used with a long
cable. For short cable applications, the errors may be
acceptalby low. If instead the single 25k resistor is re-
placed with a 10k 5% and a 10k 0.1% negative reference
resistor, the noise level introduced at the reference, at
least at higher frequencies, will be reduced. A filter can be
introduced into the network, in the form of one or more
capacitors, or ferrite beads, as long as the sampling pulses
are not translated into an error. The reference voltage is
also reduced, but this is not undesirable, as it will decrease
the value of the LSB, although, not the input referred noise
level.
The circuit shown in Figure 50 shows a more rigorous
example of Figure 49, with increased noise suppression
and more protection for remote applications.
Figure 51 shows an example of gain in the excitation circuit
and remote feedback from the bridge. The LTC1043's
provide voltage multiplication, providing
10V from a 5V
reference with only 1ppm error. The amplifiers are used at
unity-gain and, hence, introduce a very little error due to
gain error or due to offset voltages. A 1
V/
C offset voltage
drift translates into 0.05ppm/
C gain error. Simpler alter-
natives, with the amplifiers providing gain using resistor
arrays for feedback, can produce results that are similar to
bridge sensing schemes via attenuators. Note that the
amplifiers must have high open-loop gain or gain error will
be a source of error. The fact that input offset voltage has
relatively little effect on overall error may lead one to use
low performance amplifiers for this application. Note that
the gain of a device such as an LF156, (25V/mV over
temperature) will produce a worst-case error of 180ppm
at a noise gain of 3, such as would be encountered in an
inverting gain of 2, to produce 10V from a 5V reference.
Figure 48. Bridge Amplification Using a Single Amplifier
0.1
F
5V
REF
+
REF
IN
+
IN
GND
V
CC
3
3
2
4
6
7
4
350
BRIDGE
5
6
2410 F48
1, 7, 8, 9,
10, 15, 16
2
LTC2410
+
LTC1050S8
5V
0.1
V
R2
46.4k
20k
20k
175
1
F
10
F
R1
4.98k
(
)
A
V
= 9.98 1 +
46.4k
4.99k + 175
+
+
1
F
+
LTC2410
36
APPLICATIO S I FOR ATIO
W
U
U
U
The error associated with the 10V excitation would be
80ppm. Hence, overall reference error could be as high
as 130ppm, the average of the two.
Figure 52 shows a similar scheme to provide excitation
using resistor arrays to produce precise gain. The circuit
is configured to provide 10V and 5V excitation to the
bridge, producing a common mode voltage at the input to
the LTC2410 of 2.5V, maximizing the AC input range for
applications where induced 60Hz could reach amplitudes
up to 2V
RMS
.
The last two example circuits could be used where mul-
tiple bridge circuits are involved and bridge output can be
multiplexed onto a single LTC2410, via an inexpensive
multiplexer such as the 74HC4052.
Figure 53 shows the use of an LTC2410 with a differential
multiplexer. This is an inexpensive multiplexer that will
contribute some error due to leakage if used directly with
the output from the bridge, or if resistors are inserted as
a protection mechanism from overvoltage. Although the
bridge output may be within the input range of the A/D and
multiplexer in normal operation, some thought should be
given to fault conditions that could result in full excitation
voltage at the inputs to the multiplexer or ADC. The use of
amplification prior to the multiplexer will largely eliminate
errors associated with channel leakage developing error
voltages in the source impedance.
Figure 50. Remote Half Bridge Sensing with Noise Suppression on Reference
Figure 49. Remote Half Bridge Interface
2410 F49
REF
+
REF
IN
+
IN
GND
V
CC
V
S
2.7V TO 5.5V
3
4
5
6
PLATINUM
100
RTD
R1
25.5k
0.1%
1, 7, 8, 9,
10, 15, 16
2
LTC2410
REF
+
REF
IN
GND
V
CC
5V
3
4
6
2410 F50
1, 7, 8, 9,
10, 15, 16
2
LTC2410
+
LTC1050
5V
PLATINUM
100
RTD
560
R3
10k
5%
R1
10k, 5%
R2
10k
0.1%
1
F
IN
+
5
10k
10k
LTC2410
37
APPLICATIO S I FOR ATIO
W
U
U
U
Figure 51. LTC1043 Provides Precise 3X Reference for Excitation Voltages
350
BRIDGE
0.1
F
1
F
15V
15V
15V
3
8
14
7
4
13
12
11
10V
5V
15V
U1
LTC1043
6
2
7
4
7
4
+
REF
+
REF
IN
+
IN
GND
V
CC
3
4
5
6
1, 7, 8, 9,
10, 15, 16
2410 F51
2
5V
LTC2410
47
F
0.1
F
10V
+
+
17
5
15
6
18
3
2
U2
LTC1043
1
F
FILM
8
14
7
4
13
12
11
*
*
*
5V
U2
LTC1043
17
10V
10V
LT1236-5
1k
33
Q1
2N3904
0.1
F
15V
15V
15V
3
6
2
+
1k
33
Q2
2N3904
*FLYING CAPACITORS ARE
1
F FILM (MKP OR EQUIVALENT)
SEE LTC1043 DATA SHEET FOR
DETAILS ON UNUSED HALF OF U1
LTC1150
LTC1150
20
200
20
200
0.1
F
10
F
+
LTC2410
38
APPLICATIO S I FOR ATIO
W
U
U
U
Figure 52. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier
Figure 53. Use a Differential Multiplexer to Expand Channel Capability
C1
0.1
F
15V
3
1
2
3
2
1
6
5
4
+
REF
+
REF
IN
+
IN
GND
V
CC
3
4
5
6
1, 7, 8, 9,
10, 15, 16
2410 F52
2
LTC2410
LT1236-5
RN1
10k
22
10V
350
BRIDGE
TWO ELEMENTS
VARYING
RN1
10k
Q1
2N3904
1/2
LT1112
C2
0.1
F
15V
5V
15V
15V
6
7
5
8
7
+
RN1
10k
RN1 IS CADDOCK T914 10K-010-02
Q2, Q3
2N3904
2
1/2
LT1112
RN1
10k
33
2
C3
47
F
C1
0.1
F
5V
5V
8
4
20
20
+
2410 F53
REF
+
REF
IN
+
IN
1, 7, 8
A0
A1
LTC2410
V
CC
GND
13
3
6
12
47
F
14
1
5
10
16
5V
15
11
2
TO OTHER
DEVICES
4
9
8
5V
+
74HC4052
LTC2410
39
TYPICAL APPLICATIO S
U
Sample Driver for LTC2410 SPI Interface
The LTC2410 has a very simple serial interface that makes
interfacing to microprocessors and microcontrollers very
easy.
The listing in Figure 55 is a simple assembler routine for
the 68HC11 microcontroller. It uses PORT D, configuring
it for SPI data transfer between the controller and the
LTC2410. Figure 54 shows the simple 3-wire SPI
connection.
The code begins by declaring variables and allocating four
memory locations to store the 32-bit conversion result.
This is followed by initializing PORT D's SPI configuration.
The program then enters the main sequence. It activates
the LTC2410's serial interface by setting the SS output
low, sending a logic low to CS. It next waits in a loop for
a logic low on the data line, signifying end-of-conversion.
After the loop is satisfied, four SPI transfers are com-
pleted, retrieving the conversion. The main sequence ends
by setting SS high. This places the LTC2410's serial
interface in a high impedance state and initiates another
conversion.
Figure 54. Connecting the LTC2410 to a 68HC11 MCU Using the SPI Serial Interface
The performance of the LTC2410 can be verified using the
demonstration board DC291A, see Figure 56 for the
schematic. This circuit uses the computer's serial port to
generate power and the SPI digital signals necessary for
starting a conversion and reading the result. It includes a
Labview application software program (see Figure 57)
which graphically captures the conversion results. It can
be used to determine noise performance, stability and
with an external source, linearity. As exemplified in the
schematic, the LTC2410 is extremely easy to use. This
demonstration board and associated software is available
by contacting Linear Technology.
LTC2410
SCK
SDO
CS
13
12
11
SCK (PD4)
MISO (PD2)
SS (PD5)
68HC11
2410 F54
LTC2410
40
TYPICAL APPLICATIO S
U
*****************************************************
* This example program transfers the LTC2410's 32-bit output *
* conversion result into four consecutive 8-bit memory locations. *
*****************************************************
*68HC11 register definition
PORTD
EQU
$1008
Port D data register
*
" , , SS* ,CSK ;MOSI,MISO,TxD ,RxD"
DDRD
EQU
$1009
Port D data direction register
SPSR
EQU
$1028
SPI control register
*
"SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0"
SPSR
EQU
$1029
SPI status register
*
"SPIF,WCOL, ,MODF; , , , "
SPDR
EQU
$102A
SPI data register; Read-Buffer; Write-Shifter
*
* RAM variables to hold the LTC2410's 32 conversion result
*
DIN1
EQU
$00
This memory location holds the LTC2410's bits 31 - 24
DIN2
EQU
$01
This memory location holds the LTC2410's bits 23 - 16
DIN3
EQU
$02
This memory location holds the LTC2410's bits 15 - 08
DIN4
EQU
$03
This memory location holds the LTC2410's bits 07 - 00
*
**********************
* Start GETDATA Routine *
**********************
*
ORG
$C000
Program start location
INIT1
LDS
#$CFFF
Top of C page RAM, beginning location of stack
LDAA
#$2F
,,1,0;1,1,1,1
*
, , SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
STAA
PORTD
Keeps SS* a logic high when DDRD, bit 5 is set
LDAA
#$38
,,1,1;1,0,0,0
STAA
DDRD
SS*, SCK, MOSI are configured as Outputs
*
MISO, TxD, RxD are configured as Inputs
*DDRD's bit 5 is a 1 so that port D's SS* pin is a general output
LDAA
#$50
STAA
SPCR
The SPI is configured as Master, CPHA = 0, CPOL = 0
*
and the clock rate is E/2
*
(This assumes an E-Clock frequency of 4MHz. For higher E-
*
Clock frequencies, change the above value of $50 to a value
*
that ensures the SCK frequency is 2MHz or less.)
GETDATA PSHX
PSHY
PSHA
LDX
#$0
The X register is used as a pointer to the memory locations
*
that hold the conversion data
LDY
#$1000
BCLR
PORTD, Y %00100000
This sets the SS* output bit to a logic
*
low, selecting the LTC2410
*
LTC2410
41
TYPICAL APPLICATIO S
U
**********************************
* The next short loop waits for the *
* LTC2410's conversion to finish before *
* starting the SPI data transfer *
**********************************
*
CONVEND LDAA
PORTD
Retrieve the contents of port D
ANDA
#%00000100
Look at bit 2
*
Bit 2 = Hi; the LTC2410's conversion is not
*
complete
*
Bit 2 = Lo; the LTC2410's conversion is complete
BNE
CONVEND
Branch to the loop's beginning while bit 2 remains
high
*
*
********************
* The SPI data transfer *
********************
*
TRFLP1
LDAA
#$0
Load accumulator A with a null byte for SPI transfer
STAA
SPDR
This writes the byte in the SPI data register and starts
*
the transfer
WAIT1
LDAA
SPSR
This loop waits for the SPI to complete a serial
transfer/exchange by reading the SPI Status Register
BPL
WAIT1
The SPIF (SPI transfer complete flag) bit is the SPSR's MSB
*
and is set to one at the end of an SPI transfer. The branch
*
will occur while SPIF is a zero.
LDAA
SPDR
Load accumulator A with the current byte of LTC2410 data
that was just received
STAA
0,X
Transfer the LTC2410's data to memory
INX
Increment the pointer
CPX
#DIN4+1 Has the last byte been transferred/exchanged?
BNE
TRFLP1
If the last byte has not been reached, then proceed to the
*
next byte for transfer/exchange
BSET
PORTD,Y %00100000 This sets the SS* output bit to a logic high,
*
de-selecting the LTC2410
PULA
Restore the A register
PULY
Restore the Y register
PULX
Restore the X register
RTS
Figure 55. This is an Example of 68HC11 Code That Captures the LTC2410's
Conversion Results Over the SPI Serial Interface Shown in Figure 54
LTC2410
42
TYPICAL APPLICATIO S
U
Figure 56. 24-Bit A/D Demo Board Schematic
Figure 57. Display Graphic
JP4
JUMPER
2
3
1
1
P1
DB9
6
9
2
7
3
8
4
5
+
2410 F56
R1
10
J1
V
EXT
D1
BAV74LT1
C4
100
F
16V
V
OUT
V
IN
GND
U2
LT1236ACN8-5
U3E
74HC14
6
2
11
10
14
3
13
4
12
5
16
6
15
10
9
8
7
1
11
2
3
2
1
1
1
4
U3F
74HC14
13
12
U3B
74HC14
3
4
U3A
74HC14
1
2
U3C
74HC14
6
5
U3D
74HC14
8
3
2
1
9
+
C3
10
F
35V
V
OUT
V
IN
GND
U1
LT1460ACN8-2.5
6
2
4
+
C1
10
F
35V
+
C2
22
F
25V
C6
0.1
F
+
C5
10
F
35V
V
CC
V
CC
V
CC
J2
GND
J3
V
CC
1
1
J5
GND
1
J7
REF
BANANA JACK
1
J6
REF
+
BANANA JACK
1
J4
V
EXT
BANANA JACK
1
J8
V
IN
+
BANANA JACK
1
J9
V
IN
BANANA JACK
1
J10
GND
BANANA JACK
R3
51k
R4
51k
R6
3k
Q1
MMBT3904LT1
R5
49.9
R7
22k
R8
51k
REF
+
F
O
REF
SCK
V
IN
+
SDO
V
IN
GND
GND
GND
CS
V
CC
GND
GND GND GND
JP3
JUMPER
2
3
1
C7
0.1
F
BYPASS CAP
FOR U3
NOTES:
INSTALL JUMBER JP1 AT PIN 1 AND PIN 2
INSTALL JUMBER JP2 AT PIN 1 AND PIN 2
INSTALL JUMBER JP3 AT PIN 1 AND PIN 2
V
CC
JP5
JUMPER
1
2
JP1
JUMPER
2
3
1
JP2
JUMPER
2
1
R2
3
U4
LTC2410CGN
LTC2410
43
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
PCB LAYOUT A D FIL
U
W
Silkscreen Top
Top Layer
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
GN16 (SSOP) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.016 0.050
(0.406 1.270)
0.015
0.004
(0.38
0.10)
45
0
8
TYP
0.007 0.0098
(0.178 0.249)
0.053 0.068
(1.351 1.727)
0.008 0.012
(0.203 0.305)
0.004 0.0098
(0.102 0.249)
0.0250
(0.635)
BSC
1
2
3
4
5
6
7
8
0.229 0.244
(5.817 6.198)
0.150 0.157**
(3.810 3.988)
16 15 14 13
0.189 0.196*
(4.801 4.978)
12 11 10 9
0.009
(0.229)
REF
LTC2410
44
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 2000
2410i LT/TP 0400 4K PRINTED IN USA
RELATED PARTS
PCB LAYOUT A D FIL
U
W
PART NUMBER
DESCRIPTION
COMMENTS
LT1019
Precision Bandgap Reference, 2.5V, 5V
3ppm/
C Drift, 0.05% Max
LT1025
Micropower Therocouple Cold Junction Compensator
80
A Supply Current, 0.5
C Initial Accuracy
LTC1043
Dual Precision Instrumentation Switched Capacitor
Precise Charge, Balanced Switching, Low Power
Building Block
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5
V Offset, 1.6
V
P-P
Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max, 5ppm/
C Drift
LT1460
Micropower Series Reference
0.075% Max, 10ppm/
C Max Drift, 2.5V, 5V and 10V Versions
LTC2400
24-Bit, No Latency
ADC in SO-8
0.3ppm Nosie, 4ppm INL, 10ppm Total Unadjusted Error, 200
A
LTC2401/LTC2402
1-/2-Channel, 24-Bit, No Latency
ADC in MSOP
0.6ppm Nosie, 4ppm INL, 10ppm Total Unadjusted Error, 200
A
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency
ADC
0.3ppm Nosie, 4ppm INL, 10ppm Total Unadjusted Error, 200
A
LTC2420
20-Bit, No Latency
ADC in SO-8
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
Bottom Layer
PDF 
ZIP