LTC2414/LTC2418

241418f

APPLICATIO S

FEATURES

DESCRIPTIO

TYPICAL APPLICATIO

The LTC

2414/LTC2418 are 8-/16-channel (4-/8-differ-

ential) micropower 24-bit

analog-to-digital convert-

ers. They operate from 2.7V to 5.5V and include an
integrated oscillator, 2ppm INL and 0.2ppm RMS noise.
They use delta-sigma technology and provide single cycle
settling time for multiplexed applications. Through a
single pin, the LTC2414/LTC2418 can be configured for
better than 110dB differential mode rejection at 50Hz or
60Hz

2%, or they can be driven by an external oscillator

for a user-defined rejection frequency. The internal oscil-
lator requires no external frequency setting components.

The LTC2414/LTC2418 accept any external differential
reference voltage from 0.1V to V

for flexible ratiometric

and remote sensing measurement applications. They can
be configured to take 4/8 differential channels or
8/16 single-ended channels. The full-scale bipolar input
range is from 0.5V

REF

to 0.5V

REF

. The reference common

mode voltage, V

REFCM

, and the input common mode volt-

age, V

INCM

, may be independently set within GND to V

The DC common mode input rejection is better than 140dB.

The LTC2414/LTC2418 communicate through a flexible
4-wire digital interface that is compatible with SPI and
MICROWIRE

protocols.

Direct Sensor Digitizer

Weight Scales

Direct Temperature Measurement

Gas Analyzers

Strain Gauge Transducers

Instrumentation

Data Acquisition

Industrial Process Control

, LTC and LT are registered trademarks of Linear Technology Corporation.

8-/16-Channel Single-Ended or 4-/8-Channel
Differential Inputs (LTC2414/LTC2418)

Low Supply Current (200

A, 4

A in Autosleep)

Differential Input and Differential Reference
with GND to V

Common Mode Range

2ppm INL, No Missing Codes

2.5ppm Full-Scale Error and 0.5ppm Offset

0.2ppm Noise

No Latency: Digital Filter Settles in a Single Cycle.
Each Conversion Is Accurate, Even After a New
Channel is Selected

Single Supply 2.7V to 5.5V Operation

Internal Oscillator--No External Components
Required

110dB Min, 50Hz/60Hz Notch Filter

8-/16-Channel

24-Bit No Latency

ADCs

No Latency

is a trademark of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corporation.

Total Unadjusted Error

vs Input Voltage

SDI

SCK

SDO

REF

2.7V TO 5.5V

COM

REF

GND

THERMOCOUPLE

DIFFERENTIAL

24-BIT

ADC

16-CHANNEL

MUX

241418 TA01a

4-WIRE
SPI INTERFACE

LTC2418

= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION

CH0
CH1

21
22

CH7
CH8

CH15

INPUT VOLTAGE (V)

2.5 2

1.0

2.0

TUE (ppm OF V

REF

)

1.5

0.5

1.5

2414/18 TA01b

2.5

= 5V

REF

= 5V

INCM

= V

REFCM

= 2.5V

= GND

= 85

= 25

= 45

LTC2414/LTC2418

241418f

(Notes 1, 2)

ORDER PART

NUMBER

Supply Voltage (V

) to GND ....................... 0.3V to 7V

Analog Input Voltage to GND ....... 0.3V to (V

+ 0.3V)

Reference Input Voltage to GND .. 0.3V to (V

+ 0.3V)

Digital Input Voltage to GND ........ 0.3V to (V

+ 0.3V)

Digital Output Voltage to GND ..... 0.3V to (V

+ 0.3V)

JMAX

= 125

= 110

C/W

LTC2414CGN

LTC2414IGN

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Operating Temperature Range

LTC2414/LTC2418C ................................ 0

C to 70

LTC2414/LTC2418I ............................ 40

C to 85

Storage Temperature Range ................. 65

C to 150

Lead Temperature (Soldering, 10 sec).................. 300

TOP VIEW

GN PACKAGE

28-LEAD PLASTIC SSOP

COM

REF

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

SDI

SCK

SDO

GND

ORDER PART

NUMBER

LTC2418CGN

LTC2418IGN

TOP VIEW

GN PACKAGE

28-LEAD PLASTIC SSOP

CH8

CH9

CH10

CH11

CH12

CH13

CH14

CH15

COM

REF

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

SDI

SCK

SDO

GND

JMAX

= 125

= 110

C/W

LTC2414/LTC2418

241418f

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input Common Mode Rejection DC

2.5V

REF

, REF

= GND,

130

140

GND

= IN

5V (Note 5)

Input Common Mode Rejection

2.5V

REF

, REF

= GND,

140

60Hz

GND

= IN

5V (Notes 5, 7)

Input Common Mode Rejection

2.5V

REF

, REF

= GND,

140

50Hz

GND

= IN

5V (Notes 5, 8)

Input Normal Mode Rejection

(Notes 5, 7)

110

140

60Hz

Input Normal Mode Rejection

(Notes 5, 8)

110

140

50Hz

Reference Common Mode

2.5V

REF

, GND

REF

2.5V,

130

140

Rejection DC

REF

= 2.5V, IN

= IN

= GND (Note 5)

Power Supply Rejection, DC

REF

= 2.5V, REF

= GND, IN

= IN

= GND

110

Power Supply Rejection, 60Hz

REF

= 2.5V, REF

= GND, IN

= IN

= GND (Note 7)

120

Power Supply Rejection, 50Hz

REF

= 2.5V, REF

= GND, IN

= IN

= GND (Note 8)

120

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. (Notes 3, 4)

CO VERTER CHARACTERISTICS

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Resolution (No Missing Codes)

0.1V

REF

, 0.5 · V

REF

0.5 · V

REF

(Note 5)

Bits

Integral Nonlinearity

4.5V

5.5V, REF

= 2.5V, REF

= GND, V

INCM

= 1.25V (Note 6)

ppm of V

REF

5.5V, REF

= 5V, REF

= GND, V

INCM

= 2.5V (Note 6)

ppm of V

REF

= 2.5V, REF

= GND, V

INCM

= 1.25V (Note 6)

ppm of V

REF

Offset Error

2.5V

REF

, REF

= GND,

2.5

GND

= IN

(Note 14)

Offset Error Drift

2.5V

REF

, REF

= GND,

nV/

GND

= IN

Positive Full-Scale Error

2.5V

REF

, REF

= GND,

2.5

ppm of V

REF

= 0.75 · REF

, IN

= 0.25 · REF

Positive Full-Scale Error Drift

2.5V

REF

, REF

= GND,

0.03

ppm of V

REF

= 0.75 · REF

, IN

= 0.25 · REF

Negative Full-Scale Error

2.5V

REF

, REF

= GND,

2.5

ppm of V

REF

= 0.25 · REF

, IN

= 0.75 · REF

Negative Full-Scale Error Drift

2.5V

REF

, REF

= GND,

0.03

ppm of V

REF

= 0.25 · REF

, IN

= 0.75 · REF

Total Unadjusted Error

4.5V

5.5V, REF

= 2.5V, REF

= GND, V

INCM

= 1.25V

ppm of V

REF

5.5V, REF

= 5V, REF

= GND, V

INCM

= 2.5V

ppm of V

REF

= 2.5V, REF

= GND, V

INCM

= 1.25V

ppm of V

REF

Output Noise

5.5V, REF

= 5V, V

REF

= GND,

RMS

GND

= IN

5V (Note 13)

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. (Notes 3, 4)

ELECTRICAL CHARACTERISTICS

LTC2414/LTC2418

241418f

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Absolute/Common Mode IN

Voltage

GND 0.3

+ 0.3

Absolute/Common Mode IN

Voltage

GND 0.3

+ 0.3

Input Differential Voltage Range

REF

(IN

)

REF

Absolute/Common Mode REF

Voltage

0.1

REF

Absolute/Common Mode REF

Voltage

GND

0.1

REF

Reference Differential Voltage Range

0.1

(REF

REF

)

(IN

)

Sampling Capacitance

(IN

)

Sampling Capacitance

(REF

)

REF

Sampling Capacitance

(REF

)

REF

Sampling Capacitance

DC_LEAK

(IN

)

DC Leakage Current

CS = V

= 5.5V, IN

= GND

DC_LEAK

(IN

)

DC Leakage Current

CS = V

= 5.5V, IN

= 5V

DC_LEAK

(REF

)

REF

DC Leakage Current

CS = V

= 5.5V, REF

= 5V

DC_LEAK

(REF

)

REF

DC Leakage Current

CS = V

= 5.5V, REF

= GND

Off Channel to In Channel Isolation

140

= 100

)

1Hz

140

= 15,3600Hz

140

OPEN

MUX Break-Before-Make Interval

2.7V

5.5V

100

300

S(OFF)

Channel Off Leakage Current

Channel at V

and GND

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. (Note 3)

A ALOG I PUT A D REFERE CE

The

denotes specifications which apply over the full

operating temperature range, otherwise specifications are at T

= 25

C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

High Level Input Voltage

2.7V

5.5V

2.5

CS, F

, SDI

2.7V

3.3V

2.0

Low Level Input Voltage

4.5V

5.5V

0.8

CS, F

, SDI

2.7V

5.5V

0.6

High Level Input Voltage

2.7V

5.5V (Note 9)

2.5

SCK

2.7V

3.3V (Note 9)

2.0

Low Level Input Voltage

4.5V

5.5V (Note 9)

0.8

SCK

2.7V

5.5V (Note 9)

0.6

Digital Input Current

CS, F

, SDI

Digital Input Current

(Note 9)

SCK

Digital Input Capacitance

CS, F

, SDI

Digital Input Capacitance

(Note 9)

SCK

High Level Output Voltage

= 800

0.5

SDO

DIGITAL I PUTS A D DIGITAL OUTPUTS

LTC2414/LTC2418

241418f

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

2.7

5.5

Supply Current

Conversion Mode

CS = 0V (Note 12)

200

300

Sleep Mode

CS = V

(Note 12)

Sleep Mode

CS = V

, 2.7V

3.3V (Note 12)

The

denotes specifications which apply over the full operating temperature range,

otherwise specifications are at T

= 25

C. (Note 3)

POWER REQUIRE E TS

The

denotes specifications which apply over the full

operating temperature range, otherwise specifications are at T

= 25

C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Low Level Output Voltage

= 1.6mA

0.4

SDO

High Level Output Voltage

= 800

A (Note 10)

0.5

SCK

Low Level Output Voltage

= 1.6mA (Note 10)

0.4

SCK

Hi-Z Output Leakage

SDO

DIGITAL I PUTS A D DIGITAL OUTPUTS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

EOSC

External Oscillator Frequency Range

2.56

2000

kHz

HEO

External Oscillator High Period

0.25

390

LEO

External Oscillator Low Period

0.25

390

CONV

Conversion Time

= 0V

130.86

133.53

136.20

= V

157.03

160.23

163.44

External Oscillator (Note 11)

20510/f

EOSC

(in kHz)

ISCK

Internal SCK Frequency

Internal Oscillator (Note 10)

19.2

kHz

External Oscillator (Notes 10, 11)

EOSC

kHz

ISCK

Internal SCK Duty Cycle

(Note 10)

ESCK

External SCK Frequency Range

(Note 9)

2000

kHz

LESCK

External SCK Low Period

(Note 9)

250

HESCK

External SCK High Period

(Note 9)

250

DOUT_ISCK

Internal SCK 32-Bit Data Output Time

Internal Oscillator (Notes 10, 12)

1.64

1.67

1.70

External Oscillator (Notes 10, 11)

256/f

EOSC

(in kHz)

DOUT_ESCK

External SCK 32-Bit Data Output Time

(Note 9)

32/f

ESCK

(in kHz)

The

denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T

= 25

C. (Note 3)

TI I G CHARACTERISTICS

LTC2414/LTC2418

241418f

Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.

Note 2: All voltage values are with respect to GND.

Note 3: V

= 2.7V to 5.5V unless otherwise specified.

REF

= REF

REF

, V

REFCM

= (REF

+ REF

)/2; V

= IN

INCM

= (IN

+ IN

)/2, IN

and IN

are defined as the selected positive

and negative input respectively.

Note 4: F

pin tied to GND or to V

or to external conversion clock

source with f

EOSC

= 153600Hz unless otherwise specified.

Note 5: Guaranteed by design, not subject to test.

Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.

Note 7: F

= 0V (internal oscillator) or f

EOSC

= 153600Hz

(external oscillator).

Note 8: F

= V

(internal oscillator) or f

EOSC

= 128000Hz

(external oscillator).

Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is f

ESCK

and is expressed in kHz.

Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance C

LOAD

= 20pF.

Note 11: The external oscillator is connected to the F

pin. The external

oscillator frequency, f

EOSC

, is expressed in kHz.

Note 12: The converter uses the internal oscillator.
F

= 0V or F

= V

Note 13: The output noise includes the contribution of the internal
calibration operations.

Note 14: Guaranteed by design and test correlation.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

to SDO Low

200

to SDO High Z

200

to SCK

(Note 10)

200

to SCK

(Note 9)

KQMAX

SCK

to SDO Valid

220

KQMIN

SDO Hold After SCK

(Note 5)

SCK Set-Up Before CS

SCK Hold After CS

SDI Setup Before SCK

(Note 5)

100

SDI Hold After SCK

(Note 5)

100

The

denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T

= 25

C. (Note 3)

TI I G CHARACTERISTICS

LTC2414/LTC2418

241418f

TYPICAL PERFOR A CE CHARACTERISTICS

Total Unadjusted Error
(V

= 5V, V

REF

= 5V)

Total Unadjusted Error
(V

= 5V, V

REF

= 2.5V)

Total Unadjusted Error
(V

= 2.7V, V

REF

= 2.5V)

Integral Nonlinerity
(V

= 5V, V

REF

= 5V)

Integral Nonlinerity
(V

= 5V, V

REF

= 2.5V)

Integral Nonlinerity
(V

= 2.7V, V

REF

= 2.5V)

Noise Histogram
(V

= 5V, V

REF

= 5V)

Noise Histogram
(V

= 2.7V, V

REF

= 2.5V)

Long Term ADC Readings

INPUT VOLTAGE (V)

2.5 2.0

1.0

2.0

TUE (ppm OF V

REF

)

1.5

0.5

1.5

241418 G01

2.5

= GND

= 5V

REF

= 5V

INCM

= V

REFCM

= 2.5V

= 25

= 45

= 85

INPUT VOLTAGE (V)

1.25

TUE (ppm OF V

REF

)

0.75

0.25

0.75

241418 G02

1.25

= GND

= 5V

REF

= 2.5V

INCM

= V

REFCM

= 1.25V

= 25

= 85

= 45

INPUT VOLTAGE (V)

1.25

TUE (ppm OF V

REF

)

0.75

0.25

0.75

241418 G03

1.25

= GND

= 2.7V

REF

= 2.5V

INCM

= V

REFCM

= 1.25V

= 85

= 45

= 25

INPUT VOLTAGE (V)

2.5 2.0

1.0

2.0

INL (ppm OF V

REF

)

1.5

0.5

1.5

241418 G04

2.5

= GND

= 5V

REF

= 5V

INCM

= V

REFCM

= 2.5V

= 25

= 45

= 85

INPUT VOLTAGE (V)

INL (ppm OF V

REF

)

241418 G05

= GND

= 5V

REF

= 2.5V

INCM

= V

REFCM

= 1.25V

= 25

= 85

= 45

1.25

0.75

0.25

0.75

1.25

INPUT VOLTAGE (V)

1.25

INL (ppm OF V

REF

)

0.75

0.25

0.75

241418 G06

1.25

= GND

= 2.7V

REF

= 2.5V

INCM

= V

REFCM

= 1.25V

= 85

= 45

= 25

OUTPUT CODE (ppm OF V

REF

)

1.2

NUMBER OF READINGS (%)

0.6

241418 G07

0.6

10,000 CONSECUTIVE READINGS
F

= GND

= 25

= 5V

REF

= 5V

= 0V

INCM

= 2.5V

GAUSSIAN
DISTRIBUTION
m = 0.24ppm

= 0.183ppm

OUTPUT CODE (ppm OF V

REF

)

NUMBER OF READINGS (%)

241418 G08

2.4

1.8

1.2

0.6

1.2

10,000 CONSECUTIVE READINGS
F

= GND

= 25

= 2.7V

REF

= 2.5V

= 0V

INCM

= 2.5V

GAUSSIAN
DISTRIBUTION
m = 0.48ppm

= 0.375ppm

TIME (HOURS)

ADC READING (ppm OF V

REF

)

1.0

0.5

1.0

1.5

LTXXXX · TPCXX

RMS NOISE = 0.19ppm
F

= GND

= 25

= 5V

REF

= 5V

= 0V

INCM

= 2.5V

LTC2414/LTC2418

241418f

TYPICAL PERFOR A CE CHARACTERISTICS

RMS Noise vs Input Differential
Voltage

RMS Noise vs V

INCM

RMS Noise vs Temperature (T

)

RMS Noise vs V

REF

Offset Error vs V

INCM

Offset Error vs Temperature

Offset Error vs V

REF

RMS NOISE (ppm OF V

REF

)

0.5

0.4

0.3

0.2

0.1

INPUT DIFFERENTIAL VOLTAGE (V)

2.5 2.0

1.0

2.0

1.5

0.5

1.5

241418 G10

2.5

= GND

= 25

= 5V

REF

= 5V

INCM

= 2.5V

INCM

(V)

RMS NOISE (

1.0

0.9

0.8

0.7

0.6

0.5

241418 G11

= GND

= 25

= 5V

REF

= 5V

REF

= GND

= 0V

INCM

= GND

TEMPERATURE (

RMS NOISE (

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

241418 G12

100

= GND

= 5V

REF

= 5V

= 0V

INCM

= GND

(V)

2.7

RMS NOISE (

1.0

0.9

0.8

0.7

0.6

0.5

3.5

4.3

4.7

241418 G13

3.1

3.9

5.1

5.5

= GND

= 25

= 0V

INCM

= GND

REF

= 2.5V

REF

= GND

REF

(V)

RMS NOISE (

1.0

0.9

0.8

0.7

0.6

0.5

241418 G14

= GND

= 25

= 5V

= 0V

INCM

= GND

REF

= GND

INCM

(V)

OFFSET ERROR (ppm OF V

REF

)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

241418 G15

= GND

= 25

= 5V

REF

= 5V

REF

= GND

= 0V

TEMPERATURE (

45 30

OFFSET ERROR (ppm OF V

REF

)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

241418 G16

= GND

= 5V

REF

= 5V

= 0V

INCM

= GND

(V)

2.7

OFFSET ERROR (ppm OF V

REF

)

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

3.5

4.3

4.7

241418 G17

3.1

3.9

5.1

5.5

= GND

= 25

= 0V

INCM

= GND

REF

= 2.5V

REF

= GND

REF

(V)

OFFSET ERROR (ppm OF V

REF

)

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

241418 G18

= GND

= 25

= 5V

= 0V

INCM

= GND

REF

= GND

LTC2414/LTC2418

241418f

TYPICAL PERFOR A CE CHARACTERISTICS

Full-Scale Error vs Temperature

Full-Scale Error vs V

REF

PSRR vs Frequency at V

Conversion Current
vs Temperature

Supply Current at Elevated
Output Rates (F

Over Driven)

Sleep Mode Current
vs Temperature

TEMPERATURE (

FULL-SCALE ERROR (ppm OF V

REF

)

241418 G19

100

+FS ERROR

FS ERROR

= GND

= 5V

REF

= 5V

INCM

= 2.5V

(V)

2.7

FULL-SCALE ERROR (ppm OF V

REF

)

3.5

3.9

4.3

4.7

5.1

5.5

241418 G20

3.1

+FS ERROR

FS ERROR

= GND

= 25

REF

= 2.5V

INCM

= 0.5V

REF

= GND

REF

(V)

FULL-SCALE ERROR (ppm OF V

REF

)

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

241418 G21

0.5

+FS ERROR

FS ERROR

= GND

= 25

= 5V

INCM

= 0.5V

REF

= GND

FREQUENCY AT V

(Hz)

REJECTION (dB)

100

120

140

241418 G22

100

1000 10000 100000 1000000

= GND

= 25

= 4.1V

REF

= 2.5V

REF

= GND

SDI = GND

FREQUENCY AT V

(Hz)

REJECTION (dB)

180

241418 G23

120

240

100

120

140

150

210

= GND

= 25

= 4.1V

1.4V

REF

= 2.5V

REF

= GND

SDI = GND

REJECTION (dB)

241418 G24

100

120

140

= GND

= 25

= 4.1V

0.7V

P-P

REF

= 2.5V

REF

= GND

SDI = GND

FREQUENCY AT V

(Hz)

15250

15300

15350

15400

15450

TEMPERATURE (

45 30 15

CONVERSION CURRENT (

241418 G25

240

230

220

210

200

190

180

170

160

CS = GND
F

= GND

SCK = NC
SDO = NC
SDI = GND

= 5.5V

= 5V

= 3V

= 2.7V

SUPPLY CURRENT (

1000

900

800

700

600

500

400

300

200

100

OUTPUT DATA RATE (READINGS/SEC)

241418 G26

10 20 30 40

50 60 70

80 90 100

CS = GND
F

= EXT OSC

= GND

SCK = NC
SDO = NC
SDI = GND
T

= 25

REF

= V

= 5V

= 3V

TEMPERATURE (

45 30 15

SLEEP-MODE CURRENT (

241418 G27

CS = V

= GND

SCK = NC
SDO = NC
SDI = GND

= 5.5V

= 5V

= 3V

= 2.7V

LTC2414/LTC2418

241418f

CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8): Analog
Inputs. May be programmed for single-ended or differen-
tial mode. CH8 to CH15 (Pin 1 to Pin 8) not connected on
the LTC2414.

(Pin 9): Positive Supply Voltage. Bypass to GND

(Pin 15) with a 10

F tantalum capacitor in parallel with

0.1

F ceramic capacitor as close to the part as possible.

COM (Pin 10): The common negative input (IN

) for all

single-ended multiplexer configurations. The voltage on
Channel 0 to 15 and COM input pins can have any value
between GND 0.3V and V

+ 0.3V. Within these limits,

the two selected inputs (IN

and IN

) provide a bipolar

input range (V

= IN

) from 0.5 · V

REF

to 0.5 · V

REF

Outside this input range, the converter produces unique
overrange and underrange output codes.

REF

(Pin 11), REF

(Pin 12): Differential Reference

Input. The voltage on these pins can have any value
between GND and V

as long as the positive reference

input, REF

, is maintained more positive than the negative

reference input, REF

, by at least 0.1V.

GND (Pin 15): Ground. Connect this pin to a ground plane
through a low impedance connection.

CS (Pin 16): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.

SDO (Pin 17): Three-State Digital Output. During the Data
Output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = V

), the SDO pin

is in a high impedance state. During the Conversion and
Sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.

SCK (Pin 18): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
output for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as the digital input for the external serial
interface clock during the Data Output period. A weak
internal pull-up is automatically activated in Internal Serial
Clock Operation mode. The Serial Clock Operation mode is
determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.

(Pin 19): Frequency Control Pin. Digital input that

controls the ADC's notch frequencies and conversion
time. When the F

pin is connected to V

= V

), the

converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the F

pin is connected

to GND (F

= 0V), the converter uses its internal oscillator

and the digital filter first null is located at 60Hz. When F

is driven by an external clock signal with a frequency f

EOSC

the converters use this signal as their system clock and the
digital filter first null is located at a frequency f

EOSC

/2560.

SDI (Pin 20): Serial Digital Data Input. During the Data
Output period, this pin is used to shift in the multiplexer
address started from the first rising SCK edge. During the
Conversion and Sleep periods, this pin is in the DON'T
CARE state. However, a HIGH or LOW logic level should be
maintained on SDI in the DON'T CARE mode to avoid an
excessive current in the SDI input buffers.

NC Pins: Do Not Connect.

PI FU CTIO S

LTC2414/LTC2418

241418f

CS is HIGH. While in the sleep state, power consumption
is reduced by nearly two orders of magnitude. The conver-
sion result is held indefinitely in a static shift register while
the converter is in the sleep state.

Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
after the first rising edge of SCK, the device begins output-
ting the conversion result and inputting channel selection
bits. Taking CS high at this point will terminate the data
output state and start a new conversion. The channel
selection control bits are shifted in through SDI from the

Figure 1

FU CTIO AL BLOCK DIAGRA

TEST CIRCUITS

AUTOCALIBRATION

AND CONTROL

DIFFERENTIAL

3RD ORDER

MODULATOR

DECIMATING FIR

ADDRESS

INTERNAL

OSCILLATOR

SERIAL

INTERFACE

GND

CH0
CH1

·
·
·

CH15

COM

MUX

SDO

SCK

REF

SDI

(INT/EXT)

241418 F01

1.69k

SDO

241418 TA02

Hi-Z TO V

TO V

TO Hi-Z

LOAD

= 20pF

1.69k

SDO

241418 TA03

Hi-Z TO V

TO V

TO Hi-Z

LOAD

= 20pF

CONVERTER OPERATION

Converter Operation Cycle

The LTC2414/LTC2418 are multichannel, low power, delta-
sigma analog-to-digital converters with an easy-to-use
4-wire serial interface (see Figure 1). Their operation is made
up of three states. The converter operating cycle begins with
the conversion, followed by the low power sleep state and
ends with the data input/output (see Figure 2). The 4-wire
interface consists of serial data input (SDI), serial data out-
put (SDO), serial clock (SCK) and chip select (CS).

Initially, the LTC2414 or LTC2418 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. The part remains in the sleep state as long as

APPLICATIO S I FOR ATIO

LTC2414/LTC2418

241418f

first rising edge of SCK and depending on the control bits,
the converter updates its channel selection immediately
and is valid for the next conversion. The details of channel
selection control bits are described in the Input Data Mode
section. The output data is shifted out the SDO pin under
the control of the serial clock (SCK). The output data is
updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 32 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion and the cycle
repeats.

Through timing control of the CS and SCK pins, the
LTC2414/LTC2418 offer several flexible modes of opera-
tion (internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.

Conversion Clock

A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz or

APPLICATIO S I FOR ATIO

Figure 2. LTC2414/LTC2418 State Transition Diagram

CONVERT

POWER UP

= CH0, IN

= CH1

SLEEP

DATA OUTPUT

ADDRESS INPUT

241418 F02

TRUE

FALSE

CS = LOW

AND

SCK

60Hz plus their harmonics. The filter rejection perfor-
mance is directly related to the accuracy of the converter
system clock. The LTC2414/LTC2418 incorporate a highly
accurate on-chip oscillator. This eliminates the need for
external frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the LTC2414/
LTC2418 achieve a minimum of 110dB rejection at the line
frequency (50Hz or 60Hz

2%).

Ease of Use

The LTC2414/LTC2418 data output has no latency, filter
settling delay or redundant data associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog voltages is easy.

The LTC2414/LTC2418 perform offset and full-scale cali-
brations in every conversion cycle. This calibration is trans-
parent to the user and has no effect on the cyclic operation
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with re-
spect to time, supply voltage change and temperature drift.

Power-Up Sequence

The LTC2414/LTC2418 automatically enter an internal
reset state when the power supply voltage V

drops

below approximately 2V. This feature guarantees the
integrity of the conversion result and of the serial interface
mode selection. (See the 3-wire I/O sections in the Serial
Interface Timing Modes section.)

When the V

voltage rises above this critical threshold,

the converter creates an internal power-on-reset (POR)
signal with a typical duration of 1ms. The POR signal
clears all internal registers. Following the POR signal, the
LTC2414/LTC2418 start a normal conversion cycle and
follow the succession of states described above. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.

Reference Voltage Range

The LTC2414/LTC2418 accept a truly differential external
reference voltage. The absolute/common mode voltage

LTC2414/LTC2418

241418f

specification for the REF

and REF

pins covers the entire

range from GND to V

. For correct converter operation,

the REF

pin must always be more positive than the REF

pin.

The LTC2414/LTC2418 can accept a differential reference
voltage from 0.1V to V

. The converter output noise is

determined by the thermal noise of the front-end circuits,
and, as such, its value in nanovolts is nearly constant with
reference voltage. A decrease in reference voltage will not
significantly improve the converter's effective resolution.
On the other hand, a reduced reference voltage will im-
prove the converter's overall INL performance. A reduced
reference voltage will also improve the converter perfor-
mance when operated with an external conversion clock
(external F

signal) at substantially higher output data rates.

Input Voltage Range

The two selected pins are labeled IN

and IN

(see Tables

1 and 2). Once selected (either differential or single-ended
multiplexing mode), the analog input is differential with a
common mode range for the IN

and IN

input pins ex-

tending from GND 0.3V to V

+ 0.3V. Outside

these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase rap-
idly. Within these limits, the LTC2414/LTC2418 convert
the bipolar differential input signal, V

= IN

, from

FS = 0.5 · V

REF

to +FS = 0.5 · V

REF

where V

REF

. Outside this range the converters indicate

the overrange or the underrange condition using distinct
output codes.

Input signals applied to IN

and IN

pins may extend

300mV below ground or above V

. In order to limit any

fault current, resistors of up to 5k may be added in series
with the IN

or IN

pins without affecting the performance

of the device. In the physical layout, it is important to
maintain the parasitic capacitance of the connection be-
tween these series resistors and the corresponding pins
as low as possible; therefore, the resistors should be
located as close as practical to the pins. In addition, series
resistors will introduce a temperature dependent offset
error due to the input leakage current. A 1nA input leakage

current will develop a 1ppm offset error on a 5k resistor if
V

REF

= 5V. This error has a very strong temperature

dependency.

Input Data Format

When the LTC2414/LTC2418 are powered up, the default
selection used for the first conversion is IN

= CH0 and IN

= CH1 (Address = 00000). In the data input/output mode
following the first conversion, a channel selection can be
updated using an 8-bit word. The LTC2414/LTC2418
serial input data is clocked into the SDI pin on the rising
edge of SCK (see Figure 3). The input is composed of an
8-bit word with the first 3 bits acting as control bits and the
remaining 5 bits as the channel address bits.

The first 2 bits are always 10 for proper updating opera-
tion. The third bit is EN. For EN = 1, the following 5 bits are
used to update the input channel selection. For EN = 0,
previous channel selection is kept and the following bits
are ignored. Therefore, the address is updated when the 3
control bits are 101 and kept for 100. Alternatively, the 3
control bits can be all zero to keep the previous address.
This alternation is intended to simplify the SDI interface
allowing the user to simply connect SDI to ground if no
update is needed. Combinations other than 101, 100 and
000 of the 3 control bits should be avoided.

When update operation is set (101), the following 5 bits
are the channel address. The first bit, SGL, decides if the
differential selection mode (SGL = 0) or the single-ended
selection mode is used (SGL = 1). For SGL = 0, two
adjacent channels can be selected to form a differential
input; for SGL = 1, one of the 8 channels (CH0-CH7) for the
LTC2414 or one of the 16 channels (CH0-CH15) for the
LTC2418 is selected as the positive input and the COM pin
is used as the negative input. For the LTC2414, the lower
half channels (CH0-CH7) are used and the channel ad-
dress bit A2 should be always 0, see Table 1. While for the
LTC2418, all the 16 channels are used and the size of the
corresponding selection table (Table 2) is doubled from
that of the LTC2414 (Table 1). For a given channel selec-
tion, the converter will measure the voltage between the
two channels indicated by IN

and IN

in the selected row

of Tables 1 or 2.

APPLICATIO S I FOR ATIO

LTC2414/LTC2418

241418f

APPLICATIO S I FOR ATIO

Figure 3a. Input/Output Data Timing

SDO

Hi-Z

SIG

DMY

BIT29

MSB

B22

CONVERSON RESULT

BIT28

BIT27

BIT26

BIT25

BIT24

LSB

BIT6

SGL

BIT5

BIT3

BIT2

BIT1

PARITY

BIT0

ODD/
SIGN

BIT4

BIT30

SCK

SDI

SLEEP

DATA INPUT/OUTPUT

BIT31

EOC

SGL

DON'T CARE

CONVERSION

241418 F03a

ODD/
SIGN

ADDRESS CORRESPONDING TO RESULT

ADDRESS

N 1

CONVERSION RESULT

N 1

ADDRESS

N + 1

ADDRESS

N + 2

OUTPUT

N 1

OUTPUT

N + 1

SDO

SCK

SDI

OPERATION

Hi-Z

DON'T CARE

CONVERSION N

241418 F03b

CONVERSION N + 1

DON'T CARE

Hi-Z

CONVERSION RESULT

N + 1

ADDRESS

N + 1

Figure 3b. Typical Operation Sequence

Table 1. Channel Selection for the LTC2414 (Bit A2 Should Always Be 0)

MUX ADDRESS

CHANNEL SELECTION

ODD/

SGL

SIGN

A2 A1 A0

COM

*Default at power up

LTC2414/LTC2418

241418f

Table 2. Channel Selection for the LTC2418

MUX ADDRESS

CHANNEL SELECTION

ODD/

SGL

SIGN

A2 A1 A0

COM

*Default at power up

APPLICATIO S I FOR ATIO

Output Data Format

The LTC2414/LTC2418 serial output data stream is 32 bits
long. The first 3 bits represent status information indicat-
ing the sign and conversion state. The next 23 bits are the
conversion result, MSB first. The next 5 bits (Bit 5 to Bit 1)

indicate which channel the conversion just performed was
selected. The address bits programmed during this data
output phase select the input channel for the next conver-
sion cycle. These address bits are output during the sub-
sequent data read, as shown in Figure 3b. The last bit is a

LTC2414/LTC2418

241418f

parity bit representing the parity of the previous 31 bits. The
parity bit is useful to check the output data integrity espe-
cially when the output data is transmitted over a distance.
The third and fourth bits together are also used to indicate
an underrange condition (the differential input voltage is be-
low FS) or an overrange condition (the differential input
voltage is above + FS).

Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.

Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.

Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V

is >0, this bit is HIGH. If V

is <0, this

bit is LOW.

Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below FS.

The function of these bits is summarized in Table 3.

Table 3. LTC2414/LTC2418 Status Bits

Bit 31

Bit 30 Bit 29 Bit 28

Input Range

EOC

DMY

SIG

MSB

0.5 · V

REF

< 0.5 · V

REF

0.5 · V

REF

< 0V

< 0.5 · V

REF

Bits 28-6 are the 23-bit conversion result MSB first.

Bit 6 is the least significant bit (LSB).

Bits 5-1 are the corresponding channel selection bits for
the present conversion result with bit SGL output first as
shown in Figure 3.

Bit 0 is the parity bit representing the parity of the previous
31 bits. Including the parity bit, the total numbers of 1's
and 0's in the output data are always even.

Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.

In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 4 summarizes
the output data format.

As long as the voltage applied to any channel (CH0-CH15,
COM) is maintained within the 0.3V to (V

+ 0.3V)

absolute maximum operating range, a conversion result is
generated for any differential input voltage V

from

FS = 0.5 · V

REF

to +FS = 0.5 · V

REF

. For differential input

voltages greater than +FS, the conversion result is clamped
to the value corresponding to the +FS + 1LSB. For differ-
ential input voltages below FS, the conversion result is
clamped to the value corresponding to FS 1LSB.

Frequency Rejection Selection (F

)

The LTC2414/LTC2418 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz

2% or 60Hz

2%. For

60Hz rejection, F

should be connected to GND while for

50Hz rejection the F

pin should be connected to V

The selection of 50Hz or 60Hz rejection can also be made
by driving F

to an appropriate logic level. A selection

change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.

APPLICATIO S I FOR ATIO

LTC2414/LTC2418

241418f

When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2414/
LTC2418 can operate with an external conversion clock.
The converter automatically detects the presence of an
external clock signal at the F

pin and turns off the internal

oscillator. The frequency f

EOSC

of the external signal must

be at least 2560Hz (1Hz notch frequency) to be detected.
The external clock signal duty cycle is not significant as
long as the minimum and maximum specifications for the
high and low periods t

HEO

and t

LEO

are observed.

While operating with an external conversion clock of a
frequency f

EOSC

, the converter provides better than 110dB

normal mode rejection in a frequency range f

EOSC

/2560

4% and its harmonics. The normal mode rejection as a

function of the input frequency deviation from f

EOSC

/2560

is shown in Figure 4.

Whenever an external clock is not present at the F

pin, the

converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The converter
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the

serial clock duty cycle may be affected but the serial data
stream will remain valid.

Table 5 summarizes the duration of each state and the
achievable output data rate as a function of F

SERIAL INTERFACE PINS

The LTC2414/LTC2418 transmit the conversion results
and receive the start of conversion command through a
synchronous 4-wire interface. During the conversion and
sleep states, this interface can be used to assess the con-
verter status and during the data I/O state it is used to read
the conversion result and write in channel selection bits.

Figure 4. LTC2414/LTC2418 Normal Mode Rejection
When Using an External Oscillator of Frequency f

EOSC

DIFFERENTIAL INPUT SIGNAL FREQUENCY

DEVIATION FROM NOTCH FREQUENCY f

EOSC

/2560(%)

NORMAL MODE REJECTION (dB)

241418 F04

100

105

110

115

120

125

130

135

140

APPLICATIO S I FOR ATIO

Table 4. LTC2414/LTC2418 Output Data Format

Differential Input Voltage

Bit 31

Bit 30

Bit 29

Bit 28

Bit 27

Bit 26

Bit 25

...

Bit 6

EOC

DMY

SIG

MSB

LSB

0.5 · V

REF

...

0.5 · V

REF

** 1LSB

...

0.25 · V

REF

...

0.25 · V

REF

** 1LSB

...

1LSB

...

0.25 · V

REF

...

0.25 · V

REF

** 1LSB

...

0.5 · V

REF

...

* < 0.5 · V

REF

...

*The differential input voltage V

= IN

**The differential reference voltage V

REF

= REF

REF

LTC2414/LTC2418

241418f

Table 5. LTC2414/LTC2418 State Duration

State

Operating Mode

Duration

CONVERT

Internal Oscillator

= LOW

133ms, Output Data Rate

7.5 Readings/s

(60Hz Rejection)

= HIGH

160ms, Output Data Rate

6.2 Readings/s

(50Hz Rejection)

External Oscillator

= External Oscillator

20510/f

EOSC

s, Output Data Rate

EOSC

/20510 Readings/s

with Frequency f

EOSC

kHz

EOSC

/2560 Rejection)

SLEEP

As Long As CS = HIGH Until CS = LOW and SCK

DATA OUTPUT

Internal Serial Clock

= LOW/HIGH

As Long As CS = LOW But Not Longer Than 1.67ms

(Internal Oscillator)

(32 SCK cycles)

= External Oscillator with

As Long As CS = LOW But Not Longer Than 256/f

EOSC

Frequency f

EOSC

kHz

(32 SCK cycles)

External Serial Clock with

As Long As CS = LOW But Not Longer Than 32/f

SCK

Frequency f

SCK

kHz

(32 SCK cycles)

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 18) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock and each
input bit is shifted in the SDI pin on the rising edge of the
serial clock.

In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2414/LTC2418 create their own serial
clock by dividing the internal conversion clock by 8. In the
External SCK mode of operation, the SCK pin is used as
input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CS pin. If SCK is HIGH or float-
ing at power-up or during this transition, the converter
enters the internal SCK mode. If SCK is LOW at power-up
or during this transition, the converter enters the external
SCK mode.

Serial Data Input (SDI)

The serial data input pin, SDI (Pin 20), is used to shift in the
channel control bits during the data output state to prepare
the channel selection for the following conversion.

When CS (Pin 16) is HIGH or the converter is in the con-
version state, the SDI input is ignored and may be driven
HIGH or LOW. When CS goes LOW and the conversion is
complete, SDO goes low and then SDI starts to shift in bits
on the rising edge of SCK.

Serial Data Output (SDO)

The serial data output pin, SDO (Pin 17), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.

When CS (Pin 16) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.

Chip Select Input (CS)

The active LOW chip select, CS (Pin 16), is used to test the
conversion status and to enable the data input/output
transfer as described in the previous sections.

In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2414/LTC2418 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CS pin after the converter has entered the data input/
output state (i.e., after the first rising edge of SCK occurs
with CS = LOW). If the device has not finished loading the

APPLICATIO S I FOR ATIO

LTC2414/LTC2418

241418f

Table 6. LTC2414/LTC2418 Interface Timing Modes

Conversion

Data

Connection

SCK

Cycle

Output

and

Configuration

Source

Control

Waveforms

External SCK, Single Cycle Conversion

External

CS and SCK

Figures 5, 6

External SCK, 3-Wire I/O

External

SCK

Figure 7

Internal SCK, Single Cycle Conversion

Internal

Figures 8, 9

Internal SCK, 3-Wire I/O, Continuous Conversion

Internal

Continuous

Internal

Figure 10

last input bit A0 of SDI by the time CS pulled HIGH, the
address information is discarded and the previous
address is kept.

Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by F

SERIAL INTERFACE TIMING MODES

The LTC2414/LTC2418's 4-wire interface is SPI and
MICROWIRE compatible. This interface offers several
flexible modes of operation. These include internal/exter-

nal serial clock, 3- or 4-wire I/O, single cycle conversion.
The following sections describe each of these serial inter-
face timing modes in detail. In all these cases, the con-
verter can use the internal oscillator (F

= LOW or F

HIGH) or an external oscillator connected to the F

pin.

Refer to Table 6 for a summary.

External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.

APPLICATIO S I FOR ATIO

Figure 5. External Serial Clock, Single Cycle Operation

EOC

BIT 31

SDO

SCK

(EXTERNAL)

(1)

(0)

SGL

ODD/
SIGN

SDI

DON'T CARE

TEST EOC

PARITY

MSB

SIG

BIT 0

LSB

BIT 6

BIT 27

BIT 26

BIT 25

BIT 24

BIT 28

BIT 29

BIT 30

SLEEP

DATA OUTPUT

CONVERSION

241418 F05

CONVERSION

Hi-Z

TEST EOC

REF

CH0

CH7

CH8

CH15

COM

SCK

SDI

SDO

GND

REFERENCE

VOLTAGE

0.1V TO V

ANALOG

INPUTS

= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION

2.7V TO 5.5V

LTC2414/

LTC2418

4-WIRE
SPI INTERFACE

DON'T CARE

TEST EOC

(OPTIONAL)

LTC2414/LTC2418

241418f

The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.

The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. Independent of CS, the
device automatically enters the low power sleep state once
the conversion is complete.

When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device
remains in the sleep state until the first rising edge of SCK
is seen while CS is LOW. The input data is then shifted in
via the SDI pin on the rising edge of SCK (including the
first rising edge) and the output data is shifted out of the
SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK

and the last bit of the conversion result can be latched on
the 32nd rising edge of SCK. On the 32nd falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.

At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.

Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the 32nd
falling edge of SCK, see Figure 6. On the rising edge of CS,
the device aborts the data output state and immediately
initiates a new conversion. If the device has not finished
loading the last input bit A0 of SDI by the time CS is pulled
HIGH, the address information is discarded and the previ-
ous address is kept. This is useful for systems not requir-
ing all 32 bits of output data, aborting an invalid conversion
cycle or synchronizing the start of a conversion.

Figure 6. External Serial Clock, Reduced Data Output Length

APPLICATIO S I FOR ATIO

(1)

(0)

SGL

ODD/
SIGN

SDI

DON'T CARE

SDO

SCK

(EXTERNAL)

DATA

OUTPUT

CONVERSION

SLEEP

TEST EOC

DATA OUTPUT

Hi-Z

CONVERSION

241418 F06

MSB

SIG

BIT 8

BIT 27

BIT 26

BIT 25

BIT 24

BIT 9

BIT 28

BIT 29

BIT 30

EOC

BIT 31

BIT 0

EOC

Hi-Z

TEST EOC

REF

CH0

CH7

CH8

CH15

COM

SCK

SDI

SDO

GND

REFERENCE

VOLTAGE

0.1V TO V

ANALOG

INPUTS

= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION

2.7V TO 5.5V

LTC2414/

LTC2418

4-WIRE
SPI INTERFACE

TEST EOC

(OPTIONAL)

LTC2414/LTC2418

241418f

Figure 7. External Serial Clock, CS = 0 Operation

External Serial Clock, 3-Wire I/O

This timing mode utilizes a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.

The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
typically 1ms after V

exceeds approximately 2V. The

level applied to SCK at this time determines if SCK is
internal or external. SCK must be driven LOW prior to the
end of POR in order to enter the external serial clock timing
mode.

Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. The input data is then shifted in via the SDI
pin on the rising edge of SCK (including the first rising
edge) and the output data is shifted out of the SDO pin on

each falling edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 32nd falling edge of SCK, SDO
goes HIGH (EOC = 1) indicating a new conversion has
begun.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.

In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.

The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.

APPLICATIO S I FOR ATIO

(1)

(0)

SGL

ODD/
SIGN

SDI

DON'T CARE

EOC

BIT 31

SDO

SCK

(EXTERNAL)

MSB

SIG

BIT 0

PARITY

LSB

BIT 6

BIT 27

BIT 26

BIT 25

BIT 24

BIT 28

BIT 29

BIT 30

DATA OUTPUT

CONVERSION

241418 F07

CONVERSION

REF

CH0

CH7

CH8

CH15

COM

SCK

SDI

SDO

GND

REFERENCE

VOLTAGE

0.1V TO V

ANALOG

INPUTS

= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION

2.7V TO 5.5V

LTC2414/

LTC2418

3-WIRE
SPI INTERFACE

LTC2414/LTC2418

241418f

When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the low power mode during the EOC
test. In order to allow the device to return to the low power
sleep state, CS must be pulled HIGH before the first rising
edge of SCK. In the internal SCK timing mode, SCK goes
HIGH and the device begins outputting data at time t

EOCtest

after the falling edge of CS (if EOC = 0) or t

EOCtest

after EOC

goes LOW (if CS is LOW during the falling edge of EOC).
The value of t

EOCtest

is 23

s if the device is using its internal

oscillator (F

= logic LOW or HIGH). If F

is driven by an

external oscillator of frequency f

EOSC

, then t

EOCtest

3.6/f

EOSC

. If CS is pulled HIGH before time t

EOCtest

, the

device returns to the sleep state and the conversion result
is held in the internal static shift register.

If CS remains LOW longer than t

EOCtest

, the first rising

edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 32nd rising edge. The input data is then shifted in
via the SDI pin on the rising edge of SCK (including the first
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be

used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result on the 32nd rising edge of
SCK. After the 32nd rising edge, SDO goes HIGH (EOC =
1), SCK stays HIGH and a new conversion starts.

Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. If the device has not finished loading the
last input bit A0 of SDI by the time CS is pulled HIGH, the
address information is discarded and the previous ad-
dress is still kept. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.

APPLICATIO S I FOR ATIO

Figure 8. Internal Serial Clock, Single Cycle Operation

(1)

(0)

SGL

ODD/
SIGN

SDI

DON'T CARE

SDO

SCK

(INTERNAL)

MSB

SIG

BIT 0

LSB

PARITY

BIT 6

TEST EOC

BIT 27

BIT 26

BIT 25

BIT 24

BIT 28

BIT 29

BIT 30

EOC

BIT 31

SLEEP

DATA OUTPUT

CONVERSION

241418 F08

EOCtest

Hi-Z

TEST EOC

REF

CH0

CH7

CH8

CH15

COM

SCK

SDI

SDO

GND

REFERENCE

VOLTAGE

0.1V TO V

ANALOG

INPUTS

= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION

2.7V TO 5.5V

LTC2414/

LTC2418

4-WIRE
SPI INTERFACE

10k

LTC2414/LTC2418

241418f

Whenever SCK is LOW, the LTC2414/LTC2418's internal
pull-up at pin SCK is disabled. Normally, SCK is not exter-
nally driven if the device is in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If this driver goes Hi-Z after outputting a LOW
signal, the LTC2414/LTC2418's internal pull-up remains
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK timing
mode. By adding an external 10k pull-up resistor to SCK,
this pin goes HIGH once the external driver goes Hi-Z. On
the next CS falling edge, the device will remain in the in-
ternal SCK timing mode.

A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as t

EOCtest

), the internal pull-up is

activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after

detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.

Internal Serial Clock, 3-Wire I/O,
Continuous Conversion

This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal, see Figure 10. CS may be perma-
nently tied to ground, simplifying the user interface or
isolation barrier.

The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V

exceeds 2V. An internal weak

pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).

During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is

APPLICATIO S I FOR ATIO

Figure 9. Internal Serial Clock, Reduced Data Output Length

(1)

(0)

SGL

ODD/
SIGN

SDI

DON'T CARE

SDO

SCK

(INTERNAL)

> t

EOCtest

MSB

SIG

BIT 8

TEST EOC

(OPTIONAL)

TEST EOC

BIT 27

BIT 26

BIT 25

BIT 24

BIT 28

BIT 29

BIT 30

EOC

BIT 31

EOC

BIT 0

SLEEP

DATA OUTPUT

Hi-Z

DATA

OUTPUT

CONVERSION

SLEEP

2411 F09

EOCtest

10k

TEST EOC

REF

CH0

CH7

CH8

CH15

COM

SCK

SDI

SDO

GND

REFERENCE

VOLTAGE

0.1V TO V

ANALOG

INPUTS

= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION

2.7V TO 5.5V

LTC2414/

LTC2418

4-WIRE
SPI INTERFACE

LTC2414/LTC2418

241418f

complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data input/
output cycle begins on the first rising edge of SCK and
ends after the 32nd rising edge. The input data is then
shifted in via the SDI pin on the rising edge of SCK
(including the first rising edge) and the output data is
shifted out of the SDO pin on each falling edge of SCK.
The internally generated serial clock is output to the SCK
pin. This signal may be used to shift the conversion result
into external circuitry. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1) indicating a
new conversion is in progress. SCK remains HIGH during
the conversion.

PRESERVING THE CONVERTER ACCURACY

The LTC2414/LTC2418 are designed to reduce as much as
possible the conversion result sensitivity to device
decoupling, PCB layout, antialiasing circuits, line fre-

quency perturbations and so on. Nevertheless, in order to
preserve the extreme accuracy capability of this part,
some simple precautions are desirable.

Digital Signal Levels

The LTC2414/LTC2418's digital interface is easy to use.
Its digital inputs (SDI, F

, CS and SCK in External SCK mode

of operation) accept standard TTL/CMOS logic levels and
the internal hysteresis receivers can tolerate edge rates as
slow as 100

s. However, some considerations are required

to take advantage of the exceptional accuracy and low
supply current of this converter.

The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.

While a digital input signal is in the range 0.5V to
(V

0.5V), the CMOS input receiver draws additional

current from the power supply. It should be noted that,
when any one of the digital input signals (SDI, F

, CS and

SCK in External SCK mode of operation) is within this
range, the power supply current may increase even if the
signal in question is at a valid logic level. For micropower

APPLICATIO S I FOR ATIO

Figure 10. Internal Serial Clock, CS = 0 Continuous Operation

(1)

(0)

SGL

ODD/
SIGN

SDI

DON'T CARE

SDO

SCK

(INTERNAL)

LSB

MSB

SIG

BIT 6

BIT 0

PARITY

BIT 27

BIT 26

BIT 25

BIT 24

BIT 28

BIT 29

BIT 30

EOC

BIT 31

DATA OUTPUT

CONVERSION

241418 F10

REF

CH0

CH7

CH8

CH15

COM

SCK

SDI

SDO

GND

REFERENCE

VOLTAGE

0.1V TO V

ANALOG

INPUTS

= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION

2.7V TO 5.5V

LTC2414/

LTC2418

3-WIRE
SPI INTERFACE

LTC2414/LTC2418

241418f

operation, it is recommended to drive all digital input
signals to full CMOS levels [V

< 0.4V and

> (V

0.4V)].

During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the pins
may severely disturb the analog to digital conversion
process. Undershoot and overshoot can occur because of
the impedance mismatch at the converter pin when the
transition time of an external control signal is less than
twice the propagation delay from the driver to LTC2414/
LTC2418. For reference, on a regular FR-4 board, signal
propagation velocity is approximately 183ps/inch for
internal traces and 170ps/inch for surface traces. Thus, a
driver generating a control signal with a minimum transi-
tion time of 1ns must be connected to the converter pin
through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines
are used and multiple reflections may occur. The solution
is to carefully terminate all transmission lines close to
their characteristic impedance.

Parallel termination near the LTC2414/LTC2418 pin will
eliminate this problem but will increase the driver power
dissipation. A series resistor between 27

and 56

placed near the driver or near the LTC2414/LTC2418 pin
will also eliminate this problem without additional power
dissipation. The actual resistor value depends upon the
trace impedance and connection topology.

An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The differential input and refer-
ence architecture reduce substantially the converter's
sensitivity to ground currents.

Particular attention must be given to the connection of the
F

signal when the LTC2414/LTC2418 are used with an

external conversion clock. This clock is active during the
conversion time and the normal mode rejection provided
by the internal digital filter is not very high at this fre-
quency. A normal mode signal of this frequency at the
converter reference terminals may result into DC gain and
INL errors. A normal mode signal of this frequency at the
converter input terminals may result into a DC offset error.

APPLICATIO S I FOR ATIO

Such perturbations may occur due to asymmetric capaci-
tive coupling between the F

signal trace and the converter

input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the F

signal trace and the input/reference sig-

nals. When the F

signal is parallel terminated near the

converter, substantial AC current is flowing in the loop
formed by the F

connection trace, the termination and the

ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the F

signal as well as the loop area for

the differential input and reference connections.

Driving the Input and Reference

The input and reference pins of the LTC2414/LTC2418
converters are directly connected to a network of sampling
capacitors. Depending upon the relation between the
differential input voltage and the differential reference
voltage, these capacitors are switching between these
four pins transferring small amounts of charge in the
process. A simplified equivalent circuit is shown in
Figure 11.

For a simple approximation, the source impedance R

driving an analog input pin (IN

, IN

, REF

or REF

) can be

considered to form, together with R

and C

(see

Figure 11), a first order passive network with a time
constant

= (R

+ R

) · C

. The converter is able to

sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant

. The sampling process on the

four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.

When using the internal oscillator (F

= LOW or HIGH), the

LTC2414/LTC2418's front-end switched-capacitor net-
work is clocked at 76800Hz corresponding to a 13

sampling period. Thus, for settling errors of less than
1ppm, the driving source impedance should be chosen
such that

s/14 = 920ns. When an external oscillator

of frequency f

EOSC

is used, the sampling period is 2/f

EOSC

and, for a settling error of less than 1ppm,

0.14/f

EOSC

LTC2414/LTC2418

241418f

Input Current

If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 11 shows the
mathematical expressions for the average bias currents
flowing through the IN

and IN

pins as a result of the

sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).

The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The C

PAR

capacitor

includes the LTC2414/LTC2418 pin capacitance (5pF typi-
cal) plus the capacitance of the test fixture used to obtain
the results shown in Figures 13 and 14. A careful imple-
mentation can bring the total input capacitance (C

PAR

) closer to 5pF thus achieving better performance

than the one predicted by Figures 13 and 14. For simplic-
ity, two distinct situations can be considered.

For relatively small values of input capacitance (C

0.01

F), the voltage on the sampling capacitor settles

almost completely and relatively large values for the

APPLICATIO S I FOR ATIO

source impedance result in only small errors. Such values
for C

will deteriorate the converter offset and gain

performance without significant benefits of signal filtering
and the user is advised to avoid them. Nevertheless, when
small values of C

are unavoidably present as parasitics

of input multiplexers, wires, connectors or sensors, the
LTC2414/LTC2418 can maintain its exceptional accuracy
while operating with relative large values of source resis-
tance as shown in Figures 13 and 14. These measured
results may be slightly different from the first order
approximation suggested earlier because they include the
effect of the actual second order input network together
with the nonlinear settling process of the input amplifiers.
For small C

values, the settling on IN

and IN

occurs

almost independently and there is little benefit in trying to
match the source impedance for the two pins.

Larger values of input capacitors (C

> 0.01

F) may be

required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When F

= LOW (internal oscillator and 60Hz notch), the

REF

(TYP)

20k

LEAK

(TYP)

20k

18pF
(TYP)

(TYP)

20k

LEAK

REF

2414/18 F11

LEAK

SWITCHING FREQUENCY
f

= 76800Hz INTERNAL OSCILLATOR (F

= LOW OR HIGH)

= 0.5 · f

EOSC

EXTERNAL OSCILLATOR

REF

(TYP)

20k

Figure 11. LTC2414/LTC2418 Equivalent Analog Input Circuit

I IN

I REF

where

AVG

INCM

REFCM

AVG

INCM

REFCM

AVG

REF

INCM

REFCM

REF

AVG

REF

INCM

REFCM

REF

( )

= -

( )

= -

0 5

1 5

0 5

1 5

0 5

:
:

REF

INTERNAL OSCILLATOR

Hz Notch F

LOW

INTERNAL OSCILLATOR

Hz Notch F

HIGH

EXTERNAL OSCILLATOR

REF

REFCM

INCM

EOSC

(

)

(

)

(

)

3 61

4 32

0 555 10

LTC2414/LTC2418

241418f

2414/18 F12

INCM

+ 0.5V

SOURCE

LTC2414/

LTC2418

PAR

20pF

INCM

0.5V

SOURCE

PAR

20pF

SOURCE

(

)

100

10k

100k

+FS ERROR (ppm OF V

REF

)

2414/18 F13

= 5V

REF

= 5V

REF

= GND

= 3.75V

= 1.25V

= GND

= 25

= 0.01

= 0.001

= 100pF

= 0pF

SOURCE

(

)

100

10k

100k

FS ERROR (ppm OF V

REF

)

2414/18 F14

= 5V

REF

= 5V

REF

= GND

= 1.25V

= 3.75V

= GND

= 25

= 0.01

= 0.001

= 100pF

= 0pF

Figure 12. An RC Netwrk at IN

and IN

Figure 13. +FS Error vs R

SOURCE

at IN

or IN

(Small C

)

Figure 14. FS Error vs R

SOURCE

at IN

or IN

(Small C

)

APPLICATIO S I FOR ATIO

typical differential input resistance is 1.8M

which will

generate a gain error of approximately 0.28ppm for each
ohm of source resistance driving IN

or IN

. When F

HIGH (internal oscillator and 50Hz notch), the typical
differential input resistance is 2.16M

which will generate

a gain error of approximately 0.23ppm for each ohm of
source resistance driving IN

or IN

. When F

is driven by

an external oscillator with a frequency f

EOSC

(external

conversion clock operation), the typical differential input
resistance is 0.28 · 10

EOSC

and each ohm of

source resistance driving IN

or IN

will result in

1.78 · 10

· f

EOSC

ppm gain error. The effect of the source

resistance on the two input pins is additive with respect to
this gain error. The typical +FS and FS errors as a function
of the sum of the source resistance seen by IN

and IN

for

large values of C

are shown in Figures 15 and 16.

In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins

and IN

and with the difference between the input and

reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the
converter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large C

capacitor

values, it is advisable to carefully match the source imped-
ance seen by the IN

and IN

pins. When F

= LOW (internal

oscillator and 60Hz notch), every 1

mismatch in source

impedance transforms a full-scale common mode input
signal into a differential mode input signal of 0.28ppm.
When F

= HIGH (internal oscillator and 50Hz notch), every

mismatch in source impedance transforms a full-scale

common mode input signal into a differential mode input
signal of 0.23ppm. When F

is driven by an external

oscillator with a frequency f

EOSC

, every 1

mismatch in

source impedance transforms a full-scale common
mode input signal into a differential mode input signal of

LTC2414/LTC2418

241418f

SOURCE

(

)

0 100 200 300 400 500 600 700 800 900 1000

+FS ERROR (ppm OF V

REF

)

2414/18 F15

300

240

180

120

= 5V

REF

= 5V

REF

= GND

= 3.75V

= 1.25V

= GND

= 25

= 0.01

= 0.1

= 1

F, 10

SOURCE

(

)

0 100 200 300 400 500 600 700 800 900 1000

FS ERROR (ppm OF V

REF

)

2414/18 F16

120

180

240

300

= 5V

REF

= 5V

REF

= GND

= 1.25V

= 3.75V

= GND

= 25

= 0.01

= 0.1

= 1

F, 10

INCM

(V)

0.5

1.5

2.5

3.5

4.5

OFFSET ERROR (ppm OF V

REF

)

2414/18 F17

120

100

120

= GND

= 25

SOURCEIN

= 500

= 10

= 5V

REF

= 5V

REF

= GND

= IN

= V

INCM

= +400

= +200

= +100

= 0

= 100

= 200

= 400

Figure 15. +FS Error vs R

SOURCE

at IN

or IN

(Large C

)

Figure 16. FS Error vs R

SOURCE

at IN

or IN

(Large C

)

Figure 17. Offset Error vs Common Mode Voltage
(V

INCM

= IN

) and Input Source Resistance Imbalance

(

= R

SOURCEIN

+ R

SOURCEIN

) for Large C

Values (C

APPLICATIO S I FOR ATIO

1.78 · 10

· f

EOSC

ppm. Figure 17 shows the typical offset

error due to input common mode voltage for various
values of source resistance imbalance between the IN

and IN

pins when large C

values are used.

If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.

The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/

C) are

used for the external source impedance seen by IN

and

, the expected drift of the dynamic current, offset and

gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.

In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (

10nA max), results

in a small offset shift. A 100

source resistance will create

a 0.1

V typical and 1

V maximum offset voltage.

Reference Current

In a similar fashion, the LTC2414/LTC2418 samples the
differential reference pins REF

and REF

transferring

small amount of charge to and from the external driving
circuits thus producing a dynamic reference current. This
current does not change the converter offset, but it may
degrade the gain and INL performance. The effect of this
current can be analyzed in the same two distinct situa-
tions.

For relatively small values of the external reference capaci-
tors (C

REF

< 0.01

F), the voltage on the sampling capacitor

settles almost completely and relatively large values for
the source impedance result in only small errors. Such

LTC2414/LTC2418

241418f

values for C

REF

will deteriorate the converter offset and

gain performance without significant benefits of reference
filtering and the user is advised to avoid them.

Larger values of reference capacitors (C

REF

> 0.01

F) may

be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance. When F

= LOW

(internal oscillator and 60Hz notch), the typical differential
reference resistance is 1.3M

which will generate a gain

error of approximately 0.38ppm for each ohm of source
resistance driving REF

or REF

. When F

= HIGH (internal

oscillator and 50Hz notch), the typical differential refer-
ence resistance is 1.56M

which will generate a gain error

APPLICATIO S I FOR ATIO

SOURCE

(

)

100

10k

100k

+FS ERROR (ppm OF V

REF

)

2414/18 F18

= 5V

REF

= 5V

REF

= GND

= 3.75V

= 1.25V

= GND

= 25

REF

= 0.01

REF

= 0.001

REF

= 100pF

REF

= 0pF

SOURCE

(

)

100

10k

100k

FS ERROR (ppm OF V

REF

)

2414/18 F19

= 5V

REF

= 5V

REF

= GND

= 1.25V

= 3.75V

= GND

= 25

REF

= 0.01

REF

= 0.001

REF

= 100pF

REF

= 0pF

SOURCE

(

)

0 100 200 300 400 500 600 700 800 900 1000

FS ERROR (ppm OF V

REF

)

2414/18 F20

180

270

360

450

= 5V

REF

= 5V

REF

= GND

= 3.75V

= 1.25V

= GND

= 25

REF

= 0.01

REF

= 0.1

REF

= 1

F, 10

SOURCE

(

)

0 100 200 300 400 500 600 700 800 900 1000

FS ERROR (ppm OF V

REF

)

2414/18 F21

450

360

270

180

= 5V

REF

= 5V

REF

= GND

= 1.25V

= 3.75V

= GND

= 25

REF

= 0.01

REF

= 0.1

REF

= 1

F, 10

Figure 18. +FS Error vs R

SOURCE

at REF

or REF

(Small C

)

Figure 19. FS Error vs R

SOURCE

at REF

or REF

(Small C

)

Figure 20. +FS Error vs R

SOURCE

at REF

and REF

(Large C

REF

)

Figure 21. FS Error vs R

SOURCE

at REF

and REF

(Large C

REF

)

of approximately 0.32ppm for each ohm of source resis-
tance driving REF

or REF

. When F

is driven by an

external oscillator with a frequency f

EOSC

(external conver-

sion clock operation), the typical differential reference
resistance is 0.20 · 10

EOSC

and each ohm of source

resistance driving REF

or REF

will result in

2.47 · 10

· f

EOSC

ppm gain error. The effect of the source

resistance on the two reference pins is additive with
respect to this gain error. The typical +FS and FS errors
for various combinations of source resistance seen by the
REF

and REF

pins and external capacitance C

REF

con-

nected to these pins are shown in Figures 18, 19, 20
and 21.

LTC2414/LTC2418

241418f

In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When F

= LOW (internal oscillator and 60Hz notch), every

100

of source resistance driving REF

or REF

translates

into about 1.34ppm additional INL error. When F

= HIGH

(internal oscillator and 50Hz notch), every 100

of source

resistance driving REF

or REF

translates into about

1.1ppm additional INL error. When F

is driven by an

external oscillator with a frequency f

EOSC

, every 100

source resistance driving REF

or REF

translates into

about 8.73 · 10

· f

EOSC

ppm additional INL error.

Figure 22 shows the typical INL error due to the source
resistance driving the REF

or REF

pins when large C

REF

values are used. The effect of the source resistance on the
two reference pins is additive with respect to this INL error.
In general, matching of source impedance for the REF

and REF

pins does not help the gain or the INL error. The

user is thus advised to minimize the combined source
impedance driving the REF

and REF

pins rather than to

try to match it.

The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by

an external clock. When relatively stable resistors
(50ppm/

C) are used for the external source impedance

seen by REF

and REF

, the expected drift of the dynamic

current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a onetime calibration
operation may be sufficient.

In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(

10nA max), results in a small gain error. A 100

source

resistance will create a 0.05

V typical and 0.5

V maxi-

mum full-scale error.

Output Data Rate

When using its internal oscillator, the LTC2414/LTC2418
can produce up to 7.5 readings per second with a notch
frequency of 60Hz (F

= LOW) and 6.25 readings per

second with a notch frequency of 50Hz (F

= HIGH). The

actual output data rate will depend upon the length of the
sleep and data output phases which are controlled by the
user and which can be made insignificantly short. When
operated with an external conversion clock (F

connected

to an external oscillator), the LTC2414/LTC2418 output
data rate can be increased as desired up to that determined
by the maximum f

EOSC

frequency of 2000kHz. The dura-

tion of the conversion phase is 20510/f

EOSC

. If f

EOSC

153600Hz, the converter behaves as if the internal oscil-
lator is used and the notch is set at 60Hz. There is no
significant difference in the LTC2414/LTC2418 perfor-
mance between these two operation modes.

An increase in f

EOSC

over the nominal 153600Hz will

translate into a proportional increase in the maximum
output data rate. This substantial advantage is neverthe-
less accompanied by three potential effects, which must
be carefully considered.

First, a change in f

EOSC

will result in a proportional change

in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent perfor-
mance degradation can be substantially reduced by rely-
ing upon the LTC2414/LTC2418's exceptional common

APPLICATIO S I FOR ATIO

Figure 22. INL vs Differential Input Voltage (V

= IN

 IN

)

and Reference Source Resistance (R

SOURCE

at REF

and REF

for

Large C

REF

Values (C

REF

INDIF

REFDIF

0.5 0.40.30.20.1 0

0.1 0.2 0.3 0.4 0.5

INL (ppm OF V

REF

)

= 5V

REF+ = 5V
REF = GND
V

INCM

= 0.5 · (IN

+ IN

) = 2.5V

= GND

REF

= 10

= 25

SOURCE

= 1000

SOURCE

= 500

SOURCE

= 100

2414/18 F22

LTC2414/LTC2418

241418f

mode rejection and by carefully eliminating common
mode to differential mode conversion sources in the input
circuit. The user should avoid single-ended input filters
and should maintain a very high degree of matching and
symmetry in the circuits driving the IN

and IN

pins.

Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (C

, C

REF

) are used, the

previous section provides formulae for evaluating the
effect of the source resistance upon the converter perfor-
mance for any value of f

EOSC

. If small external input and/

or reference capacitors (C

, C

REF

) are used, the effect of

the external source resistance upon the LTC2414/LTC2418
typical performance can be inferred from Figures 12, 13,
18 and 19 in which the horizontal axis is scaled by 153600/
f

EOSC

Third, an increase in the frequency of the external oscilla-
tor above 460800Hz (a more than 3

increase in the

output data rate) will start to decrease the effectiveness of
the internal autocalibration circuits. This will result in a
progressive degradation in the converter accuracy and
linearity. Typical measured performance curves for output
data rates up to 100 readings per second are shown in
Figures 23, 24, 25, 26, 27, 28, 29 and 30. In order to obtain
the highest possible level of accuracy from this converter
at output data rates above 20 readings per second, the
user is advised to maximize the power supply voltage used
and to limit the maximum ambient operating temperature.
In certain circumstances, a reduction of the differential
reference voltage may be beneficial.

Input Bandwidth

The combined effect of the internal Sinc

digital filter and

of the analog and digital autocalibration circuits deter-
mines the LTC2414/LTC2418 input bandwidth. When the
internal oscillator is used with the notch set at 60Hz
(F

= LOW), the 3dB input bandwidth is 3.63Hz. When the

internal oscillator is used with the notch set at 50Hz
(F

= HIGH), the 3dB input bandwidth is 3.02Hz. If an

external conversion clock generator of frequency f

EOSC

connected to the F

pin, the 3dB input bandwidth is 0.236

· 10

· f

EOSC

APPLICATIO S I FOR ATIO

OUTPUT DATA RATE (READINGS/SEC)

200

160

120

160

200

OFFSET ERROR (ppm of V

ERROR

)

2414/18 F23

10 20 30 40

50 60 70

80 90 100

= 25

= 85

= 5V

REF

= 5V

= 2.5V

INCM

= 2.5V

SDI = GND
F

= EXTERNAL OSCILLATOR

OUTPUT DATA RATE (READINGS/SEC)

+FS ERROR (ppm of V

REF

)

2000

4000

6000

8000

10000

12000

2414/18 F24

100

30 40

= 25

= 85

= 5V

REF

= 5V

= 2.5V

INCM

= 2.5V

SDI = GND
F

= EXTERNAL OSCILLATOR

OUTPUT DATA RATE (READINGS/SEC)

FS ERROR (ppm of V

REF

)

12000

10000

8000

6000

4000

2000

2414/18 F25

100

30 40

= 25

= 85

= 5V

REF

= 5V

= 2.5V

INCM

= 2.5V

SDI = GND
F

= EXTERNAL OSCILLATOR

Figure 23. Offset Error vs Output Data Rate and Temperature

Figure 24. +FS Error vs Output Data Rate and Temperature

Figure 25. FS Error vs Output Data Rate and Temperature

LTC2414/LTC2418

241418f

Figure 26. Resolution (Noise

RMS

1LSB)

vs Output Data Rate and Temperature

Figure 27. Resolution (INL

RMS

1LSB)

vs Output Data Rate and Temperature

Figure 28. Offset Error vs Output
Data Rate and Reference Voltage

Figure 29. Resolution (Noise

RMS

1LSB) vs

Output Data Rate and Reference Voltage

Figure 30. Resolution (INL

MAX

1LSB) vs

Output Data Rate and Reference Voltage

Figure 31. Input Signal Bandwidth
Using the Internal Oscillator

APPLICATIO S I FOR ATIO

OUTPUT DATA RATE (READINGS/SEC)

10 20 30 40 50 60 70 80 90 100

RESOLUTION (BITS)

2414/18 F26

= 85

= 5V

REF

= 5V

REF

= GND

INCM

= 2.5V

= 0V

SDI = GND
F

= EXTERNAL OSCILLATOR

RESOLUTION = LOG

REF

/NOISE

RMS

)

= 25

OUTPUT DATA RATE (READINGS/SEC)

10 20 30 40 50 60 70 80 90 100

RESOLUTION (BITS)

2414/18 F27

= 85

= 5V

REF

= 5V

REF

= GND

INCM

= 2.5V

2.5V < V

< 2.5V

SDI = GND
F

= EXTERNAL OSCILLATOR

RESOLUTION = LOG

REF

/INL

MAX

)

= 25

OUTPUT DATA RATE (READINGS/SEC)

200

150

100

OFFSET ERROR (ppm of V

REF

)

2414/18 F28

10 20 30 40

50 60 70

80 90 100

REF

= 5V

REF

= 2.5V

= EXTERNAL OSCILLATOR

= 5V

REF

= GND

= 0V

INCM

= 2.5V

SDI = GND
T

= 25

OUTPUT DATA RATE (READINGS/SEC)

10 20 30 40 50 60 70 80 90 100

RESOLUTION (BITS)

2414/18 F29

REF

= 5V

REF

= GND

INCM

= 2.5V

= 0V

SDI = GND
F

= EXTERNAL OSCILLATOR

= 25

RESOLUTION = LOG

REF

/NOISE

RMS

)

REF

= 2.5V

OUTPUT DATA RATE (READINGS/SEC)

10 20 30 40 50 60 70 80 90 100

RESOLUTION (BITS)

2414/18 F30

= 25

= 5V

REF

= GND

INCM

= 0.5 · REF

0.5V · V

REF

< V

< 0.5 · V

REF

SDI = GND
F

= EXTERNAL OSCILLATOR

REF

= 2.5V

REF

= 5V

RESOLUTION =
LOG

REF

/INL

MAX

)

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

0.5

1.5

2.5

3.5

4.5

INPUT SIGNAL ATTENUATION (dB)

2414/18 F31

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

= HIGH

= LOW

Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled very
accurately by a first order filter with the pole located at the
3dB frequency. When the internal oscillator is used, the
shape of the LTC2414/LTC2418 input bandwidth is shown
in Figure 31 for F

= LOW and F

= HIGH. When an external

oscillator of frequency f

EOSC

is used, the shape of the

LTC2414/LTC2418 input bandwidth can be derived from
Figure 31, F

= LOW curve in which the horizontal axis is

scaled by f

EOSC

/153600.

The conversion noise (1

RMS

typical for V

REF

= 5V) can

be modeled by a white noise source connected to a noise

free converter. The noise spectral density is 78nV/

Hz for

an infinite bandwidth source and 107nV/

Hz for a single

0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is a
high gain, low bandwidth amplifier stage followed by a
high bandwidth unity-gain buffer.

LTC2414/LTC2418

241418f

APPLICATIO S I FOR ATIO

When external amplifiers are driving the LTC2414/
LTC2418, the ADC input referred system noise calculation
can be simplified by Figure 32. The noise of an amplifier
driving the LTC2414/LTC2418 input pin can be modeled
as a band limited white noise source. Its bandwidth can be
approximated by the bandwidth of a single pole lowpass
filter with a corner frequency f

. The amplifier noise spec-

tral density is n

. From Figure 32, using f

as the x-axis

selector, we can find on the y-axis the noise equivalent
bandwidth freq

of the input driving amplifier. This band-

width includes the band limiting effects of the ADC internal
calibration and filtering. The noise of the driving amplifier
referred to the converter input and including all these
effects can be calculated as N = n

freq

. The total system

noise (referred to the LTC2414/LTC2418 input) can now
be obtained by summing as square root of sum of squares
the three ADC input referred noise sources: the LTC2414/
LTC2418 internal noise (1

V), the noise of the IN

driving

amplifier and the noise of the IN

driving amplifier.

If the F

pin is driven by an external oscillator of frequency

EOSC

, Figure 32 can still be used for noise calculation if the

x-axis is scaled by f

EOSC

/153600. For large values of the

ratio f

EOSC

/153600, the Figure 32 plot accuracy begins to

decrease, but in the same time the LTC2414/LTC2418
noise floor rises and the noise contribution of the driving
amplifiers lose significance.

Normal Mode Rejection and Antialiasing

One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2414/LTC2418 signifi-
cantly simplify antialiasing filter requirements.

The Sinc

digital filter provides greater than 120dB normal

mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (f

). The

LTC2414/LTC2418's autocalibration circuits further sim-
plify the antialiasing requirements by additional normal
mode signal filtering both in the analog and digital domain.
Independent of the operating mode, f

= 256 · f

= 2048

· f

OUTMAX

where f

in the notch frequency and f

OUTMAX

the maximum output data rate. In the internal oscillator
mode with a 50Hz notch setting, f

= 12800Hz and with a

60Hz notch setting f

= 15360Hz. In the external oscillator

mode, f

= f

EOSC

/10.

Figure 33. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch

Figure 34. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Notch or External Oscillator

Figure 32. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source

INPUT NOISE SOURCE SINGLE POLE

EQUIVALENT BANDWIDTH (Hz)

INPUT REFERRED NOISE

EQUIVALENT BANDWIDTH (Hz)

0.1

100

10k

100k

2414/18 F32

0.1

100

= HIGH

= LOW

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

10f

11f

12f

INPUT NORMAL MODE REJECTION (dB)

2414/18 F33

100

110

120

= HIGH

= LOW OR

= EXTERNAL

OSCILLATOR,

EOSC

= 10 · f

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

INPUT NORMAL MODE REJECTION (dB)

2414/18 F34

100

110

120

10f

LTC2414/LTC2418

241418f

The combined normal mode rejection performance is
shown in Figure 33 for the internal oscillator with 50Hz
notch setting (F

= HIGH) and in Figure 34 for the internal

oscillator with 60Hz notch setting (F

= LOW) and for the

external oscillator mode. The regions of low rejection
occurring at integer multiples of f

have a very narrow

bandwidth. Magnified details of the normal mode rejection
curves are shown in Figure 35 (rejection near DC) and
Figure 36 (rejection at f

= 256f

) where f

represents the

notch frequency. These curves have been derived for the
external oscillator mode but they can be used in all
operating modes by appropriately selecting the f

value.

The user can expect to achieve in practice this level of
performance using the internal oscillator as it is demon-
strated by Figures 37 and 38. Typical measured values of
the normal mode rejection of the LTC2414/LTC2418

operating with an internal oscillator and a 60Hz notch
setting are shown in Figure 37 superimposed over the
theoretical calculated curve. Similarly, typical measured
values of the normal mode rejection of the LTC2414/
LTC2418 operating with an internal oscillator and a 50Hz
notch setting are shown in Figure 38 superimposed over
the theoretical calculated curve.

As a result of these remarkable normal mode specifica-
tions, minimal (if any) antialias filtering is required in front
of the LTC2414/LTC2418. If passive RC components are
placed in front of the LTC2414/LTC2418, the input dy-
namic current should be considered (see Input Current
section). In cases where large effective RC time constants
are used, an external buffer amplifier may be required to
minimize the effects of dynamic input current.

Figure 35. Input Normal Mode Rejection

Figure 36. Input Normal Mode Rejection

Figure 37. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (60Hz Notch)

Figure 38. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (50Hz Notch)

APPLICATIO S I FOR ATIO

INPUT SIGNAL FREQUENCY (Hz)

INPUT NORMAL MODE REJECTION (dB)

2414/18 F35

100

110

120

INPUT SIGNAL FREQUENCY (Hz)

250f

252f

254f

256f

258f

260f

262f

INPUT NORMAL MODE REJECTION (dB)

2414/18 F36

100

110

120

INPUT FREQUENCY (Hz)

105 120 135 150 165 180 195 210 225 240

NORMAL MODE REJECTION (dB)

2414/18 F37

100

120

= 5V

REF

= 5V

REF

= GND

INCM

= 2.5V

IN(P-P)

= 5V

SDI = GND
F

= GND

= 25

MEASURED DATA
CALCULATED DATA

INPUT FREQUENCY (Hz)

12.5

37.5

62.5

87.5 100 112.5 125 137.5 150 162.5 175 187.5 200

NORMAL MODE REJECTION (dB)

2414/18 F38

100

120

= 5V

REF

= 5V

REF

= GND

INCM

= 2.5V

IN(P-P)

= 5V

SDI = GND
F

= 5V

= 25

MEASURED DATA
CALCULATED DATA

LTC2414/LTC2418

241418f

Traditional high order delta-sigma modulators, while
providing very good linearity and resolution, suffer from
potential instabilities at large input signal levels. The pro-
prietary architecture used for the LTC2414/LTC2418 third
order modulator resolves this problem and guarantees a
predictable stable behavior at input signal levels of up to
150% of full scale. In many industrial applications, it is not
uncommon to have to measure microvolt level signals
superimposed over volt level perturbations and LTC2414/
LTC2418 is eminently suited for such tasks. When the
perturbation is differential, the specification of interest is
the normal mode rejection for large input signal levels.
With a reference voltage V

REF

= 5V, the LTC2414/LTC2418

has a full-scale differential input range of 5V peak-to-peak.

Figures 39 and 40 show measurement results for the
LTC2414/LTC2418 normal mode rejection ratio with a 7.5V
peak-to-peak (150% of full scale) input signal superim-
posed over the more traditional normal mode rejection
ratio results obtained with a 5V peak-to-peak (full scale)
input signal. In Figure 39, the LTC2414/LTC2418 uses the
internal oscillator with the notch set at 60Hz (F

= LOW)

and in Figure 40 it uses the internal oscillator with the
notch set at 50Hz (F

= HIGH). It is clear that the LTC2414/

LTC2418 rejection performance is maintained with no com-
promises in this extreme situation. When operating with
large input signal levels, the user must observe that such
signals do not violate the device absolute maximum
ratings.

Figure 39. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (60Hz Notch)

Figure 40. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (50Hz Notch)

INPUT FREQUENCY (Hz)

105 120 135 150 165 180 195 210 225 240

NORMAL MODE REJECTION (dB)

2414/18 F39

100

120

= 5V

REF

= 5V

REF

= GND

INCM

= 2.5V

SDI = GND
F

= GND

= 25

IN(P-P)

= 5V

IN(P-P)

= 7.5V

(150% OF FULL SCALE)

INPUT FREQUENCY (Hz)

NORMAL MODE REJECTION (dB)

2414/18 F40

100

120

= 5V

REF

= 5V

REF

= GND

INCM

= 2.5V

SDI = GND
F

= 5V

= 25

IN(P-P)

= 5V

IN(P-P)

= 7.5V

(150% OF FULL SCALE)

12.5

37.5

62.5

87.5 100 112.5 125 137.5 150 162.5 175 187.5 200

APPLICATIO S I FOR ATIO

LTC2414/LTC2418

241418f

BRIDGE APPLICATIONS

Typical strain gauge based bridges deliver only 2mV/Volt
of excitation. As the maximum reference voltage of the
LTC2414/LTC2418 is 5V, remote sensing of applied exci-
tation without additional circuitry requires that excitation
be limited to 5V. This gives only 10mV full scale input
signal, which can be resolved to 1 part in 10000 without
averaging. For many solid state sensors, this is still better
than the sensor. Averaging 64 samples however reduces
the noise level by a factor of eight, bringing the resolving
power to 1 part in 80000, comparable to better weighing
systems. Hysteresis and creep effects in the load cells are
typically much greater than this. Most applications that
require strain measurements to this level of accuracy are
measuring slowly changing phenomena, hence the time
required to average a large number of readings is usually
not an issue. For those systems that require accurate
measurement of a small incremental change on a signifi-
cant tare weight, the lack of history effects in the LTC2400
family is of great benefit.

For those applications that cannot be fulfilled by the
LTC2414/LTC2418 alone, compensating for error in exter-
nal amplification can be done effectively due to the "no
latency" feature of the LTC2414/LTC2418. No latency
operation allows samples of the amplifier offset and gain
to be interleaved with weighing measurements. The use of
correlated double sampling allows suppression of 1/f
noise, offset and thermocouple effects within the bridge.
Correlated double sampling involves alternating the polar-
ity of excitation and dealing with the reversal of input
polarity mathematically. Alternatively, bridge excitation
can be increased to as much as

10V, if one of several

precision attenuation techniques is used to produce a
precision divide operation on the reference signal. An-
other option is the use of a reference within the 5V input
range of the LTC2414/LTC2418 and developing excitation
via fixed gain, or LTC1043 based voltage multiplication,
along with remote feedback in the excitation amplifiers, as
shown in Figures 46 and 47.

Figure 41 shows an example of a simple bridge connec-
tion. Note that it is suitable for any bridge application
where measurement speed is not of the utmost impor-
tance. For many applications where large vessels are

weighed, the average weight over an extended period of
time is of concern and short term weight is not readily
determined due to movement of contents, or mechanical
resonance. Often, large weighing applications involve load
cells located at each load bearing point, the output of
which can be summed passively prior to the signal pro-
cessing circuitry, actively with amplification prior to the
ADC, or can be digitized via multiple ADC channels and
summed mathematically. The mathematical summation
of the output of multiple LTC2414/LTC2418's provides the
benefit of a root square reduction in noise. The low power
consumption of the LTC2414/LTC2418 makes it attractive
for multidrop communication schemes where the ADC is
located within the load-cell housing.

REF

SDI

SCK

SDO

CH0

CH1

GND

350

BRIDGE

2414/18 F41

LTC2414/

LTC2418

R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS

LT1019

0.1

Figure 41. Simple Bridge Connection

A direct connection to a load cell is perhaps best incorpo-
rated into the load-cell body, as minimizing the distance to
the sensor largely eliminates the need for protection
devices, RFI suppression and wiring. The LTC2414/
LTC2418 exhibits extremely low temperature dependent
drift. As a result, exposure to external ambient tempera-
ture ranges does not compromise performance. The in-
corporation of any amplification considerably compli-
cates thermal stability, as input offset voltages and cur-
rents, temperature coefficient of gain settling resistors all
become factors.

APPLICATIO S I FOR ATIO

LTC2414/LTC2418

241418f

The circuit in Figure 42 shows an example of a simple
amplification scheme. This example produces a differen-
tial output with a common mode voltage of 2.5V, as
determined by the bridge. The use of a true three amplifier
instrumentation amplifier is not necessary, as the LTC2414/
LTC2418 has common mode rejection far beyond that of
most amplifiers. The LTC1051 is a dual autozero amplifier
that can be used to produce a gain of 15 before its input
referred noise dominates the LTC2414/LTC2418 noise.
This example shows a gain of 34, that is determined by a
feedback network built using a resistor array containing 8
individual resistors. The resistors are organized to opti-
mize temperature tracking in the presence of thermal
gradients. The second LTC1051 buffers the low noise
input stage from the transient load steps produced during
conversion.

The gain stability and accuracy of this approach is very
good, due to a statistical improvement in resistor match-
ing. A gain of 34 may seem low, when compared to
common practice in earlier generations of load-cell inter-
faces, however the accuracy of the LTC2414/LTC2418

changes the rationale. Achieving high gain accuracy and
linearity at higher gains may prove difficult, while provid-
ing little benefit in terms of noise reduction.

At a gain of 100, the gain error that could result from
typical open-loop gain of 160dB is 1ppm, however,
worst-case is at the minimum gain of 116dB, giving a gain
error of 158ppm. Worst-case gain error at a gain of 34,
is 54ppm. The use of the LTC1051A reduces the worst-
case gain error to 33ppm. The advantage of gain higher
than 34, then becomes dubious, as the input referred
noise sees little improvement and gain accuracy is poten-
tially compromised.

Note that this 4-amplifier topology has advantages over
the typical integrated 3-amplifier instrumentation ampli-
fier in that it does not have the high noise level common in
the output stage that usually dominates when and instru-
mentation amplifier is used at low gain. If this amplifier is
used at a gain of 10, the gain error is only 10ppm and input
refered noise is reduced to 0.1

RMS

. The buffer stages

can also be configured to provide gain of up to 50 with high
gain stability and linearity.

0.1

REF

SDI

SCK

SD0

CH0

CH1

GND

REF

350

BRIDGE

2414/18 F42

LTC2414/

LTC2418

RN1 = 5k

8 RESISTOR ARRAY

U1A, U1B, U2A, U2B = 1/2 LTC1051

U1A

RN1

U1B

U2A

U2B

Figure 42. Using Autozero Amplifiers to Reduce Input Referred Noise

APPLICATIO S I FOR ATIO

LTC2414/LTC2418

241418f

Figure 43 shows an example of a single amplifier used to
produce single-ended gain. This topology is best used in
applications where the gain setting resistor can be made
to match the temperature coefficient of the strain gauges.
If the bridge is composed of precision resistors, with only
one or two variable elements, the reference arm of the
bridge can be made to act in conjunction with the feedback
resistor to determine the gain. If the feedback resistor is
incorporated into the design of the load cell, using resis-
tors which match the temperature coefficient of the load-
cell elements, good results can be achieved without the
need for resistors with a high degree of absolute accuracy.
The common mode voltage in this case, is again a function
of the bridge output. Differential gain as used with a 350

bridge is A

= (R1+ R2)/(R1+175

). Common mode gain

is half the differential gain. The maximum differential
signal that can be used is 1/4 V

REF

, as opposed to 1/2 V

REF

in the 2-amplifier topology above.

Remote Half Bridge Interface

As opposed to full bridge applications, typical half bridge
applications must contend with nonlinearity in the bridge
output, as signal swing is often much greater. Applications
include RTD's, thermistors and other resistive elements
that undergo significant changes over their span. For
single variable element bridges, the nonlinearity of the half
bridge output can be eliminated completely; if the refer-
ence arm of the bridge is used as the reference to the ADC,
as shown in Figure 44. The LTC2414/LTC2418 can accept
inputs up to 1/2 V

REF

. Hence, the reference resistor R1

must be at least 2x the highest value of the variable
resistor.

In the case of 100

platinum RTD's, this would suggest a

value of 800

for R1. Such a low value for R1 is not

advisable due to self-heating effects. A value of 25.5k is
shown for R1, reducing self-heating effects to acceptable
levels for most sensors.

APPLICATIO S I FOR ATIO

Figure 43. Bridge Amplification Using a Single Amplifier

0.1

REF

CH0

CH1

GND

350

BRIDGE

2410 F49

LTC2414/

LTC2418

LTC1050S8

0.1

46.4k

20k

175

4.99k

(

)

= 9.95 =

R1 + R2

R1 + 175

2410 F50

REF

CH0

CH1

GND

2.7V TO 5.5V

PLATINUM

100

RTD

25.5k

0.1%

LTC2414/

LTC2418

Figure 44. Remote Half Bridge Interface

LTC2414/LTC2418

241418f

The basic circuit shown in Figure 44 shows connections
for a full 4-wire connection to the sensor, which may be
located remotely. The differential input connections will
reject induced or coupled 60Hz interference, however, the
reference inputs do not have the same rejection. If 60Hz or
other noise is present on the reference input, a low pass
filter is recommended as shown in Figure 45. Note that you
cannot place a large capacitor directly at the junction of R1
and R2, as it will store charge from the sampling process.
A better approach is to produce a low pass filter decoupled
from the input lines with a high value resistor (R3).

The use of a third resistor in the half bridge, between the
variable and fixed elements gives essentially the same
result as the two resistor version, but has a few benefits.
If, for example, a 25k reference resistor is used to set the
excitation current with a 100

RTD, the negative refer-

ence input is sampling the same external node as the
positive input and may result in errors if used with a long
cable. For short cable applications, the errors may be
acceptably low. If instead the single 25k resistor is re-
placed with a 10k 5% and a 10k 0.1% reference resistor,
the noise level introduced at the reference, at least at
higher frequencies, will be reduced. A filter can be intro-
duced into the network, in the form of one or more
capacitors, or ferrite beads, as long as the sampling pulses

are not translated into an error. The reference voltage is
also reduced, but this is not undesirable, as it will decrease
the value of the LSB, although, not the input referred noise
level.

The circuit shown in Figure 45 shows a more rigorous
example of Figure 44, with increased noise suppression
and more protection for remote applications.

Figure 46 shows an example of gain in the excitation circuit
and remote feedback from the bridge. The LTC1043's
provide voltage multiplication, providing

10V from a 5V

reference with only 1ppm error. The amplifiers are used at
unity gain and introduce very little error due to gain error
or due to offset voltages. A 1

C offset voltage drift

translates into 0.05ppm/

C gain error. Simpler alterna-

tives, with the amplifiers providing gain using resistor
arrays for feedback, can produce results that are similar to
bridge sensing schemes via attenuators. Note that the
amplifiers must have high open-loop gain or gain error will
be a source of error. The fact that input offset voltage has
relatively little effect on overall error may lead one to use
low performance amplifiers for this application. Note that
the gain of a device such as an LF156, (25V/mV over
temperature) will produce a worst-case error of 180ppm
at a noise gain of 3, such as would be encountered in an
inverting gain of 2, to produce 10V from a 5V reference.

APPLICATIO S I FOR ATIO

Figure 45. Remote Half Bridge Sensing with Noise Suppression on Reference

REF

CH1

GND

2410 F51

LTC2414/

LTC2418

LTC1050

PLATINUM

100

RTD

560

10k

10k, 5%

10k

0.1%

CH0

10k

LTC2414/LTC2418

241418f

350

BRIDGE

0.1

15V

10V

15V

U1
LTC1043

REF

CH0

CH1

GND

2410 F52

LTC2414/

LTC2418

0.1

10V

U2
LTC1043

FILM

U2
LTC1043

10V

LT1236-5

2N3904

0.1

15V

10V

Q2
2N3906

*FLYING CAPACITORS ARE
1

F FILM (MKP OR EQUIVALENT)

SEE LTC1043 DATA SHEET FOR
DETAILS ON UNUSED HALF OF U1

LTC1150

200

0.1

Figure 46. LTC1043 Provides Precise 4X Reference for Excitation Voltages

APPLICATIO S I FOR ATIO

The error associated with the 10V excitation would be
80ppm. Hence, overall reference error could be as high
as 130ppm, the average of the two.

Figure 47 shows a similar scheme to provide excitation
using resistor arrays to produce precise gain. The circuit

is configured to provide 10V and 5V excitation to the
bridge, producing a common mode voltage at the input to
the LTC2414/LTC2418 of 2.5V, maximizing the AC input
range for applications where induced 60Hz could reach
amplitudes up to 2V

RMS

LTC2414/LTC2418

241418f

MULTIPLE CHANNEL USAGE

The LTC2414/LTC2418 have up to sixteen input channels
and this feature provides a very flexible and efficient
solution in applications where more than one variable
need to be measured.

Measurements of a Ladder of Sensors

In industrial process, it is likely that a large group of real
world phenomena need to be monitored where the speed
is not critical. One example is the cracking towers in
petroleum refineries where a group of temperature mea-
surements need to be taken and related. This is done by
passing an excitation current through a ladder of RTDs.
The configuration using a single LTC2418 to monitor up to
eight RTDs in differential mode is shown in Figure 48. A
high accuracy R1 is used to set the excitation current and
the reference voltage. A larger value of 25k is selected to

C1
0.1

15V

REF

CH0

CH1

GND

2410 F53

LTC2414/

LTC2418

LT1236-5

RN1

10k

10V

350

BRIDGE

TWO ELEMENTS

VARYING

RN1
10k

2N3904

1/2

LT1112

C2
0.1

15V

RN1
10k

RN1 IS CADDOCK T914 10K-010-02

Q2, Q3

2N3906

1/2

LT1112

RN1

10k

C3
47

C1
0.1

Figure 47. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier

reduce the self-heating effects. R1 can also be broken into
two resistors, one 25k to set the excitation current and the
other a high accuracy 1k resistor to set the reference
voltage, assuming 100

platinum RTDs. This results in a

reduced reference voltage and a reduced common mode
difference between the reference and the input signal,
which improves the conversion linearity and reduces total
error.

Each input should be taken close to the related RTD to
minimize the error caused by parasitic wire resistance.
The interference on a signal transmission line from RTD to
the LTC2418 is rejected due to the excellent common
mode rejection and the digital LPF included in the LTC2418.
It should be noted that the input source resistance of CHO
can have a maximum value of 800

· 8 = 6.4k, so the

parasitic capacitance and resistance of the connection
wires need to be minimized in order not to degrade the
converter performance.

APPLICATIO S I FOR ATIO

LTC2414/LTC2418

241418f

APPLICATIO S I FOR ATIO

SDI

SCK

SDO

REF

CH0

CH1

CH2

CH3

CH14

CH15

GND

LTC2418

0.1

25k

0.1%

PT2

100

RTD

PT1

100

RTD

PT8

100

RTD

2418 F48

4-WIRE
SPI

Figure 48. Measurement of a Ladder of Sensors Using

Differential Mode

Multichannel Bridge Digitizer and Digital Cold
Junction Compensation

The bridge application as shown in Figures 41, 42, and 43
can be expanded to multiple bridge transducers. Figure 54
shows the expansion for simple bridge measurement.
Also included is the temperature measurement.

In Figure 54, CH0 to CH13 are configured as differential to
measure up to seven bridge transducers using the LTC2418.
CH14 and CH15 are configured as single-ended. CH14
measures the thermocouple while CH15 measures the
output of the cold junction sensor (diode, thermistor,
etc.). The measured cold junction sensor output is then
used to compensate the thermocouple output to find the
absolute temperature. The final temperature value may
then be used to compensate the temperature effects of the
bridge transducers.

Sample Driver for LTC2414/LTC2418 SPI Interface

The LTC2414/LTC2418 have a simple 4-wire serial inter-
face and it is easy to program microprocessors and
microcontrollers to control the device.

Figure 49 shows the 4-wire SPI connection between the
LTC2414/LTC2418 and a PIC16F84 microcontroller. The
sample program for CC5X compiler in Figure 50 can be
used to program the PIC16F84 to control the LTC2414/
LTC2418. It uses PORT B to interface with the device.

The program begins by declaring variables and allocating
four memory locations to store the 32-bit conversion
result. In execution, it first initiates the PORT B to the
proper SPI configuration and prepares channel address.
The LTC2414/LTC2418 is activated by setting the CS low.
Then the microcontroller waits until a logic LOW is de-
tected on the data line, signifying end-of-conversion. After
a LOW is detected, a subroutine is called to exchange data
between the LTC2414/LTC2418 and the microcontroller.
The main loop ends by setting CS high, ending the data
output state.

The performance of the LTC2414/LTC2418 can be verified
using the demonstration board DC434A, see Figure 51 for
the schematic. This circuit uses the computer's serial port
to generate power and the SPI digital signals necessary for
starting a conversion and reading the result. It includes a

SCK

SDI

SDO

PIC16F84

LTC2414/

LTC2418

RB2

RB3

RB4

RB5

2414/18 F49

Figure 49. Connecting the LTC2414/LTC2418 to
a PIC16F84 MCU Using the SPI Serial Interface

LabVIEW

application software program (see Figure 52)

which graphically captures the conversion results. It can
be used to determine noise performance, stability and with
an external source linearity. As exemplified in the sche-
matic, the LTC2414/LTC2418 is extremely easy to use.
This demonstration board and associated software is
available by contacting Linear Technology.

LabVIEW is a trademark of National Instruments Corporation

LTC2414/LTC2418

241418f

// LTC2418 PIC16F84 Interface Example
// Written for CC5X Compiler
// Processor is PIC16F84 running at 10 MHz

#include <16f84.h>
#include <int16cxx.h>
#pragma origin = 0x4
#pragma config |= 0x3fff, WDTE=off,FOSC=HS

// global pin definitions:
#pragma bit rx_pin

@ PORTB.0

//input

#pragma bit tx_pin

@ PORTB.1

//output

#pragma bit sck

@ PORTB.2

//output

#pragma bit sdi

@ PORTB.3

//output

#pragma bit sdo

@ PORTB.4

//input

#pragma bit cs_bar

@ PORTB.5

//output

// Global Variables
uns8 result_3;

// Conversion result MS byte

uns8 result_2;

// ..

uns8 result_1;

// ..

uns8 result_0;

// Conversion result LS byte

void shiftbidir(char nextch);

// function prototype

void main( void)

{

INTCON=0b00000000;

// no interrupts

TRISA=0b00000000;

// all PORTA pins outputs

TRISB=0b00010001;

// according to definitions above

char channel;

// next channel to send

while(1)
{

/* channel bit fields are 7:6, 10 always; 5, EN; 4, SGL; 3, ODD/SIGN; 2:0, ADDR */

channel = 0b10101000;

// CH0,1 DIFF.

cs_bar=0;

// activate ADC

while(sdo==1)

// test for end of conversion

{

// wait if conversion is not complete

}

shiftbidir(channel);

// read ADC, send next channel

cs_bar = 1;

// deactivate ADC

/* At this point global variables result 3,2,1 contain the 24 bit conversion result. Variable result3
contains the corresponding channel information in the following fields:

bits 7:6, 00 always, 5, EN; 4, SGL; 3, ODD/SIGN; 2:0, ADDR */

}

// end of loop

}

// end of main

Figure 50. Sample Program in CC5X for PIC16F84

APPLICATIO S I FOR ATIO

LTC2414/LTC2418

241418f

////////// Bidirectional Shift Routine for ADC //////////

void shiftbidir(char nextch)

{

int i;
for(i=0;i<2;i++)

// send config bits 7:6,

// ignore EOC/ and DMY bits

{

sdi=nextch.7;

// put data on pin

nextch = rl(nextch);

// get next config bit ready

sck=1;

// clock high

sck=0;

// clock low

}

for(i=0;i<8;i++)

// send config, read byte 3

{

sdi=nextch.7;

// put data on pin

nextch = rl(nextch);

// get next config bit ready

result_3 = rl(result_3);// get ready to load lsb
result_3.0 = sdo;

// load lsb

sck=1;

// clock high

sck=0;

// clock low

}

for(i=0;i<8;i++)

// read byte 2

{

result_2 = rl(result_2);// get ready to load lsb
result_2.0 = sdo;

// load lsb

sck=1;

// clock high

sck=0;

// clock low

}

for(i=0;i<8;i++)

// read byte 1

{

result_1 = rl(result_1);// get ready to load lsb
result_1.0 = sdo;

// load lsb

sck=1;

// clock high

sck=0;

// clock low

}

result_0=0;

// ensure bits 7:6 are zero

for(i=0;i<6;i++)

// read byte 0

{

result_0 = rl(result_0);// get ready to load lsb
result_0.0 = sdo;

// load lsb

sck=1;

// clock high

sck=0;

// clock low

}

Figure 50. Sample Program in CC5X for PIC16F84 (cont)

APPLICATIO S I FOR ATIO

LTC2414/LTC2418

241418f

Figure 51. Demo Board Schematic

1
3
5
7
9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

11
12
21
22
23
24
25
26
27
28

1
2
3
4
5
6
7
8

13
14
15

19
18
17
16
20

LTC2418CGN

COM

REF+
REF
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15

SCK

SDO

SDI

NC
NC

GND

10
11
12
13
14

3
4
5
6
2

9
7
8

JP6
JMPR

1
6
2
7
3
8
4
9
5

DB9

SER
A
B
C
D
E
F
G
H
CLK
INH
SH/LD

QH
QH

GND

C5
10

35V

JP5
JMPR

C6
0.1

C7
0.1

C8
0.1

GND

REF

VEX

50Hz/60Hz

BANANA

JACK

CON40A

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

74HC165

Q1
MMBT3904LT1

R7
22k

R8
51k

51k

R5
49.9

2.5V

OUT

GND

LT1460ACN8-2.5

OUT

GND

LT1236ACN8-5

JP3

JMPR

2.5V

JP1

JMPR

JP4

JMPR

JP2

JMPR

GND

REMOVE TO

DISCONNECT

AND

5V REF

C2
22

25V

35V

C4
100

16V

35V

R2
3

U3C

74HC14

U3D

74HC14

U3B

74HC14

U3A

74HC14

U3E

74HC14

U3F

74HC14

BYPASS

CAPACITOR

FOR U3 AND U4

EXT

2414/18 F51

BAV74LT1

APPLICATIO S I FOR ATIO

LTC2414/LTC2418

241418f

PACKAGE DESCRIPTIO

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

0.386 0.393*

(9.804 9.982)

GN28 (SSOP) 1098

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

9 10 11 12

0.229 0.244

(5.817 6.198)

0.150 0.157**

(3.810 3.988)

19 18 17

13 14

1615

0.016 0.050

(0.406 1.270)

0.015

0.004

(0.38

0.10)

TYP

0.0075 0.0098

(0.191 0.249)

0.053 0.069

(1.351 1.748)

0.008 0.012

(0.203 0.305)

0.004 0.009

(0.102 0.249)

0.0250

(0.635)

BSC

0.033

(0.838)

REF

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC2414/LTC2418

241418f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear.com

LINEAR TECHNOLOGY CORPORATION 2002

LT/TP 1002 2K · PRINTED IN USA

PART NUMBER

DESCRIPTION

COMMENTS

LT1019

Precision Bandgap Reference, 2.5V, 5V

3ppm/

C Drift, 0.05% Max Initial Accuracy

LT1025

Micropower Thermocouple Cold Junction Compensator

A Supply Current, 0.5

C Initial Accuracy

LTC1050

Precision Chopper Stabilized Op Amp

No External Components 5

V Offset, 1.6

P-P

Noise

LT1236A-5

Precision Bandgap Reference, 5V

0.05% Max Initial Accuracy, 5ppm/

C Drift

LT1460

Micropower Series Reference

0.075% Max Initial Accuracy, 10ppm/

C Max Drift

LTC2400

24-Bit, No Latency

ADC in SO-8

0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200

LTC2401/LTC2402

1-/2-Channel, 24-Bit, No Latency

ADC in MSOP

0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200

LTC2404/LTC2408

4-/8-Channel, 24-Bit, No Latency

ADC

0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200

LTC2410

24-Bit, Fully Differential, No Latency

ADC

0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200

LTC2411

24-Bit, Fully Differential, No Latency

ADC in MSOP

0.3ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200

LTC2411-1

24-Bit, Simultaneous 50Hz/60Hz Rejection

ADC

0.3ppm Noise, 2ppm INL, Pin Compatible with LTC2411

LTC2413

24-Bit, Fully Differential, No Latency

ADC

Simultaneous 50Hz and 60Hz Rejection, 800nV

RMS

Noise

LTC2415/LTC2415-1

24-Bit, No Latency

ADC with 15Hz Output Rate

Pin Compatible with the LTC2410/LTC2413

LTC2420

20-Bit, No Latency

ADC in SO-8

1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400

LTC2424/LTC2428

4-/8-Channel, 20-Bit, No Latency

ADC

1.2ppm Noise, Pin Compatible with LTC2404/LTC2408

RELATED PARTS

TYPICAL APPLICATIO

Figure 54. Multichannel Bridge Digitizer and Digital Cold Junction Compensation

GND

LTC2418

0.1

2418 F54

SDI

SCK

SDO

REF

CH0

CH1

CH2

CH3

CH14

CH15

COM

THERMISTOR

THERMOCOUPLE

LTC2418

GND

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC2414IGN