1
LTC2420
20-Bit
Power
No Latency
TM
ADC in SO-8
January 2000
s
Weight Scales
s
Direct Temperature Measurement
s
Gas Analyzers
s
Strain-Gage Transducers
s
Instrumentation
s
Data Acquisition
s
Industrial Process Control
s
4-Digit DVMs
No Latency
is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
Total Unadjusted Error vs Output Code
, LTC and LT are registered trademarks of Linear Technology Corporation.
s
20-Bit ADC in SO-8 Package
s
8ppm INL, No Missing Codes at 20 Bits
s
4ppm Full-Scale Error
s
0.5ppm Offset
s
1.2ppm Noise
s
Digital Filter Settles in a Single Cycle. Each
Conversion Is Accurate, Even After an Input Step.
s
Internal Oscillator--No External Components
Required
s
Fast Mode: 16-Bit Noise, 12 Bits TUE at 100sps
s
110dB Min, 50Hz/60Hz Notch Filter
s
Reference Input Voltage: 0.1V to V
CC
s
Live Zero--Extended Input Range Accommodates
12.5% Overrange and Underrange
s
Single Supply 2.7V to 5.5V Operation
s
Low Supply Current (200
A) and Auto Shutdown
s
Pin Compatible with 24-Bit LTC2400
The LTC
2420 is a micropower 20-bit A/D converter with
an integrated oscillator, 8ppm INL and 1.2ppm RMS
noise that operates from 2.7V to 5.5V. It uses delta-sigma
technology and provides a digital filter that settles in a
single cycle for multiplexed applications. Through a single
pin, the LTC2420 can be configured for better than 110dB
rejection at 50Hz or 60Hz
2%, or it can be driven by an
external oscillator for a user-defined rejection frequency
in the range 1Hz to 800Hz. The internal oscillator requires
no external frequency setting components.
The converter accepts any external reference voltage from
0.1V to V
CC
. With its extended input conversion range of
12.5% V
REF
to 112.5% V
REF
, the LTC2420 smoothly
resolves the offset and overrange problems of preceding
sensors or signal conditioning circuits.
The LTC2420 communicates through a flexible 3-wire
digital interface which is compatible with SPI and
MICROWIRE
TM
protocols.
V
CC
F
O
V
REF
SCK
V
IN
SDO
1
2
3
4
8
7
6
5
GND
CS
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT RANGE
0.12V
REF
TO 1.12V
REF
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
3-WIRE
SPI INTERFACE
1
F
2.7V TO 5.5V
LTC2420
2420 TA01
V
CC
OUTPUT CODE (DECIMAL)
0
524,288
1,048,575
TOTAL UNADJUSTED ERROR (ppm)
2420 TA02
10
8
6
4
2
0
2
4
6
8
10
V
CC
= 5V
V
REF
= 5V
T
A
= 25
C
F
O
= LOW
DESCRIPTIO
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FEATURES
APPLICATIO S
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TYPICAL APPLICATIO
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Final Electrical Specifications
2
LTC2420
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
0.1V
V
REF
V
CC
, (Note 5)
q
20
Bits
Integral Nonlinearity
V
REF
= 2.5V (Note 6)
q
4
10
ppm of V
REF
V
REF
= 5V (Note 6)
q
8
20
ppm of V
REF
Integral Nonlinearity (Fast Mode)
V
REF
= 5V, V
REF
= 2.5V, 100 Samples/Second, f
O
= 2.048MHz
q
40
250
ppm of V
REF
Offset Error
2.5V
V
REF
V
CC
q
0.5
10
ppm of V
REF
Offset Error (Fast Mode)
2.5V < V
REF
< 5V, 100 Samples/Second, f
O
= 2.048MHz
3
ppm of V
REF
Offset Error Drift
2.5V
V
REF
V
CC
0.04
ppm of V
REF
/
C
Full-Scale Error
2.5V
V
REF
V
CC
q
4
10
ppm of V
REF
Full-Scale Error (Fast Mode)
2.5V < V
REF
< 5V, 100 Samples/Second, f
O
= 2.048MHz
10
ppm of V
REF
Full-Scale Error Drift
2.5V
V
REF
V
CC
0.04
ppm of V
REF
/
C
Total Unadjusted Error
V
REF
= 2.5V
8
ppm of V
REF
V
REF
= 5V
16
ppm of V
REF
Output Noise
V
IN
= 0V (Note 13)
6
V
RMS
Output Noise (Fast Mode)
V
REF
= 5V, 100 Samples/Second, f
O
= 2.048MHz
20
V
RMS
Normal Mode Rejection 60Hz
2%
(Note 7)
q
110
130
dB
Normal Mode Rejection 50Hz
2%
(Note 8)
q
110
130
dB
Power Supply Rejection, DC
V
REF
= 2.5V, V
IN
= 0V
100
dB
Power Supply Rejection, 60Hz
2%
V
REF
= 2.5V, V
IN
= 0V, (Note 7)
110
dB
Power Supply Rejection, 50Hz
2%
V
REF
= 2.5V, V
IN
= 0V, (Note 8)
110
dB
ORDER PART NUMBER
Consult factory for Military grade parts.
S8 PART MARKING
(Notes 1, 2)
Supply Voltage (V
CC
) to GND ....................... 0.3V to 7V
Analog Input Voltage to GND ....... 0.3V to (V
CC
+ 0.3V)
Reference Input Voltage to GND .. 0.3V to (V
CC
+ 0.3V)
Digital Input Voltage to GND ........ 0.3V to (V
CC
+ 0.3V)
Digital Output Voltage to GND ..... 0.3V to (V
CC
+ 0.3V)
Operating Temperature Range
LTC2420C ............................................... 0
C to 70
C
LTC2420I ............................................ 40
C to 85
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec).................. 300
C
T
JMAX
= 125
C,
JA
= 130
C/W
LTC2420CS8
LTC2420IS8
2420
2420I
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. (Notes 3, 4)
ABSOLUTE
M
AXI
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RATINGS
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FOR
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VERTER CHARACTERISTICS
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1
2
3
4
8
7
6
5
TOP VIEW
F
O
SCK
SDO
CS
V
CC
V
REF
V
IN
GND
S8 PACKAGE
8-LEAD PLASTIC SO
3
LTC2420
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
2.7V
V
CC
5.5V
q
2.5
V
CS, F
O
2.7V
V
CC
3.3V
2.0
V
V
IL
Low Level Input Voltage
4.5V
V
CC
5.5V
q
0.8
V
CS, F
O
2.7V
V
CC
5.5V
0.6
V
V
IH
High Level Input Voltage
2.7V
V
CC
5.5V (Note 9)
q
2.5
V
SCK
2.7V
V
CC
3.3V (Note 9)
2.0
V
V
IL
Low Level Input Voltage
4.5V
V
CC
5.5V (Note 9)
q
0.8
V
SCK
2.7V
V
CC
5.5V (Note 9)
0.6
V
I
IN
Digital Input Current
0V
V
IN
V
CC
q
10
10
A
CS, F
O
I
IN
Digital Input Current
0V
V
IN
V
CC
(Note 9)
q
10
10
A
SCK
C
IN
Digital Input Capacitance
10
pF
CS, F
O
C
IN
Digital Input Capacitance
(Note 9)
10
pF
SCK
V
OH
High Level Output Voltage
I
O
= 800
A
q
V
CC
0.5
V
SDO
V
OL
Low Level Output Voltage
I
O
= 1.6mA
q
0.4
V
SDO
V
OH
High Level Output Voltage
I
O
= 800
A (Note 10)
q
V
CC
0.5
V
SCK
V
OL
Low Level Output Voltage
I
O
= 1.6mA (Note 10)
q
0.4
V
SCK
I
OZ
High-Z Output Leakage
q
10
10
A
SDO
DIGITAL I PUTS A D DIGITAL OUTPUTS
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SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
Supply Voltage
q
2.7
5.5
V
I
CC
Supply Current
Conversion Mode
CS = 0V (Note 12)
q
200
300
A
Sleep Mode
CS = V
CC
(Note 12)
q
20
30
A
POWER REQUIRE E TS
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The
q
denotes specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25
C. (Note 3)
The
q
denotes specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
Input Voltage Range
(Note 14)
q
0.125 V
REF
1.125 V
REF
V
V
REF
Reference Voltage Range
q
0.1
V
CC
V
C
S(IN)
Input Sampling Capacitance
1
pF
C
S(REF)
Reference Sampling Capacitance
1.5
pF
I
IN(LEAK)
Input Leakage Current
CS = V
CC
q
100
1
100
nA
I
REF(LEAK)
Reference Leakage Current
V
REF
= 2.5V, CS = V
CC
q
100
1
100
nA
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. (Note 3)
A ALOG I PUT A D REFERE CE
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LTC2420
The
q
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
C. (Note 3)
f
EOSC
External Oscillator Frequency Range
20-Bit Effective Resolution
q
2.56
307.2
kHz
12-Bit Effective Resolution
q
2.56
2.048
MHz
t
HEO
External Oscillator High Period
q
0.5
390
s
t
LEO
External Oscillator Low Period
q
0.5
390
s
t
CONV
Conversion Time
F
O
= 0V
q
130.66
133.33
136
ms
F
O
= V
CC
q
156.80
160
163.20
ms
External Oscillator (Note 11)
q
20480/f
EOSC
(in kHz)
ms
f
ISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
19.2
kHz
External Oscillator (Notes 10, 11)
f
EOSC
/8
kHz
D
ISCK
Internal SCK Duty Cycle
(Note 10)
45
55
%
f
ESCK
External SCK Frequency Range
(Note 9)
q
2000
kHz
t
LESCK
External SCK Low Period
(Note 9)
q
250
ns
t
HESCK
External SCK High Period
(Note 9)
q
250
ns
t
DOUT_ISCK
Internal SCK 24-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
q
1.23
1.25
1.28
ms
External Oscillator (Notes 10, 11)
q
192/f
EOSC
(in kHz)
ms
t
DOUT_ESCK
External SCK 24-Bit Data Output Time
(Note 9)
q
24/f
ESCK
(in kHz)
ms
t
1
CS
to SDO Low Z
q
0
150
ns
t2
CS
to SDO High Z
q
0
150
ns
t3
CS
to SCK
(Note 10)
q
0
150
ns
t4
CS
to SCK
(Note 9)
q
50
ns
t
KQMAX
SCK
to SDO Valid
q
200
ns
t
KQMIN
SDO Hold After SCK
(Note 5)
q
15
ns
t
5
SCK Set-Up Before CS
q
50
ns
t
6
SCK Hold After CS
q
50
ns
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: All voltages are with respect to GND. V
CC
= 2.7 to 5.5V unless
otherwise specified. R
SOURCE
= 0
.
Note 4: Internal Conversion Clock source with the F
O
pin tied
to GND or to V
CC
or to external conversion clock source with
f
EOSC
= 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: F
O
= 0V (internal oscillator) or f
EOSC
= 153600Hz
2%
(external oscillator).
Note 8: F
O
= V
CC
(internal oscillator) or f
EOSC
= 128000Hz
2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is f
ESCK
and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance C
LOAD
= 20pF.
Note 11: The external oscillator is connected to the F
O
pin. The external
oscillator frequency, f
EOSC
, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
F
O
= 0V or F
O
= V
CC
.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: For reference voltage values V
REF
> 2.5V the extended input
of 0.125 V
REF
to 1.125 V
REF
is limited by the absolute maximum
rating of the Analog Input Voltage pin (Pin 3). For 2.5V < V
REF
0.267V + 0.89 V
CC
the input voltage range is 0.3V to 1.125 V
REF
.
For 0.267V + 0.89 V
CC
< V
REF
V
CC
the input voltage range is 0.3V
to V
CC
+ 0.3V.
TI I G CHARACTERISTICS
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LTC2420
V
CC
(Pin 1): Positive Supply Voltage. Bypass to GND
(Pin 4) with a 10
F tantalum capacitor in parallel with
0.1
F ceramic capacitor as close to the part as possible.
V
REF
(Pin 2): Reference Input. The reference voltage range
is 0.1V to V
CC
.
V
IN
(Pin 3): Analog Input. The input voltage range is
0.125 V
REF
to 1.125 V
REF
. For V
REF
> 2.5V the input
voltage range may be limited by the pin absolute maxi-
mum rating of 0.3V to V
CC
+ 0.3V.
GND (Pin 4): Ground. Shared pin for analog ground,
digital ground, reference ground and signal ground. Should
be connected directly to a ground plane through a mini-
mum length trace or it should be the single-point-ground
in a single point grounding system.
CS (Pin 5): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW on CS wakes up the ADC. A
LOW-to-HIGH transition on this pin disables the SDO
digital output. A LOW-to-HIGH transition on CS during the
Data Output transfer aborts the data transfer and starts a
new conversion.
SDO (Pin 6): Three-State Digital Output. During the data
output period this pin is used for serial data output. When
the chip select CS is HIGH (CS = V
CC
), the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin can be used as a conversion status out-
put. The conversion status can be observed by pulling CS
LOW.
SCK (Pin 7): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the data output
period. In External Serial Clock Operation mode, SCK is
used as digital input for the external serial interface. A
weak internal pull-up is automatically activated in Internal
Serial Clock Operation mode. The Serial Clock mode is
determined by the level applied to SCK at power up and the
falling edge of CS.
F
O
(Pin 8): Frequency Control Pin. Digital input that
controls the ADC's notch frequencies and conversion
time. When the F
O
pin is connected to V
CC
(F
O
= V
CC
), the
converter uses its internal oscillator and the digital filter's
first null is located at 50Hz. When the F
O
pin is connected
to GND (F
O
= OV) the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When F
O
is driven by an external clock signal with a frequency f
EOSC
,
the converter uses this signal as its clock and the digital
filter first null is located at a frequency f
EOSC
/2560.
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APPLICATIO S I FOR ATIO
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The LTC2420 is pin compatible with the LTC2400. The two
devices are designed to allow the user to incorporate
either device in the same design with no modifications.
While the LTC2420 output word length is 24 bits (as
opposed to the 32-bit output of the LTC2400), its output
clock timing can be identical to the LTC2400. As shown in
Figure 1, the LTC2420 data output is concluded on the
falling edge of the 24th serial clock (SCK). In order to
maintain drop-in compatibility with the LTC2400, it is
possible to clock the LTC2420 with an additional 8 serial
clock pulses. This results in 8 additional output bits which
are always logic HIGH.
Output Data Format
The LTC2420 serial output data stream is 24 bits long. The
first 4 bits represent status information indicating the
sign, input range and conversion state. The next 20 bits are
the conversion result, MSB first.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
6
LTC2420
APPLICATIO S I FOR ATIO
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CS
SCK
SDO
CONVERSION
SLEEP
8
8
8
8 (OPTIONAL)
EOC = 1
EOC = 1
LAST 8 BITS ALWAYS 1
EOC = 0
DATA OUT
4 STATUS BITS 20 DATA BITS
DATA OUTPUT
2420 F01
CONVERSION
Figure 1. LTC2420 Compatible Timing with the LTC2400
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW. The sign bit changes state during the zero code.
Bit 20 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0
V
IN
V
REF
, this bit is LOW. If the input is outside the
normal input range, V
IN
> V
REF
or V
IN
< 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Table 1. LTC2420 Status Bits
Bit 23
Bit 22
Bit 21
Bit 20
Input Range
EOC
DMY
SIG
EXR
V
IN
> V
REF
0
0
1
1
0 < V
IN
V
REF
0
0
1
0
V
IN
= 0
+
/0
0
0
1/0
0
V
IN
< 0
0
0
0
1
Bit 19 (fifth output bit) is the most significant bit (MSB).
Bits 19-0 are the 20-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 2. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 23 (EOC) can be captured on the first rising
edge of SCK. Bit 22 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 23rd SCK and may be latched on
the rising edge of the 24th SCK pulse. On the falling edge
of the 24th SCK pulse, SDO goes HIGH indicating a new
conversion cycle has been initiated. This bit serves as EOC
(Bit 23) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the V
IN
pin is maintained within
the 0.3V to (V
CC
+ 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from 0.125 V
REF
to 1.125 V
REF
.
For input voltages
greater than 1.125 V
REF
, the conversion result is clamped
to the value corresponding to 1.125 V
REF
. For input
voltages below 0.125 V
REF
, the conversion result is
clamped to the value corresponding to 0.125 V
REF
.
Operation at Higher Data Output Rates
The LTC2420 typically operates with an internal oscillator
of 153.6kHz. This corresponds to a notch frequency of
60Hz and an output rate of 7.5 samples/second. The
internal oscillator is enabled if the F
O
pin is logic LOW
(logic HIGH for a 50Hz notch). It is possible to drive the F
O
pin with an external oscillator for higher data output rates.
As shown in Figure 3, an external clock of 2.048MHz
applied to the F
O
pin results in a notch frequency of 800Hz
with a data output rate of 100 samples/second.
Figure 4 shows the total unadjusted error (Offset Error +
Full-Scale Error + INL + DNL) as a function of the output
data rate with a 5V reference. The relationship between the
7
LTC2420
APPLICATIO S I FOR ATIO
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Figure 2. Output Data Timing
Table 2. LTC2420 Output Data Format
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
...
Bit 0
Input Voltage
EOC
DMY
SIG
EXR
MSB
LSB
V
IN
> 9/8 V
REF
0
0
1
1
0
0
0
1
1
...
1
9/8 V
REF
0
0
1
1
0
0
0
1
1
...
1
V
REF
+ 1LSB
0
0
1
1
0
0
0
0
0
...
0
V
REF
0
0
1
0
1
1
1
1
1
...
1
3/4V
REF
+ 1LSB
0
0
1
0
1
1
0
0
0
...
0
3/4V
REF
0
0
1
0
1
0
1
1
1
...
1
1/2V
REF
+ 1LSB
0
0
1
0
1
0
0
0
0
...
0
1/2V
REF
0
0
1
0
0
1
1
1
1
...
1
1/4V
REF
+ 1LSB
0
0
1
0
0
1
0
0
0
...
0
1/4V
REF
0
0
1
0
0
0
1
1
1
...
1
0
+
/0
0
0
1/0*
0
0
0
0
0
0
...
0
1LSB
0
0
0
1
1
1
1
1
1
...
1
1/8 V
REF
0
0
0
1
1
1
1
0
0
...
0
V
IN
< 1/8 V
REF
0
0
0
1
1
1
1
0
0
...
0
*The sign bit changes state during the 0 code.
MSB
EXT
SIG
"0"
1
2
3
4
5
19
20
24
BIT 0
BIT 19
BIT 4
LSB
20
BIT 20
BIT 21
BIT 22
SDO
SCK
CS
EOC
BIT 23
SLEEP
DATA OUTPUT
CONVERSION
2420 F02
Hi-Z
Figure 3. Selectable 100 Samples/Second Turbo Mode
Figure 4. Total Error vs Output Rate (V
REF
= 5V)
F
O
SCK
SDO
CS
V
CC
V
REF
V
IN
GND
8
7
6
5
1
2
3
4
LTC2420
800Hz NOTCH (100 SAMPLES/SECOND)
60Hz NOTCH (7.5 SAMPLES/SECOND)
EXTERNAL 2.048MHz CLOCK SOURCE
INTERNAL 153.6kHz OSCILLATOR
2420 F03
OUTPUT RATE (SAMPLES/SEC)
0
TOTAL UNADJUSTED ERROR (ppm)
96
128
160
12 BITS
13 BITS
14 BITS
16 BITS
2420 F04
64
32
0
50
100
192
224
256
V
REF
= 5V
150
8
LTC2420
APPLICATIO S I FOR ATIO
W
U
U
U
output data rate (ODR) and the frequency applied to the F
O
pin (F
O
) is:
ODR = F
O
/20480
For output data rates up to 50 samples/second, the total
unadjusted error (TUE) is better than 16 bits, and better
than 12 bits at 100 samples/second. As shown in Figure 5,
for output data rates of 100 samples/second, the TUE is
better than 15 bits for V
REF
below 2.5V. Figure 6 shows an
unaveraged total unadjusted error for the LTC2420 oper-
ating at 100 samples/second with V
REF
= 2.5V. Figure 7
shows the same device operating with a 5V reference and
an output data rate of 7.5 samples/second.
Figure 6. Total Unadjusted Error at
100 Samples/Second (No Averaging)
Figure 7. Total Unadjusted Error at 7.5 Samples/Second
(No Averaging)
Figure 5. Total Error vs V
REF
(Output Rate = 100sps)
REFERENCE VOLTAGE (V)
1.0
TOTAL UNADJUSTED ERROR (ppm)
128
192
5.0
2420 F05
64
0
2.0
3.0
4.0
1.5
2.5
3.5
4.5
256
96
160
32
224
OUTPUT RATE = 100sps
12 BITS
13 BITS
14 BITS
15 BITS
INPUT VOLTAGE (V)
0
40
TOTAL UNADJUSTED ERROR (ppm)
30
25
20
15
10
5
2420 F06
0
5
10
35
2.5
V
CC
= 5V
V
REF
= 2.5V
INPUT VOLTAGE (V)
0
TOTAL UNADJUSTED ERROR (ppm)
2
0
2
5
2420 F07
4
6
10
8
6
4
V
CC
= 5V
V
REF
= 5V
At 100 samples/second, the LTC2420 can be used to
capture transient data. This is useful for monitoring set-
tling or auto gain ranging in a system. The LTC2420 can
monitor signals at an output rate of 100 samples/second.
After acquiring 100 samples/second data the F
O
pin may
be driven LOW enabling 60Hz rejection to 110dB and the
highest possible DC accuracy. The no latency architecture
of the LTC2420 allows consecutive readings (one at 100
samples/second the next at 7.5 samples/second) without
interaction between the two readings.
9
LTC2420
APPLICATIO S I FOR ATIO
W
U
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U
8a. Digitized Waveform
8b. Output FFT
Figure 8. Transient Signal Acquisiton
9a. Digitized Waveform with 2V DC Offset
9b. FFT Waveform with 2V DC Offset
As shown in Figure 8, the LTC2420 can capture transient
data with 90dB of dynamic range (with a 300mV
P-P
input
signal at 2Hz). The exceptional DC performance of the
LTC2420 enables signals to be digitized independent of a
TIME
ADC OUTPUT (NORMALIZED TO VOLTS)
0
0.05
0.10
2420 F08a
0.05
0.10
0.20
0.15
0.20
500ms
0.15
f
IN
= 2Hz
FREQUENCY (Hz)
MAGNITUDE (dB)
60
40
20
0
80
100
120
2Hz
100sps
0V OFFSET
2420 F08b
TIME
ADC OUTPUT (NORMALIZED TO VOLTS)
2.00
2.05
2.10
2420 F09a
1.95
1.90
1.80
1.85
2.20
2.15
V
IN
= 300mV
P-P
+ 2V DC
FREQUENCY (Hz)
MAGNITUDE (dB)
60
40
20
0
2420 F09b
80
100
120
15Hz
100sps
2V OFFSET
TIME
ADC OUTPUT (NORMALIZED TO VOLTS)
0.00
0.05
0.10
2420 F09c
0.05
0.10
0.20
0.15
0.20
0.15
V
IN
= 300mV
P-P
+ 0V DC
9c. Digitized Waveform with No Offset
Figure 9. Using the LTC2420's High Accuracy Wide Dynamic Range to Digitize
a 300mV
P-P
15Hz Waveform with a Large DC Offset (V
CC
= 5V, V
REF
= 5V)
9d. FFT Waveform with No Offset
large DC offset. Figures 9a and 9b show the dynamic
performance with a 15Hz signal superimposed on a 2V DC
level. The same signal with no DC level is shown in Figures
9c and 9d.
FREQUENCY (Hz)
MAGNITUDE (dB)
60
40
20
0
2420 F09d
80
100
120
15Hz
100sps
0V OFFSET
10
LTC2420
Figure 10. The LT1920 is a Simple Solution That Converts a Differential Input
to a Ground Referred Single-Ended Signal for the LTC2420
Single-Chip Instrumentation Amplifier
for the LTC2420
The circuit in Figure 10 is a simple solution for processing
differential signals in pressure transducer, weigh scale or
strain gauge applications that can operate on a supply
voltage range of
5V to
15V. The circuit uses an LT
1920
single-chip instrumentation amplifier to perform a differ-
ential to single-ended conversion. The amplifier's output
voltage is applied to the LTC2420's input and converted to
a digital value with an overall accuracy exceeding 17 bits
(0.0008%). Key circuit performance results are shown in
Table 3.
The practical gain range for this topology as shown is from
5 to 100 because the LTC2420's wide dynamic range
makes gains below 5 virtually unnecessary, whereas gain
up to 100 significantly reduce the input referred noise.
The optional passive RC lowpass filter between the
amplifier's output and the LTC2420's input attenuates
high frequency noise and its effects. Typically, the filter
reduces the magnitude of averaged noise by 30% and
improves resolution by 0.5 bit without compromising
linearity. Resistor R2 performs two functions: it isolates
C1 from the LTC2420's input and limits the LTC2420's
input current should its input voltage drop below 300mV
or swing above V
CC
+ 300mV.
The LT1920 is the choice for applications where low cost
is important. For applications where more precision is
required, the LT1167 is a pin-to-pin alternative choice with
a lower offset voltage, lower input bias current and higher
gain accuracy than the LT1920. The LT1920's maximum
total input-referred offset (V
OST
) is 135
V for a gain of
100. At the same gain, the LT1167's V
OST
is 63
V. At gains
of 10 or 100, the LT1920's maximum gain error is 0.3%
and its maximum gain nonlinearity is 30ppm. At the same
gains, the LT1167's maximum gain error is 0.1% and its
maximum gain nonlinearity is 15ppm. Table 4 summa-
rizes the performance of Figure 10's circuit using the
LT1167.
V
S
+
V
S
7
2
1
8
3
4
6
V
IN
+
V
IN
R
G
R
G
**
DIFFERENTIAL
INPUT
R
G
3
2
1
*OPTIONAL--SEE TEXT
**R
G
= 49.4k/(A
V
1): USE 5.49k FOR A
V
= 10; 499
FOR A
V
= 100
USE SHORT LEAD LENGTHS
4
8
2429 F10
5
6
7
CHIP SELECT
SERIAL DATA OUT
SERIAL CLOCK
CS
SDO
SCK
0.1
F
0.1
F
5V
R1*
47
C1*
1
F
SINGLE POINT
"STAR" GROUND
R2*
10k
0.1
F
V
IN
V
REF
V
REFIN
V
CC
GND
LTC2420
F
O
LT1920
APPLICATIO S I FOR ATIO
W
U
U
U
11
LTC2420
APPLICATIO S I FOR ATIO
W
U
U
U
Table 3. Typical Performance of the LTC2420 ADC When Used with the
LT1920 Instrumentation Amplifiers in Figure 9's Differential Digitizing Circuit
V
S
=
5V
V
S
=
15V
PARAMETER
A
V
= 10
A
V
= 100
A
V
= 10
A
V
= 100
TOTAL (UNITS)
Differential Input Voltage Range
30 to 400
3 to 40
30 to 500
3 to 50
mV
Zero Error
160
2650
213
2625
V
Maximum Input Current
2.0
nA
Nonlinearity
8.2
7.4
6.5
6.1
ppm
Noise (Without Averaging)
1.8*
0.25*
1.5*
0.27*
V
RMS
Noise (Averaged 64 Readings)
0.2*
0.03*
0.19*
0.03*
V
RMS
Resolution (with Averaged Readings)
21
20.6
21.3
20.5
Bits
Overall Accuracy (Uncalibrated)
17.2
17.3
17.5
18.2
Bits
Common Mode Rejection Ratio
120
dB
Common Mode Range
2/1.5**
2.2/1.7**
11.5/11**
11.7/11.2**
V
*Input referred noise for the respective gain. **Typical values based on single lab tested sample of each amplifier.
Table 4. Typical Performance of the LTC2420 ADC When Used with the
LT1167 Instrumentation Amplifiers in Figure 9's Differential Digitizing Circuit
V
S
=
5V
V
S
=
15V
PARAMETER
A
V
= 10
A
V
= 100
A
V
= 10
A
V
= 100
TOTAL (UNITS)
Differential Input Voltage Range
30 to 400
3 to 40
30 to 500
3 to 50
mV
Zero Error
94
1590
110
1470
V
Maximum Input Current
0.5
nA
Nonlinearity
4.1
4.4
4.1
3.7
ppm
Noise (Without Averaging)
1.4*
0.19*
1.5*
0.18*
V
RMS
Noise (Averaged 64 Readings)
0.18*
0.02*
0.19*
0.02*
V
RMS
Resolution (with Averaged Readings)
21.4
21.0
21.3
21.1
Bits
Overall Accuracy (Uncalibrated)
18.2
18.1
18.2
19.4
Bits
Common Mode Rejection Ratio
120
dB
Common Mode Range
2/1.5**
2.2/1.7**
11.5/11**
11.7/11.2**
V
*Input referred noise for the respective gain. **Typical values based on single lab tested sample of each amplifier.
12
LTC2420
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1019
Precision Bandgap Reference, 2.5V, 5V
3ppm/
C Drift, 0.05% Max
LT1025
Micropower Thermocouple Cold Junction Compensator
0.5
C Initial Accuracy, 80
A Supply Current
LTC1043
Dual Precision Instrumentation Switched Capacitor
Precise Charge, Balanced Switching, Low Power
Building Block
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5
V Offset, 1.6
V
P-P
Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max, 5ppm/
C Drift
LTC1391
8-Channel Multiplexer
Low R
ON
: 45
, Low Charge Injection, Serial Interface
LT1460
Micropower Series Reference
0.075% Max, 10ppm/
C Max Drift, 2.5V, 5V and 10V Versions,
MSOP, PDIP, SO-8, SOT-23 and TO-92 Packages
LTC2400
24-Bit
Power, No Latency
ADC in SO-8
4ppm INL, 10ppm Total Unadjusted Error, 200
A
LTC2408
8-Channel, 24-Bit No Latency
ADC
4ppm INL, 10ppm Total Unadjusted Error, 200
A
2420i LT/TP 0100 4K PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2000
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear-tech.com
PACKAGE I FOR ATIO
U
U
W
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.016 0.050
(0.406 1.270)
0.010 0.020
(0.254 0.508)
45
0
8
TYP
0.008 0.010
(0.203 0.254)
SO8 1298
0.053 0.069
(1.346 1.752)
0.014 0.019
(0.355 0.483)
TYP
0.004 0.010
(0.101 0.254)
0.050
(1.270)
BSC
1
2
3
4
0.150 0.157**
(3.810 3.988)
8
7
6
5
0.189 0.197*
(4.801 5.004)
0.228 0.244
(5.791 6.197)
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
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