LTC2424/LTC2428

4-/8-Channel 20-Bit

Power

No Latency

ADCs

March 2000

The LTC

2424/LTC2428 are 4-/8-channel 2.7V to 5.5V

micropower 20-bit A/D converters with an integrated
oscillator, 8ppm INL and 1.2ppm RMS noise. They use
delta-sigma technology and provide single cycle digital
filter settling time (no latency delay) for multiplexed
applications. The first conversion after the channel is
changed is always valid. Through a single pin the LTC2424/
LTC2428 can be configured for better than 110dB rejec-
tion at 50Hz or 60Hz

2%, or can be driven by an external

oscillator for a user defined rejection frequency in the
range 1Hz to 800Hz. The internal oscillator requires no
external frequency setting components.

The converters accept any external reference voltage from
0.1V to V

. With their extended input conversion range of

12.5% V

REF

to 112.5% V

REF

= FS

SET

) the

LTC2424/LTC2428 smoothly resolve the offset and
overrange problems of preceding sensors or signal con-
ditioning circuits.

The LTC2424/LTC2428 communicate through a flexible
4-wire digital interface which is compatible with SPI and
MICROWIRE

protocols.

Pin Compatible 4-/8-Channel 20-Bit ADCs

8ppm INL, No Missing Codes at 20 Bits

4ppm Full-Scale Error and 0.5ppm Offset

1.2ppm Noise

Digital Filter Settles in a Single Cycle. Each
Conversion is Accurate, Even After Changing
Channels

Fast Mode: 16-Bit Noise, 12-Bit TUE at 100sps

Internal Oscillator--No External Components
Required

110dB Min, 50Hz/60Hz Notch Filter

Reference Input Voltage: 0.1V to V

Live Zero--Extended Input Range Accommodates
12.5% Overrange and Underrange

Single Supply 2.7V to 5.5V Operation

Low Supply Current (200

A) and Auto Shutdown

Can Be Interchanged with 24-Bit LTC2404/LTC2408
if ZS

SET

Pin is Grounded

Total Unadjusted Error vs Output Code

, LTC and LT are registered trademarks of Linear Technology Corporation.

No Latency

is a trademark of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corporation.

Weight Scales

Direct Temperature Measurement

Gas Analyzers

Strain-Gage Transducers

Instrumentation

Data Acquisition

Industrial Process Control

4-Digit DVMs

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

ANALOG

INPUTS

0.12V

REF

1.12V

REF

24248 TA01

CH0

CH1

CH2

CH3

CH4*

CH5*

CH6*

CH7*

4-/8-CHANNEL

MUX

SET

*THESE PINS ARE NO CONNECTS ON THE LTC2404

GND

1, 6, 16, 18, 22, 27, 28

MPU

SERIAL DATA LINK

MICROWIRE AND

SPI COMPATABLE

CSADC

CSMUX

SCK

CLK

SDO

20-BIT

ADC

LTC2424/LTC2428

0.1V TO V

ADCIN

MUXOUT

2, 8

2.7V TO 5.5V

SET

= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION

OUTPUT CODE (DECIMAL)

8,338,608

16,777,215

LINEARITY ERROR (ppm)

24248 TA02

= 5V

REF

= 5V

= 25

= LOW

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Final Electrical Specifications

LTC2424/LTC2428

ORDER

PART NUMBER

Consult factory for Military grade parts.

(Notes 1, 2)

Supply Voltage (V

) to GND ....................... 0.3V to 7V

Analog Input Voltage to GND ....... 0.3V to (V

+ 0.3V)

Reference Input Voltage to GND .. 0.3V to (V

+ 0.3V)

Digital Input Voltage to GND ........ 0.3V to (V

+ 0.3V)

Digital Output Voltage to GND ..... 0.3V to (V

+ 0.3V)

JMAX

= 125

= 130

C/W

LTC2424CG
LTC2424IG

Operating Temperature Range

LTC2424C/LTC2428C .............................. 0

C to 70

LTC2424I/LTC2428I ........................... 40

C to 85

Storage Temperature Range ................. 65

C to 150

Lead Temperature (Soldering, 10 sec).................. 300

ORDER

PART NUMBER

LTC2428CG
LTC2428IG

JMAX

= 125

= 130

C/W

ABSOLUTE

AXI

RATINGS

PACKAGE/ORDER I

FOR

ATIO

TOP VIEW

G PACKAGE

28-LEAD PLASTIC SSOP

GND

SET

ADCIN

SET

GND

MUXOUT

CH0

CH1

CH2

CH3

GND

SCK

SDO

CSADC

GND

CSMUX

CLK

GND

TOP VIEW

G PACKAGE

28-LEAD PLASTIC SSOP

GND

SET

ADCIN

SET

GND

MUXOUT

CH0

CH1

CH2

CH3

CH4

CH5

GND

SCK

SDO

CSADC

GND

CSMUX

CLK

GND

CH7

GND

CH6

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Resolution (No Missing Codes)

0.1V

REF

, (Note 5)

Bits

Integral Nonlinearity

REF

= 2.5V (Note 6)

ppm of V

REF

= 5V (Note 6)

ppm of V

REF

Integral Nonlinearity (Fast Mode)

2.5V < V

REF

< V

, 100 Samples/Second, f

= 2.048MHz

250

ppm of V

REF

Offset Error

2.5V

REF

0.5

ppm of V

REF

Offset Error (Fast Mode)

2.5V < V

REF

< 5V, 100 Samples/Second, f

= 2.048MHz

ppm of V

REF

Offset Error Drift

2.5V

REF

0.04

ppm of V

REF

Full-Scale Error

2.5V

REF

ppm of V

REF

Full-Scale Error (Fast Mode)

2.5V < V

REF

< 5V, 100 Samples/Second, f

= 2.048MHz

ppm of V

REF

Full-Scale Error Drift

2.5V

REF

0.04

ppm of V

REF

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. (Notes 3, 4)

VERTER CHARACTERISTICS

LTC2424/LTC2428

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Input Voltage Range

(Note 14)

0.125 · V

REF

1.125 · V

REF

Reference Voltage Range

0.1

S(IN)

Input Sampling Capacitance

S(REF)

Reference Sampling Capacitance

1.5

IN(LEAK)

Input Leakage Current

CS = V

100

REF(LEAK)

Reference Leakage Current

REF

= 2.5V, CS = V

100

IN(MUX)

On Channel Leakage Current

= 2.5V (Note 15)

MUX On-Resistance

OUT

= 1mA, V

= 2.7V

250

300

OUT

= 1mA, V

= 5V

120

250

MUX

vs Temperature

0.5

vs V

(Note 15)

S(OFF)

MUX Off Input Leakage

Channel Off, V

= 2.5V

D(OFF)

MUX Off Output Leakage

Channel Off, V

= 2.5V

OPEN

MUX Break-Before-Make Interval

290

Enable Turn-On Time

= 1.5V, R

= 3.4k, C

= 15pF

490

OFF

Enable Turn-Off Time

= 1.5V, R

= 3.4k, C

= 15pF

190

QIRR

MUX Off Isolation

= 2V

P-P

, R

= 1k, f = 100kHz

QINJ

Charge Injection

= 0

, C

= 1000pF, V

= 1V

S(OFF)

Input Off Capacitance (MUX)

D(OFF)

Output Off Capacitance (MUX)

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. (Note 3)

A ALOG I PUT A D REFERE CE

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Total Unadjusted Error

REF

= 2.5V

ppm of V

REF

= 5V

ppm of V

REF

Output Noise

= 0V, V

REF

= 5V (Note 13)

RMS

Output Noise (Fast Mode)

REF

= 5V, 100 Samples/Second, f

= 2.048MHz

RMS

Normal Mode Rejection 60Hz

(Note 7)

110

130

Normal Mode Rejection 50Hz

(Note 8)

110

130

Power Supply Rejection, DC

REF

= 2.5V, V

= 0V

100

Power Supply Rejection, 60Hz

REF

= 2.5V, V

= 0V, (Notes 7, 16)

110

Power Supply Rejection, 50Hz

REF

= 2.5V, V

= 0V, (Notes 8, 16)

110

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. (Notes 3, 4)

VERTER CHARACTERISTICS

LTC2424/LTC2428

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

High Level Input Voltage

2.7V

5.5V

2.5

CS, F

2.7V

3.3V

2.0

Low Level Input Voltage

4.5V

5.5V

0.8

CS, F

2.7V

5.5V

0.6

High Level Input Voltage

2.7V

5.5V (Note 9)

2.5

SCK

2.7V

3.3V (Note 9)

2.0

Low Level Input Voltage

4.5V

5.5V (Note 9)

0.8

SCK

2.7V

5.5V (Note 9)

0.6

Digital Input Current

CS, F

Digital Input Current

(Note 9)

SCK

Digital Input Capacitance

CS, F

Digital Input Capacitance

(Note 9)

SCK

High Level Output Voltage

= 800

0.5V

SDO

Low Level Output Voltage

= 1.6mA

0.4V

SDO

High Level Output Voltage

= 800

A (Note 10)

0.5V

SCK

Low Level Output Voltage

= 1.6mA (Note 10)

0.4V

SCK

High-Z Output Leakage

SDO

MUX

MUX High Level Input Voltage

= 3V

MUX

MUX Low Level Input Voltage

= 2.4V

0.8

The

denotes specifications which apply over the full

operating temperature range, otherwise specifications are at T

= 25

C. (Note 3)

DIGITAL I PUTS A D DIGITAL OUTPUTS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Supply Voltage

2.7

5.5

Supply Current (Pin 2)

Conversion Mode

CS = 0V (Note 12)

200

300

Sleep Mode

CS = V

(Note 12)

CC(MUX)

Multiplexer Supply Current (Pin 8)

All Logic Inputs Tied Together

= 0V or 5V

The

denotes specifications which apply over the full operating temperature range,

otherwise specifications are at T

= 25

C. (Note 3)

POWER REQUIRE E TS

LTC2424/LTC2428

The

denotes specifications which apply over the full operating temperature range,

otherwise specifications are at T

= 25

C. (Note 3)

EOSC

External Oscillator Frequency Range

20-Bit Effective Resolution

2.56

307.2

kHz

12-Bit Effective Resolution

2.56k

2.048M

HEO

External Oscillator High Period

0.5

390

LEO

External Oscillator Low Period

0.5

390

CONV

Conversion Time

= 0V

130.66

133.33

136

= V

156.80

160

163.20

External Oscillator (Note 11)

20480/f

EOSC

(in kHz)

ISCK

Internal SCK Frequency

Internal Oscillator (Note 10)

19.2

kHz

External Oscillator (Notes 10, 11)

EOSC

kHz

ISCK

Internal SCK Duty Cycle

(Note 10)

ESCK

External SCK Frequency Range

(Note 9)

2000

kHz

LESCK

External SCK Low Period

(Note 9)

250

HESCK

External SCK High Period

(Note 9)

250

DOUT_ISCK

Internal SCK 24-Bit Data Output Time

Internal Oscillator (Notes 10, 12)

1.23

1.25

1.28

External Oscillator (Notes 10, 11)

192/f

EOSC

(in kHz)

DOUT_ESCK

External SCK 24-Bit Data Output Time

(Note 9)

24/f

ESCK

(in kHz)

to SDO Low Z

150

to SDO High Z

150

to SCK

(Note 10)

150

to SCK

(Note 9)

KQMAX

SCK

to SDO Valid

200

KQMIN

SDO Hold After SCK

(Note 5)

SCK Set-Up Before CS

SCK Hold After CS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.

Note 2: All voltage values are with respect to GND.

Note 3: V

= 2.7 to 5.5V unless otherwise specified, source input

is 0

. CSADC = CSMUX = CS. V

REF

= FS

SET

Note 4: Internal Conversion Clock source with the F

pin tied

to GND or to V

or to external conversion clock source with

EOSC

= 153600Hz unless otherwise specified.

Note 5: Guaranteed by design, not subject to test.

Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.

Note 7: F

= 0V (internal oscillator) or f

EOSC

= 153600Hz

(external oscillator).

Note 8: F

= V

(internal oscillator) or f

EOSC

= 128000Hz

(external oscillator).

Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is f

ESCK

and is expressed in kHz.

Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance C

LOAD

= 20pF.

Note 11: The external oscillator is connected to the F

pin. The external

oscillator frequency, f

EOSC

, is expressed in kHz.

Note 12: The converter uses the internal oscillator.
F

= 0V or F

= V

Note 13: The output noise includes the contribution of the internal
calibration operations.

Note 14: For reference voltage values V

REF

> 2.5V the extended input

of 0.125 · V

REF

to 1.125 · V

REF

is limited by the absolute maximum

rating of the Analog Input Voltage pin (Pin 3). For 2.5V < V

REF

0.267V + 0.89 · V

the input voltage range is 0.3V to 1.125 · V

REF

For 0.267V + 0.89 · V

< V

REF

the input voltage range is 0.3V

to V

+ 0.3V.

Note 15: V

is the voltage applied to a channel input. V

is the voltage

applied to the MUX output.

Note 16: V

CC(DC)

= 4.1V, V

CC(AC)

= 2.8V

P-P

TI I G CHARACTERISTICS

LTC2424/LTC2428

CTIO

GND (Pins 1, 6, 16, 18, 22, 27, 28): Ground. Should be
connected directly to a ground plane through a minimum
length trace or it should be the single-point-ground in a
single-point grounding system.

(Pins 2, 8): Positive Supply Voltage. 2.7V

5.5V. Bypass to GND with a 10

F tantalum capacitor in

parallel with 0.1

F ceramic capacitor as close to the part

as possible.

SET

(Pin 3): Full-Scale Set Input. This pin defines the

full-scale input value. When V

= FS

SET

, the ADC outputs

full scale (FFFFF

). The total reference voltage (V

REF

) is

SET

ADCIN (Pin 4): Analog Input. The input voltage range is
0.125 · V

REF

to 1.125 · V

REF

. For V

REF

> 2.5V the input

voltage range may be limited by the pin absolute maxi-
mum rating of 0.3V to V

+ 0.3V.

SET

(Pin 5): Zero-Scale Set Input. This pin defines the

zero-scale input value. When V

= ZS

SET

, the ADC outputs

zero scale (00000

). For pin compatibility with the LTC2404/

LTC2408 this pin must be grounded.

MUXOUT (Pin 7): MUX Output. This pin is the output of the
multiplexer. Tie to ADCIN for normal operation.

CH0 (Pin 9): Analog Multiplexer Input.

CH1 (Pin 10): Analog Multiplexer Input.

CH2 (Pin 11): Analog Multiplexer Input.

CH3 (Pin 12): Analog Multiplexer Input.

CH4 (Pin 13): Analog Multiplexer Input. No connect on the
LTC2424.

CH5 (Pin 14): Analog Multiplexer Input. No connect on the
LTC2424.

CH6 (Pin 15): Analog Multiplexer Input. No connect on the
LTC2424.

CH7 (Pin 17): Analog Multiplexer Input. No connect on the
LTC2424.

CLK (Pin 19): Shift Clock for Data In. This clock synchro-
nizes the serial data transfer into the MUX. For normal
operation, drive this pin in parallel with SCK.

CSMUX (Pin 20): MUX Chip Select Input. A logic high on
this input allows the MUX to receive a channel address. A
logic low enables the selected MUX channel and connects
it to the MUXOUT pin for A/D conversion. For normal
operation, drive this pin in parallel with CSADC.

(Pin 21): Digital Data Input. The multiplexer address

is shifted into this input on the last four rising CLK edges
before CSMUX goes low.

CSADC (Pin 23): ADC Chip Select Input. A low on this pin
enables the SDO digital output and following each conver-
sion, the ADC automatically enters the Sleep mode and
remains in this low power state as long as CSADC is high.
A high on this pin also disables the SDO digital output. A
low-to-high transition on CSADC during the Data Output
state aborts the data transfer and starts a new conversion.
For normal operation, drive this pin in parallel with CSMUX.

SDO (Pin 24): Three-State Digital Output. During the data
output period this pin is used for serial data output. When
the chip select CSADC is high (CSADC = V

), the SDO pin

is in a high impedance state. During the Conversion and
Sleep periods, this pin can be used as a conversion status
output. The conversion status can be observed by pulling
CSADC low.

SCK (Pin 25): Shift Clock for Data Out. This clock synchro-
nizes the serial data transfer of the ADC data output. Data
is shifted out of SDO on the falling edge of SCK. For normal
operation, drive this pin in parallel with CLK.

(Pin 26): Digital input which controls the ADC's notch

frequencies and conversion time. When the F

pin is

connected to V

= V

), the converter uses its internal

oscillator and the digital filter first null is located at 50Hz.
When the F

pin is connected to GND (F

= OV), the

converter uses its internal oscillator and the digital filter
first null is located at 60Hz. When F

is driven by an

external clock signal with a frequency f

EOSC

, the converter

uses this signal as its clock and the digital filter first null is
located at a frequency f

EOSC

/2560. The resulting output

word rate is f

EOSC

/20480.

LTC2424/LTC2428

FU CTIO AL BLOCK DIAGRA

TEST CIRCUITS

3.4k

SDO

24248 TC01

Hi-Z TO V

TO V

TO Hi-Z

LOAD

= 20pF

3.4k

SDO

24248 TC02

Hi-Z TO V

TO V

TO Hi-Z

LOAD

= 20pF

AUTOCALIBRATION

AND CONTROL

DECIMATING FIR

INTERNAL

OSCILLATOR

SERIAL

INTERFACE

CHANNEL

SELECT

ADC

DAC

GND

8-CHANNEL MUX

CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7

SDO

SCK

SET

CSADC

(INT/EXT)

24248 BD

CSMUX

CLK

APPLICATIO

S I

FOR

ATIO

Converter Operation Cycle

The LTC2424/LTC2428 are low power, 4-/8-channel delta-
sigma analog-to-digital converters with easy-to-use
4-wire interfaces. Their operation is simple and made up
of four states. The converter operation begins with the
conversion, followed by a low power sleep state and
concluded with the data output (see Figure 1). Channel
selection may be performed while the device is in the sleep
state or at the conclusion of the data output state. The
interface consists of serial data output (SDO), serial clock
(CLK/SCK), chip select (CSADC/CSMUX) and data input

). By tying SCK to CLK and CSADC to CSMUX, the

interface requires only four wires.

Initially, the LTC2424 or LTC2428 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in the sleep state, power consumption
is reduced by an order of magnitude. The part remains in
the sleep state as long as CSADC is logic HIGH. The
conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.

Channel selection for the next conversion cycle is per-
formed while the device is in the sleep state or at the end

LTC2424/LTC2428

of the data output state. A specific channel is selected by
applying a 4-bit serial word to the D

pin on the rising edge

of CLK while CSMUX is HIGH, see Figure 4 and Table 3. The
channel is selected based on the last four bits clocked into
the D

pin before CSMUX goes low. If D

is all 0's, the

previous channel remains selected.

In the example, Figure 4, the MUX channel is selected
during the sleep state, just before the data output state
begins. Once the channel selection is complete, the device
remains in the sleep state as long as CSADC remains
HIGH.

Once CSADC is pulled low, the device begins outputting
the conversion result. There is no latency in the conversion
result. Since there is no latency, the first conversion
following a change in input channel is valid and corre-
sponds to that channel. The data output corresponds to
the conversion just performed. This result is shifted out on
the serial data output pin (SDO) under the control of the
serial clock (SCK). Data is updated on the falling edge of
SCK allowing the user to reliably latch data on the rising
edge of SCK, see Figure 4. The data output state is
concluded once 24 bits are read out of the ADC or when
CSADC is brought HIGH. The device automatically initiates
a new conversion and the cycle repeats.

Through timing control of the CSADC and SCK pins, the
LTC2424/LTC2428 offer two modes of operation: internal

APPLICATIO

S I

FOR

ATIO

Figure 1. LTC2428 State Transition Diagram

CONVERT

SLEEP

CHANNEL SELECT

(SLEEP)

DATA OUTPUT

(CHANNEL SELECT)

24248 F01

CSADC

AND

SCK

or external SCK. These modes do not require program-
ming configuration registers; moreover, they do not dis-
turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.

Conversion Clock

A major advantage delta-sigma converters offer over
conventional type converters is an on-chip digital filter
(commonly known as Sinc or Comb filter). For high
resolution, low frequency applications, this filter is typi-
cally designed to reject line frequencies of 50 or 60Hz plus
their harmonics. In order to reject these frequencies in
excess of 110dB, a highly accurate conversion clock is
required. The LTC2424/LTC2428 incorporate an on-chip
highly accurate oscillator. This eliminates the need for
external frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the LTC2424/
LTC2428 reject line frequencies (50 or 60Hz

2%) a

minimum of 110dB.

Ease of Use

The LTC2424/LTC2428 data output has no latency, filter
settling or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
an analog input voltage is easy.

The LTC2424/LTC2428 perform offset and full-scale cali-
brations every conversion cycle. This calibration is trans-
parent to the user and has no effect on the cyclic operation
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage change and temperature
drift.

Power-Up Sequence

The LTC2424/LTC2428 automatically enter an internal
reset state when the power supply voltage V

drops

below approximately 2.2V. When the V

voltage rises

above this critical threshold, the converter creates an
internal power-on-reset (POR) signal with duration of
approximately 0.5ms. The POR signal clears all internal
registers within the ADC and initiates a conversion. At

LTC2424/LTC2428

APPLICATIO

S I

FOR

ATIO

Figure 2. LTC2424/LTC2428 Input Range

24248 F02

+ 0.3V

9/8V

REF

1/2V

REF

0.3V

1/8V

REF

NORMAL

INPUT

RANGE

EXTENDED

INPUT

RANGE

ABSOLUTE
MAXIMUM

INPUT

RANGE

power-up, the multiplexer channel is disabled and should
be programmed once the device enters the sleep state.
The results of the first conversion following a POR are not
valid since a multiplexer channel was disabled.

Reference Voltage Range

The LTC2424/LTC2428 can accept a reference voltage
from 0V to V

. The converter output noise is determined

by the thermal noise of the front-end circuits, and as such,
its value in microvolts is nearly constant with reference
voltage. A decrease in reference voltage will not signifi-
cantly improve the converter's effective resolution. On the
other hand, a reduced reference voltage will improve the
overall converter INL performance. The recommended
range for the LTC2424/LTC2428 voltage reference is
100mV to V

Input Voltage Range

The converter is able to accommodate system level offset
and gain errors as well as system level overrange
situations due to its extended input range, see Figure 2.
The LTC2424/LTC2428 converts input signals within the
extended input range of 0.125 · V

REF

to 1.125 · V

REF

= FS

SET

For large values of V

REF

this range is limited to a voltage

range of 0.3V to (V

+ 0.3V). Beyond this range the input

ESD protection devices begin to turn on and the errors due
to the input leakage current increase rapidly.

Input signals applied to V

may extend below ground by

300mV and above V

by 300mV. In order to limit any fault

current, a resistor of up to 5k may be added in series with

any channel input pin (CH0 to CH7) without affecting the
performance of the device. In the physical layout, it is im-
portant to maintain the parasitic capacitance of the connec-
tion between this series resistance and the channel input
pin as low as possible; therefore, the resistor should be
located as close as practical to the channel input pin. The
effect of the series resistance on the converter accuracy can
be evaluated from the curves presented in the Analog In-
put/Reference Current section. In addition, a series resis-
tor will introduce a temperature dependent offset error due
to the input leakage current. A 1nA input leakage current
will develop a 1ppm offset error on a 5k resistor if V

REF

5V. This error has a very strong temperature dependency.

Output Data Format

The LTC2424/LTC2428 serial output data stream is 24 bits
long. The first 4 bits represent status information indicat-
ing the sign, input range and conversion state. The next 20
bits are the conversion result, MSB first.

The LTC2424/LTC2428 can be interchanged with the
LTC2404/LTC2408. The two devices are designed to allow
the user to incorporate either device in the same design as
long as ZS

SET

of the LTC2424/LTC2428 is tied to ground.

While the LTC2424/LTC2428 output word lengths are 24
bits (as opposed to the 32-bit output of the LTC2404/
LTC2408), their output clock timing can be identical to the
LTC2404/LTC2408. As shown in Figure 3, the LTC2424/
LTC2408 data output is concluded on the falling edge of the
24th serial clock (SCK). In order to maintain drop-in com-
patibility with the LTC2404/LTC2408, it is possible to clock
the LTC2424/LTC2428 with an additional 8 serial clock
pulses. This results in 8 additional output bits which are
always logic HIGH.

Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.

Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.

Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If V

is >0, this bit is HIGH. If V

is <0, this

bit is LOW. The sign bit changes state during the zero code.

LTC2424/LTC2428

indicating a new conversion cycle has been initiated. This
bit serves as EOC (Bit 23) for the next conversion cycle.
Table 2 summarizes the output data format.

As long as the voltage on the V

pin is maintained within

the 0.3V to (V

+ 0.3V) absolute maximum operating

range, a conversion result is generated for any input value
from 0.125 · V

REF

to 1.125 · V

REF

For input voltages

greater than 1.125 · V

REF

, the conversion result is clamped

to the value corresponding to 1.125 · V

REF

. For input

voltages below 0.125 · V

REF

, the conversion result is

clamped to the value corresponding to 0.125 · V

REF

Channel Selection

Typically, CSADC and CSMUX are tied together or CSADC
is inverted and drives CSMUX. SCK and CLK are tied
together and driven with a common clock signal. During
channel selection, CSMUX is HIGH. Data is shifted into the
D

pin on the rising edge of CLK, see Figure 4. Table 3

shows the bit combinations for channel selection. In order
to enable the multiplexer output, CSMUX must be pulled
LOW. The multiplexer should be programmed after the
previous conversion is complete. In order to guarantee the
conversion is complete, the multiplexer addressing should
be delayed a minimum t

CONV

(approximately 133ms for a

60Hz notch) after the data out is read.

While the multiplexer is being programmed, the ADC is in
a low power sleep state. Once the MUX addressing is
complete, the data from the preceding conversion can be
read. A new conversion cycle is initiated following the data
read cycle with the analog input tied to the newly selected
channel.

APPLICATIO

S I

FOR

ATIO

Bit 20 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0

REF

, this bit is LOW. If the input is outside the

normal input range, V

> V

REF

or V

< 0, this bit is HIGH.

The function of these bits is summarized in Table 1.

Table 1. LTC2424/LTC2428 Status Bits

Bit 23

Bit 22

Bit 21

Bit 20

Input Range

EOC

DMY

SIG

EXR

> V

REF

0 < V

REF

= 0

1/0

< 0

Bit 19 (fifth output bit) is the most significant bit (MSB).

Bits 19-0 are the 20-bit conversion result MSB first.

Bit 0 is the least significant bit (LSB).

Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 4. Whenever CSADC is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.

In order to shift the conversion result out of the device,
CSADC must first be driven LOW. EOC is seen at the SDO
pin of the device once CSADC is pulled LOW. EOC changes
real time from HIGH to LOW at the completion of a
conversion. This signal may be used as an interrupt for an
external microcontroller. Bit 23 (EOC) can be captured on
the first rising edge of SCK. Bit 22 is shifted out of the
device on the first falling edge of SCK. The final data bit (Bit
0) is shifted out on the falling edge of the 23rd SCK and
may be latched on the rising edge of the 24th SCK pulse.
On the falling edge of the 24th SCK pulse, SDO goes HIGH

CSADC

SCK

SDO

CONVERSION

SLEEP

8 (OPTIONAL)

EOC = 1

LAST 8 BITS ALWAYS 1

EOC = 0

DATA OUT

4 STATUS BITS 20 DATA BITS

DATA OUTPUT

24248 F03

CONVERSION

Figure 3. LTC2424/LTC2428 Compatible Timing with the LTC2404/LTC2408

LTC2424/LTC2428

Table 3. Logic Table for Channel Selection

CHANNEL STATUS

All Off

CH0

CH1

CH2

CH3

CH4*

CH5*

CH6*

CH7*

*Not used for the LTC2424.

APPLICATIO

S I

FOR

ATIO

Frequency Rejection Selection (F

Pin Connection)

The LTC2424/LTC2428 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz

2% or 60Hz

2%. For

60Hz rejection, F

(Pin 26) should be connected to GND

(Pin 1) while for 50Hz rejection the F

pin should be

connected to V

(Pin 2).

The selection of 50Hz or 60Hz rejection can also be made
by driving F

to an appropriate logic level. A selection

change during the sleep or data output states will not
disturb the converter operation. If the selection is made

Figure 4. Typical Data Input/Output Timing

EOC

"0"

SDO

SCK/CLK

CSMUX/CSADC

MSB

LSB

EXT

SIG

BIT 22

BIT 23

BIT 0

24248 F04

Hi-Z

DON'T CARE

CONV

Hi-Z

Table 2. LTC2424/LTC2428 Output Data Format

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

Bit 16

Bit 15

...

Bit 0

Input Voltage

EOC

DMY

SIG

EXR

MSB

LSB

> 9/8 · V

REF

...

9/8 · V

REF

...

REF

+ 1LSB

...

REF

...

3/4V

REF

+ 1LSB

...

3/4V

REF

...

1/2V

REF

+ 1LSB

...

1/2V

REF

...

1/4V

REF

+ 1LSB

...

1/4V

REF

...

1/0*

...

1LSB

...

1/8 · V

REF

...

< 1/8 · V

REF

...

*The sign bit changes state during the 0 code.

LTC2424/LTC2428

APPLICATIO

S I

FOR

ATIO

Figure 5. LTC2424/LTC2428 Normal Mode Rejection When
Using an External Oscillator of Frequency f

EOSC

during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.

When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2424/
LTC2428 can operate with an external conversion clock.
The converter automatically detects the presence of an
external clock signal at the F

pin and turns off the internal

oscillator. The frequency f

EOSC

of the external signal must

be at least 2560Hz (1Hz notch frequency) to be detected.
The external clock signal duty cycle is not significant as
long as the minimum and maximum specifications for the
high and low periods t

HEO

and t

LEO

are observed.

While operating with an external conversion clock of a
frequency f

EOSC

, the LTC2424/LTC2428 provide better

than 110dB normal mode rejection in a frequency range
f

EOSC

/2560

4% and its harmonics. The normal mode

rejection as a function of the input frequency deviation
from f

EOSC

/2560 is shown in Figure 5.

Whenever an external clock is not present at the F

pin the

converter automatically activates its internal oscillator
and enters the Internal Conversion Clock mode. The
LTC2424/LTC2428 operation will not be disturbed if the
change of conversion clock source occurs during the
sleep state or during the data output state while the

converter uses an external serial clock. If the change
occurs during the conversion state, the result of the
conversion in progress may be outside specifications but
the following conversions will not be affected. If the
change occurs during the data output state and the
converter is in the Internal SCK mode, the serial clock duty
cycle may be affected but the serial data stream will
remain valid.

Table 4 summarizes the duration of each state as a
function of F

INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)

REJECTION (dB)

24248 F05

100

110

120

130

140

Table 4. LTC2424/LTC2428 State Duration

State

Operating Mode

Duration

CONVERT

Internal Oscillator

= LOW (60Hz Rejection)

133ms

= HIGH (50Hz Rejection)

160ms

External Oscillator

= External Oscillator

20480/f

EOSC

(In Seconds)

with Frequency f

EOSC

kHz

EOSC

/2560 Rejection)

SLEEP

As Long As CSADC = HIGH Until CSADC = 0 and SCK

DATA OUTPUT

Internal Serial Clock

= LOW/HIGH

As Long As CSADC = LOW But Not Longer Than 1.67ms

(Internal Oscillator)

(32 SCK cycles)

= External Oscillator with

As Long As CSADC = LOW But Not Longer Than 256/f

EOSC

Frequency f

EOSC

kHz

(32 SCK cycles)

External Serial Clock with

As Long As CSADC = LOW But Not Longer Than 32/f

SCK

Frequency f

SCK

kHz

(32 SCK cycles)

MAXIMUM OUTPUT
WORD RATE (OWR)

OWR

in Hz

CONVERT

DATAOUTPUT

LTC2424/LTC2428

data rate with a 5V reference. The relationship between the
output data rate (ODR) and the frequency applied to the F

pin (F

) is:

ODR = F

/20480

For output data rates up to 50 samples/second, the total
unadjusted error (TUE) is better than 16 bits, and better
than 12 bits at 100 samples/second. As shown in Figure 8,
for output data rates of 100 samples/second, the TUE is
better than 15 bits for V

REF

below 2.5V. Figure 9 shows an

unaveraged total unadjusted error for the LTC2424 or
LTC2428 operating at 100 samples/second with V

REF

2.5V. Figure 10 shows the same device operating with a 5V
reference and an output data rate of 7.5 samples/second.

Operation at Higher Data Output Rates

The LTC2424/LTC2428 typically operate with an internal
oscillator of 153.6kHz. This corresponds to a notch fre-
quency of 60Hz and an output rate of 7.5 samples/second.
The internal oscillator is enabled if the F

pin is logic LOW

(logic HIGH for a 50Hz notch). It is possible to drive the F

pin with an external oscillator for higher data output rates.
As shown in Figure 6, an external clock of 2.048MHz
applied to the F

pin results in a notch frequency of 800Hz

with a data output rate of 100 samples/second.

Figure 7 shows the total unadjusted error (Offset Error +
Full-Scale Error + INL + DNL) as a function of the output

APPLICATIO

S I

FOR

ATIO

OUTPUT RATE (SAMPLES/SEC)

TOTAL UNADJUSTED ERROR (ppm)

128

160

12 BITS

13 BITS

14 BITS

16 BITS

24248 F07

100

192

224

256

REF

= 5V

150

Figure 7. Total Error vs Output Rate (V

REF

= 5V)

LTC2424

0.1

HCO4

C7
10pF

270pF

C8 5pF

R7 5k

R6 47k

R8 1k

10k

10 TVEN POT

SWITCH

R9 1k

24248 F06

GND

SET

ADCIN

SET

GND

MUXOUT

CH0

CH1

CH2

CH3

GND

SCK

SDO

CSADC

GND

CSMUX

CLK

GND

Figure 6. Selectable 100 Sample/Second Turbo Mode

REFERENCE VOLTAGE (V)

1.0

TOTAL UNADJUSTED ERROR (ppm)

128

192

5.0

24248 F08

2.0

3.0

4.0

1.5

2.5

3.5

4.5

256

160

224

OUTPUT RATE = 100sps

12 BITS

13 BITS

14 BITS

15 BITS

Figure 8. Total Error vs V

REF

(Output Rate = 100sps)

INPUT VOLTAGE (V)

TOTAL UNADJUSTED ERROR (ppm)

24248 F09

2.5

= 5V

REF

= 2.5V

Figure 9. Total Unadjusted Error at
100 Samples/Second (No Averaging)

LTC2424/LTC2428

APPLICATIO

S I

FOR

ATIO

At 100 samples/second, the LTC2424/LTC2428 can be
used to capture transient data. This is useful for monitor-
ing settling or auto gain ranging in a system. The LTC2424/
LTC2428 can monitor signals at an output rate of 100
samples/second. After acquiring 100 samples/second data,
the F

pin may be driven LOW enabling 60Hz rejection to

110dB and the highest possible DC accuracy. The no
latency architecture of the LTC2424/LTC2428 allows con-
secutive readings (one at 100 samples/second the next at
7.5 samples/second) without interaction between the two
readings.

As shown in Figure 11, the LTC2424/LTC2428 can cap-
ture transient data with 90dB of dynamic range (with a

INPUT VOLTAGE (V)

TOTAL UNADJUSTED ERROR (ppm)

24248 F10

= 5V

REF

= 5V

Figure 10. Total Unadjusted Error at
7.5 Samples/Second (No Averaging)

300mV

P-P

input signal at 2Hz). The exceptional DC

performance of the LTC2424/LTC2428 enables signals to
be digitized independent of a large DC offset. Figures 12a
and 12b show the dynamic performance with a 15Hz
signal superimposed on a 2V DC level. The same signal
with no DC level is shown in Figures 12c and 12d.

SERIAL INTERFACE

The LTC2424/LTC2428 transmit the conversion results,
program the channel selection, and receive the start of
conversion command through a synchronous 4-wire in-
terface (SCK = CLK, CSADC = CSMUX). During the conver-
sion and sleep states, this interface can be used to assess
the converter status. While in the sleep state this interface
may be used to program an input channel. During the data
output state, it is used to read the conversion result.

ADC Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 25) is used to
synchronize the data transfer. Each bit of data is shifted out
of the SDO pin on the falling edge of the serial clock.

In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2424/LTC2428 creates its own serial
clock by dividing the internal conversion clock by 8. In the
External SCK mode of operation, the SCK pin is used as
input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CSADC pin. If SCK is HIGH or

0.5

1.5

2.5

TIME (SEC)

ADC OUTPUT (NORMALIZED TO VOLTS)

0.05

0.10

24248 F11a

0.05

0.10

0.20

0.15

0.20

500ms

0.15

= 2Hz

MAGNITUDE (dB)

100

120

2Hz
100sps
0V OFFSET

24248 F11b

FREQUENCY (Hz)

Figure 11b. Output FFT

Figure 11a. Digitized Waveform

Figure 11. Transient Signal Acquisition

LTC2424/LTC2428

APPLICATIO

S I

FOR

ATIO

Figure 12. Using the LTC2424/LTC2428's High Accuracy Wide Dynamic Range
to Digitize a 300mV

P-P

15Hz Waveform with a Large DC Offset (V

= 5V, V

REF

= 5V)

1.5

2.5

0.5

TIME (SEC)

ADC OUTPUT (NORMALIZED TO VOLTS)

2.00

2.05

2.10

24248 F12a

1.95

1.90

1.80

1.85

2.20

2.15

= 300mV

P-P

+ 2V DC

FREQUENCY (Hz)

MAGNITUDE (dB)

24248 F12b

100

120

15Hz
100sps
2V OFFSET

1.5

2.5

0.5

TIME (SEC)

ADC OUTPUT (NORMALIZED TO VOLTS)

0.00

0.05

0.10

24248 F12c

0.05

0.10

0.20

0.15

0.20

0.15

= 300mV

P-P

+ 0V DC

FREQUENCY (Hz)

MAGNITUDE (dB)

24248 F12d

100

120

15Hz
100sps
0V OFFSET

Figure 12b. FFT Waveform with 2V DC Offset

Figure 12a. Digitized Waveform with 2V DC Offset

Figure 12d. FFT Waveform with No Offset

Figure 12c. Digitized Waveform with No Offset

floating at power-up or during this transition, the converter
enters the internal SCK mode. If SCK is LOW at power-up
or during this transition, the converter enters the external
SCK mode.

Multiplexer Serial Input Clock (CLK)

Generally, this pin is externally tied to SCK for 4-wire op-
eration. On the rising edge of CLK (Pin 19) with CSMUX held
HIGH, data is serially shifted into the multiplexer. If CSMUX
is LOW the CLK input will be disabled and the channel
selection unchanged.

Serial Data Output (SDO)

The serial data output pin, SDO (Pin 24), drives the serial
data during the data output state. In addition, the SDO pin

is used as an end of conversion indicator during the
conversion and sleep states.

When CSADC (Pin 23) is HIGH, the SDO driver is switched
to a high impedance state. This allows sharing the serial
interface with other devices. If CSADC is LOW during the
convert or sleep state, SDO will output EOC. If CSADC is
LOW during the conversion phase, the EOC bit appears
HIGH on the SDO pin. Once the conversion is complete,
EOC goes LOW. The device remains in the sleep state until
the first rising edge of SCK occurs while CSADC = 0.

ADC Chip Select Input (CSADC)

The active LOW chip select, CSADC (Pin 23), is used to test
the conversion status and to enable the data output
transfer as described in the previous sections.

LTC2424/LTC2428

APPLICATIO

S I

FOR

ATIO

In addition, the CSADC signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2424/LTC2428 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CSADC pin after the converter has entered the data output
state (i.e., after the first rising edge of SCK occurs with
CSADC = 0).

Multiplexer Chip Select (CSMUX)

For 4-wire operation, this pin is tied directly to CSADC or
the output of an inverter tied to CSADC. CSMUX (Pin 20)
is driven HIGH during selection of a multiplexer channel.
On the falling edge of CSMUX, the selected channel is
enabled and drives MUXOUT.

Data Input (D

)

The data input to the multiplexer, D

(Pin 21), is used to

program the multiplexer. The input channel is selected by
serially shifting a 4-bit input word into the D

pin under

the control of the multiplexer clock, CLK. Data is shifted
into the multiplexer on the rising edge of CLK. Table 3
shows the logic table for channel selection. In order to
select or change a previously programmed channel, an
enable bit (D

= 1) must proceed the 3-bit channel select

serial data. The user may set D

= 0 to continually convert

on the previously selected channel.

SERIAL INTERFACE TIMING MODES

The LTC2424/LTC2428's 4-wire interface is SPI and
MICROWIRE compatible. This interface offers two modes
of operation. These include an internal or external serial
clock. The following sections describe both of these serial
interface timing modes in detail. For both cases the
converter can use the internal oscillator (F

= LOW or F

= HIGH) or an external oscillator connected to the F

pin.

Refer to Table 5 for a summary.

External Serial Clock (SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock (SCK) to
shift out the conversion result, see Figure 13. This same
external clock signal drives the CLK pin in order to pro-
gram the multiplexer. A single CS signal drives both the
multiplexer CSMUX and converter CSADC inputs. This
common signal is used to monitor and control the state of
the conversion as well as enable the channel selection.

The serial clock mode is selected on the falling edge of
CSADC. To select the external serial clock mode, the serial
clock pin (SCK) must be LOW during each CSADC falling
edge.

The serial data output pin (SDO) is HI-Z as long as CSADC
is HIGH. At any time during the conversion cycle, CSADC
may be pulled LOW in order to monitor the state of the
converter. While CSADC is LOW, EOC is output to the SDO
pin. EOC = 1 while a conversion is in progress and EOC =
0 if the device is in the sleep state. Independent of CSADC,
the device automatically enters the low power sleep state
once the conversion is complete.

While the device is in the sleep state, prior to entering the
data output state, the user may program the multiplexer.
As shown in Figure 13, the multiplexer channel is selected
by serial shifting a 4-bit word into the D

pin on the rising

edge of CLK (CLK is tied to SCK). The first bit is an enable
bit that must be HIGH in order to program a channel. The
next three bits determine which channel is selected, see
Table 3. On the falling edge of CSMUX, the new channel is
selected and will be valid for the first conversion performed
following the data output state. Clock signals applied to the
CLK pin while CSMUX is LOW (during the data output
state) will have no effect on the channel selection. Further-
more, if D

is held LOW or CLK is held LOW during the

sleep state, the channel selection is unchanged.

When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift register.

Table 5. LTC2424/LTC2428 Interface Timing Modes

Conversion

Data

Connection

SCK

Cycle

Output

and

Configuration

Source

Control

Waveforms

External SCK

External

CSADC and SCK

Figures 7, 8, 9

Internal SCK

Internal

CSADC

Figures 10, 11

LTC2424/LTC2428

APPLICATIO

S I

FOR

ATIO

The device remains in the sleep state until the first rising
edge of SCK is seen while CSADC is LOW. Data is shifted
out the SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 24th rising edge of SCK. On the 24th falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.

At the conclusion of the data cycle, CSADC may remain
LOW and EOC monitored as an end-of-conversion inter-
rupt. Alternatively, CSADC may be driven HIGH setting
SDO to HI-Z. As described above, CSADC may be pulled
LOW at any time in order to monitor the conversion status.
For each of these operations, CSMUX may be tied to
CSADC without affecting the selected channel.

At the conclusion of the data output cycle, the converter
enters a user transparent calibration cycle prior to actually
performing a conversion on the selected input channel.
This enables a 66ms (for 60Hz notch frequency) look ahead
time for the multiplexer input. Following the data output
cycle, the multiplexer input channel may be selected any
time in this 66ms window by pulling CSADC HIGH and
serial shifting data into the D

pin, see Figure 14.

While the device is performing the internal calibration, it is
sensitive to ground current disturbances. Error currents
flowing in the ground pin may lead to offset errors. If the
SCK pin is toggling during the calibration, these ground
disturbances will occur. The solution is to either drive the
multiplexer clock input (CLK) separately from the ADC
clock input (SCK), or program the multiplexer in the first
1ms following the data output cycle. The remaining 65ms
may be used to allow the input signal to settle.

Typically, CSADC remains LOW during the data output
state. However, the data output state may be aborted by
pulling CSADC HIGH anytime between the first rising edge
and the 24th falling edge of SCK, see Figure 15. On the
rising edge of CSADC, the device aborts the data output
state and immediately initiates a new conversion. This is
useful for systems not requiring all 24 bits of output data,
aborting an invalid conversion cycle or synchronizing the
start of a conversion.

Internal Serial Clock

This timing mode uses an internal serial clock to shift out
the conversion result and program the multiplexer, see
Figure 16. A CS signal directly drives the CSADC input,
while the inverse of CS drives the CSMUX input. The CS

SCK/CLK

SDO

CSADC/

CSMUX

SET

CSMUX

CSADC

SCK

CLK

MUXOUT

ADCIN

SET

GND

SDO

0.1V

TO V

CH0
TO CH7

0.12V

REF

TO 1.12V

REF

2.7V TO 5.5V

LTC2424/LTC2428

MSB

EXR

SIG

BIT0

LSB

BIT4

BIT19 BIT18

BIT20

BIT21

BIT22

BIT23

24248 F13

= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION

TEST EOC

DON'T CARE

Hi-Z

TEST EOC

Hi-Z

TEST EOC

SCK

Figure 13. External Serial Clock Timing Diagram

LTC2424/LTC2428

Figure 15. External Serial Clock with Reduced Data Output Length Timing Diagram

SCK/CLK

SDO

CSADC/

CSMUX

SCK

SET

CSMUX

CSADC

SCK

CLK

MUXOUT

ADCIN

SET

GND

SDO

0.1V

TO V

CH0
TO CH7

0.12V

REF

TO 1.12V

REF

2.7V TO 5.5V

LTC2424/LTC2428

MSB

EXR

SIG

BIT8

BIT9

BIT19 BIT18

BIT20

BIT21

BIT22

BIT23

24248 F15

= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION

TEST EOC

DON'T CARE

Hi-Z

TEST EOC

APPLICATIO

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FOR

ATIO

signal is used to monitor and control the state of the
conversion cycles as well as enable the channel selection.
The multiplexer is programmed during the data output
state. The internal serial clock (SCK) generated by the ADC
is applied to the multiplexer clock input (CLK).

In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (HI-Z) or pulled
HIGH prior to the falling edge of CSADC. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CSADC. An internal weak pull-up

resistor is active on the SCK pin during the falling edge of
CSADC; therefore, the internal serial clock timing mode is
automatically selected if SCK is not externally driven.

The serial data output pin (SDO) is HI-Z as long as CSADC
is HIGH. At any time during the conversion cycle, CSADC
may be pulled LOW in order to monitor the state of the
converter. Once CSADC is pulled LOW, SCK goes LOW
and EOC is output to the SDO pin. EOC = 1 while a
conversion is in progress and EOC = 0 if the device is in the
sleep state.

Figure 14. Use of Look Ahead to Program Multiplexer After Data Output

SCK/CLK

SDO

CONVERTER

STATE

CSADC/

CSMUX

MSB

EXR

SIG

BIT0

LSB

BIT4

BIT19 BIT18

BIT20

BIT21

BIT22

BIT23

24248 F14

TEST EOC

CONV

SLEEP

DATA OUTPUT

INTERNAL CALIBRATION

66ms LOOK AHEAD

CONVERSION ON SELECTED CHANNEL

DON'T CARE

Hi-Z

TEST EOC

66ms CONVERT

133ms CONVERSION CYCLE (OUTPUT RATE = 7.5Hz)

LTC2424/LTC2428

APPLICATIO

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FOR

ATIO

Figure 16. Internal Serial Clock Timing Diagram

SCKCLK

SDO

CSADC

CSMUX

EOCtest

MSB

LSB

EXR

SIG

BIT0

BIT4 BIT3 BIT2 BIT1

BIT19 BIT18

BIT20

BIT21

BIT22

BIT23

24248 F16

TEST EOC

DON'T CARE

Hi-Z

TEST EOC

10k

SET

CSMUX

CSADC

SCK

CLK

MUXOUT

ADCIN

GND

SET

SDO

0.1V

TO V

CH0
TO CH7

0.12V

REF

TO 1.12V

REF

2.7V TO 5.5V

LTC2424/LTC2428

= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION

When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CSADC remains LOW. In order to prevent the
device from exiting the low power sleep state, CSADC
must be pulled HIGH before the first rising edge of SCK. In
the internal SCK timing mode, SCK goes HIGH and the
device begins outputting data at time t

EOCtest

after the

falling edge of CSADC (if EOC = 0) or t

EOCtest

after EOC

goes LOW (if CSADC is LOW during the falling edge of
EOC). The value of t

EOCtest

is 23

s if the device is using its

internal oscillator (F

= logic LOW or HIGH). If F

is driven

by an external oscillator of frequency f

EOSC

, then t

EOCtest

3.6/f

EOSC

. If CSADC is pulled HIGH before time t

EOCtest

, the

device remains in the sleep state. The conversion result is
held in the internal static shift register.

If CSADC remains LOW longer than t

EOCtest

, the first rising

edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 24th
rising edge. Data is shifted out the SDO pin on each falling

edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.

While operating in the internal serial clock mode, the SCK
output of the ADC may be used as the multiplexer clock
(CLK). D

is latched into the multiplexer on the rising

edge of CLK. As shown in Figure 16, the multiplexer
channel is selected by serial shifting a 4-bit word into the
D

pin on the rising edge of CLK. The first bit is an enable

bit which must be HIGH in order to program a channel. The
next three bits determine which channel is selected, see
Table 3. On the rising edge of CSADC (falling edge of
CSMUX), the new channel is selected and will be valid for
the next conversion. If D

is held LOW during the data

output state, the previous channel selection remains valid.

LTC2424/LTC2428

Figure 17. Internal Serial Clock with Reduced Data Output Length Timing Diagram

SCKCLK

SDO

CSADC

CSMUX

EOCtest

MSB

EXR

SIG

BIT8

BIT12 BIT11 BIT10 BIT9

BIT19 BIT18

BIT20

BIT21

BIT22

BIT23

24248 F17

TEST EOC

DON'T CARE

Hi-Z

TEST EOC

10k

SET

CSMUX

CSADC

SCK

CLK

MUXOUT

ADCIN

GND

SET

SDO

0.1V

TO V

CH0
TO CH7

0.12V

REF

TO 1.12V

REF

2.7V TO 5.5V

LTC2424/LTC2428

= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION

APPLICATIO

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FOR

ATIO

Typically, CSADC remains LOW during the data output
state. However, the data output state may be aborted by
pulling CSADC HIGH anytime between the first and 24th
rising edge of SCK, see Figure 17. On the rising edge of
CSADC, the device aborts the data output state and
immediately initiates a new conversion. This is useful for
systems not requiring all 24 bits of output data, aborting
an invalid conversion cycle, or synchronizing the start of
a conversion. If CSADC is pulled HIGH while the con-
verter is driving SCK LOW, the internal pull-up is not
available to restore SCK to a logic HIGH state. This will
cause the device to exit the internal serial clock mode on
the next falling edge of CSADC. This can be avoided by
adding an external 10k pull-up resistor to the SCK pin or
by never pulling CSADC HIGH when SCK is LOW.

Whenever SCK is LOW, the LTC2424/LTC2428's internal
pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing

mode. However, certain applications may require an exter-
nal driver on SCK. If this driver goes HI-Z after outputting
a LOW signal, the LTC2424/LTC2428's internal pull-up
remains disabled. Hence, SCK remains LOW. On the next
falling edge of CSADC, the device is switched to the
external SCK timing mode. By adding an external 10k pull-
up resistor to SCK, this pin goes HIGH once the external
driver goes HI-Z. On the next CSADC falling edge, the
device will remain in the internal SCK timing mode.

A similar situation may occur during the sleep state when
CSADC is pulsed HIGH-LOW-HIGH in order to test the
conversion status. If the device is in the sleep state
(EOC = 0), SCK will go LOW. Once CSADC goes HIGH
(within the time period defined above as t

EOCtest

), the

internal pull-up is activated. For a heavy capacitive load
on the SCK pin, the internal pull-up may not be adequate
to return SCK to a HIGH level before CSADC goes LOW
again. This is not a concern under normal conditions

LTC2424/LTC2428

APPLICATIO

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FOR

ATIO

where CSADC remains LOW after detecting EOC = 0. This
situation is easily avoided by adding an external 10k pull-
up resistor to the SCK pin.

DIGITAL SIGNAL LEVELS

The LTC2424/LTC2428's digital interface is easy to use.
Its digital inputs (F

, CSADC, CSMUX, CLK, D

and SCK

in External SCK mode of operation) accept standard TTL/
CMOS logic levels and can tolerate edge rates as slow as
100

s. However, some considerations are required to take

advantage of exceptional accuracy and low supply current.

The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.

In order to preserve the accuracy of the LTC2424/LTC2428,
it is very important to minimize the ground path imped-
ance which may appear in series with the input and/or
reference signal and to reduce the current which may flow
through this path. The ZS

SET

pin (Pin 6) should be con-

nected directly to the signal ground.

The power supply current during the conversion state
should be kept to a minimum. This is achieved by restrict-
ing the number of digital signal transitions occurring
during this period.

While a digital input signal is in the 0.5V to (V

0.5V)

range, the CMOS input receiver draws additional current
from the power supply. It should be noted that, when any
one of the digital input signals (F

, CSADC, CSMUX, D

CLK and SCK in External SCK mode of operation) is within
this range, the LTC2424/LTC2428 power supply current
may increase even if the signal in question is at a valid logic
level. For micropower operation and in order to minimize
the potential errors due to additional ground pin current,
it is recommended to drive all digital input signals to full
CMOS levels [V

< 0.4V and V

> (V

0.4V)].

Severe ground pin current disturbances can also occur
due to the undershoot of fast digital input signals. Under-
shoot and overshoot can occur because of the imped-
ance mismatch at the converter pin when the transition
time of an external control signal is less than twice the
propagation delay from the driver to LTC2424/LTC2428.

For reference, on a regular FR-4 board, signal propaga-
tion velocity is approximately 183ps/inch for internal
traces and 170ps/inch for surface traces. Thus, a driver
generating a control signal with a minimum transition
time of 1ns must be connected to the converter pin
through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines
are used and multiple reflections may occur. The solution
is to carefully terminate all transmission lines close to
their characteristic impedance.

Parallel termination near the LTC2424/LTC2428 input
pins will eliminate this problem but will increase the driver
power dissipation. A series resistor between 27

and 56

placed near the driver or near the LTC2424/LTC2428 pin
will also eliminate this problem without additional power
dissipation. The actual resistor value depends upon the
trace impedance and connection topology.

Driving the Input and Reference

The analog input and reference of the typical delta-sigma
analog-to-digital converter are applied to a switched ca-
pacitor network. This network consists of capacitors switch-
ing between the analog input (ADCIN), ZS

SET

(Pin 6) and

the reference (FS

SET

). The result is small current spikes

seen at both ADCIN and V

REF

. A simplified input equivalent

circuit is shown in Figure 18.

The key to understanding the effects of this dynamic input
current is based on a simple first order RC time constant
model. Using the internal oscillator, the internal switched
capacitor network of the LTC2424/LTC2428 is clocked at
153,600Hz corresponding to a 6.5

s sampling period.

Fourteen time constants are required each time a capacitor
is switched in order to achieve 1ppm settling accuracy.

Therefore, the equivalent time constant at V

and V

REF

should be less than 6.5

s/14 = 460ns in order to achieve

1ppm accuracy.

Input Current (V

)

If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. If the
settling is incomplete, it does not degrade the linearity
performance of the device. It simply results in an offset/

LTC2424/LTC2428

APPLICATIO

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FOR

ATIO

full-scale shift, see Figure 19. To simplify the analysis of
input dynamic current, two separate cases are assumed:
large capacitance at V

> 0.01

F) and small capaci-

tance at V

< 0.01

F).

If the total capacitance at V

(see Figure 20) is small

(< 0.01

F), relatively large external source resistances (up

to 20k for 20pF parasitic capacitance) can be tolerated
without any offset/full-scale error.

ANTIALIASING

One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2424/LTC2428 signifi-
cantly simplify antialiasing filter requirements.

The digital filter provides very high rejection except at
integer multiples of the modulator sampling frequency
(f

), see Figure 21. The modulator sampling frequency is

256 · F

, where F

is the notch frequency (typically 50Hz

or 60Hz). The bandwidth of signals not rejected by the
digital filter is narrow (

0.2%) compared to the bandwidth

of the frequencies rejected.

Figure 18. LTC2424/LTC2428 Equivalent Analog Input Circuit

SET

CHX

ADCV

(PIN 2)

AVERAGE INPUT CURRENT:

= 0.25(V

0.5 · V

REF

) · f · C

REF

ADCV

(PIN 2)

IN(LEAK)

MUXV

(PIN 8)

IN(MUX)

1pF (TYP)

SELECTED

CHANNEL

24248 F18

OUT

= 50Hz, INTERNAL OSCILLATOR: f = 128kHz

OUT

= 60Hz, INTERNAL OSCILLATOR: f = 153.6kHz

EXTERNAL OSCILLATOR: 2.56kHz

307.2kHz

SET

ADCIN

MUXOUT

Figure 19. Offset/Full-Scale Shift

Figure 20. An RC Network at CH0 to CH7

TUE

REF

24248 F19

REF

24248 F20

INTPUT

SIGNAL

SOURCE

CH0 TO
CH7

LTC2424/

LTC2428

PAR

20pF

Figure 21. Sync

Filter Rejection

INPUT FREQUENCY

24248 F21

100

120

140

REJECTION (dB)

LTC2424/LTC2428

APPLICATIO

S I

FOR

ATIO

As a result of the oversampling ratio (256) and the digital
filter, minimal (if any) antialias filtering is required in front
of the LTC2424/LTC2428. If passive RC components are
placed in front of the LTC2424/LTC2428, the input dy-
namic current should be considered. In cases where large
effective RC time constants are used, an external buffer
amplifier may be required to minimize the effects of input
dynamic current.

The modulator contained within the LTC2424/LTC2428
can handle large-signal level perturbations without satu-
rating. Signal levels up to 40% of V

REF

do not saturate the

analog modulator. These signals are limited by the input
ESD protection to 300mV below ground and 300mV above
V

The LTC2428's Resolution and Accuracy Allows You
to Measure Points in a Ladder of Sensors

In many industrial processes, for example, cracking tow-
ers in petroleum refineries, a group of temperature mea-
surements must be related to one another. A series of
platinum RTDs that sense slow changing temperatures

can be configured into a resistive ladder, using the LTC2428
to sense each node. This approach allows a single excita-
tion current passed through the entire ladder, reducing
total supply current consumption. In addition, this ap-
proach requires only one high precision resistor, thereby
reducing cost. A group of up to seven temperatures can be
measured as a group by a single LTC2428 in a loop-pow-
ered remote acquisition unit. In the example shown in
Figure 22, the excitation current is 240

A at 0

C. The

LTC2428 requires 300

A, leaving nearly 3.5mA for the

remainder of the remote transmitter.

The resistance of any of the RTDs (PT1 to PT7) is deter-
mined from the voltage across it, as compared to the
voltage drop across the reference resistor (R1). This is a
ratiometric implementation where the voltage drop across
R1 is given by V

REF

CH1

. Channel 7 is used to measure

the voltage on a representative length of wire. If the same
type and length of wire is used for all connections, then
errors associated with the voltage drops across all wiring
can be removed in software. The contribution of wiring
drop can be scaled if wire lengths are not equal.

Figure 22. Measuring Up to Seven RTD Temperatures with One Reference Resistor and One Reference Current

24248 F22

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

8-CHANNEL

MUX

SET

GND

1, 6, 16, 18, 22, 27, 28

CSADC

CSMUX

SCK

CLK

SDO

LTC2428

ADCIN

MUXOUT

0.1

300

OPTIONAL
GAIN
BLOCK

TO PT3-PT6

PT1

100

PLATINUM

RTD

OPTIONAL

PROTECTION

RESISTORS

5k MAX

UP TO SEVERAL
HUNDRED FEET.

ALL SAME

WIRE TYPE

PT2

PT7

R1
20.1k
0.1%

2, 8

SET

LTC1050

LTC1634-2.5

20-BIT

ADC

LTC2424/LTC2428

Gain can be added to this circuit as the total voltage drop
across all the RTDs is small compared to ADC full-scale
range. The maximum recommended gain is 50, as limited
by both amplifier noise contribution, as well as the maxi-
mum voltage developed at CH0 when all sensors are at the
maximum temperature specified for platinum RTDs.

Adding gain requires that one of the resistors (PT1 to PT7)
be a precision resistor in order to eliminate the error asso-
ciated with the gain setting resistors R2 and R3. Note, that
if a precision (100

to 400

) resistor is used in place of

one of the RTDs (PT7 recommended), R1 does not need
to be a high precision resistor. Although the substitution
of a precision reference resistor for an RTD to determine
gain may suggest that R2 and R3 (and R1) need not be
precise, temperature fluctuations due to airflow may ap-
pear as noise that cannot be removed in firmware. Conse-
quently, these resistors should be low temperature coef-
ficient devices. The use of higher resistance RTDs is not
recommended in this topology, although the inclusion of
one 1000

RTD at the top on the ladder will have minimal

impact on the lower elements. The same caveat applies to
fast changing temperatures. Any fast changing sensors
should be at the top of the ladder.

The LTC2428's Uncommitted Multiplexer Finds Use in
a Programmable Gain Scheme

If the multiplexer in the LTC2428 is not committed to
channel selection, it can be used to select various signal-
processing options such as different gains, filters or at-
tenuator characteristics. In Figure 23, the multiplexer is
shown selecting different taps on an R/2R ladder in the
feedback loop of an amplifier. This example allows selec-
tion of gain from 1 to 128 in binary steps. Other feedback
networks could be used to provide gains tailored for
specific purposes. (For example, 1x, 1.1x, 1.41x, 2x,
2.028x, 5x, 10x, 40x, etc.) Alternatively, different bandpass
characteristics or signal inversion/noninversion could be
selected. The R/2R ladder can be purchased as a network
to ensure tight temperature tracking. Alternatively, resis-
tors in a ladder or as separate dividers can be assembled
from discrete resistors. In the configuration shown, the
channel resistance of the multiplexer does not contribute
much to the error budget, as only input op amp current

APPLICATIO

S I

FOR

ATIO

flows through the switch. The LTC1050 was chosen for
its low input current and offset voltage, as well as its
ability to drive the input of a

ADC.

Insert Gain or Buffering After the Multiplexer

Separate MUXOUT and ADCIN terminals permit insertion
of a gain stage between the MUX and the ADC. If passive
filtering is used at the input to the ADC, a buffer amplifier
is strongly recommended to avoid errors resulting from
the dynamic ADC input current. If antialiasing is required,
it should be placed at the input to the MUX. If bandwidth
limiting is required to improve noise performance, a filter
with a 3dB point at 1500Hz will reduce the effective total
noise bandwidth of the system to 15Hz. A roll-off at 1500Hz
eliminates all higher order images of the base bandwidth
of 6Hz. In the example shown, the optional bandwidth-
limiting filter has a 3dB point at 1450Hz. This filter can be
inserted after the multiplexer provided that higher source
impedance prior to the multiplexer does not reduce the
3dB frequency, extending settling time, and resulting in
charge sharing between samples. The settling time of this
filter to 20+ bits of accuracy is less than 2ms. In the pres-
ence of external wideband noise, this filter reduces the
apparent noise by a factor of 5. Note that the noise band-
width for noise developed in the amplifier is 150Hz. In the
example shown, the gain of the amplifier is set to 40, the
point at which amplifier noise gain dominates the LTC2428
noise. Input voltage range as shown is then 0V to 125mV
DC. The recommended capacitor at C2 for a gain of 40
would be 560pF.

An 8-Channel DC-to-Daylight Digitizer

The circuit in Figure 25 shows an example of the LTC2428's
flexibility in digitizing a number of real-world physical
phenomena--from DC voltages to ultraviolet light. All of
the examples implement single-ended signal condition-
ing. Although differential signal conditioning is a pre-
ferred approach in applications where the sensor is a
bridge-type, is located some distance from the ADC or
operates in a high ambient noise environment, the
LTC2428's low power dissipation allows circuit operation
in close proximity to the sensor. As a result, conditioning
the sensor output can be greatly simplified through the

LTC2424/LTC2428

APPLICATIO

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FOR

ATIO

Figure 23. Using the Multiplexer to Produce Programmable Gains of 1 to 128

Figure 24. Inserting Gain Between the Multiplexer and the ADC Input

24248 F23

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

8-CHANNEL

MUX

SET

GND

1, 6, 16, 18, 22, 27, 28

CSADC

CSMUX

SCK

CLK

SDO

LTC2428

ADCIN

MUXOUT

128

AV = 1, 2, 4...128

10k

20k

10k

20k

10k

20k

10k

20k

10k

20k

10k

20k

10k

20k

2, 8

SET

LTC1050

0.1V TO V

20-BIT

ADC

24248 F24

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

8-CHANNEL

MUX

ANALOG

INPUTS

SET

GND

1, 6, 16, 18, 22, 27, 28

CSADC

CSMUX

SCK

CLK

SDO

LTC2428

ADCIN

MUXOUT

C1
0.022

200k

OPTIONAL GAIN

AND ROLL-OFF

OPTIONAL

BANDWIDTH

LIMIT

R2
5.1K

2, 8

SET

R4
5K

MAY BE REQUIRED BY OTHER
AMPLIFIERS (IS REQUIRED BY
BIPOLAR AMPLIFIERS)

5.1k

LTC1050

20-BIT

ADC

LTC2424/LTC2428

use of single-ended arrangements. In those applications
where differential signal conditioning is required, chopper
amplifier-based or self-contained instrumentation ampli-
fiers (also available from LTC) can be used with the
LTC2428.

With the resistor network connected to CH0, the LTC2428
is able to measure DC voltages from 1mV to 1kV in a single
range without the need for autoranging. The 990k resistor
should be a 1W resistor rated for high voltage operation.
Alternatively, the 990k resistor can be replaced with a
series connection of several lower cost, lower power metal
film resistors.

The circuit connected to CH1 shows an LT1793 FET input
operational amplifier used as an electrometer for high
impedance, low frequency applications such as measur-
ing pH. The circuit has been configured for a gain of 21;
thus, the input signal range is 15mV

250mV. An

amplifier circuit is necessary in these applications be-
cause high output impedance sensors cannot drive
switched-capacitor ADCs directly. The LT1793 was cho-
sen for its low input bias current (10pA, max) and low
noise (8nV/

Hz) performance. As shown, the use of a

driven guard (and Teflon

standoffs) is recommended in

high impedance sensor applications; otherwise, PC board
surface leakage current effects can degrade results.

The circuit connected to CH2 illustrates a precision half-
wave rectifier that uses the LTC2428's internal

ADC as

an integrator. This circuit can be used to measure 60Hz,
120Hz or from 400Hz to 1kHz with good results. The
LTC2428's internal sinc

filter effectively eliminates any

frequency in this range. Above 1kHz, limited amplifier
gain-bandwidth product and transient overshoot behavior
can combine to degrade performance. The circuit's dy-
namic range is limited by operational amplifier input offset
voltage and the system's overall noise floor. Using an
LTC1050 chopper-stabilized operational amplifier with a
V

of 5

V, the dynamic range of this application covers

approximately 5 orders of magnitude. The circuit configu-
ration is best implemented with a precision, 3-terminal,
2-resistor 10k

network (for example, an IRC PFC-D

network) for R6 and R7 to maintain gain and temperature
stability. Alternatively, discrete resistors with 0.1% initial

APPLICATIO

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FOR

ATIO

tolerance and 5ppm/

C temperature coefficient would

also be adequate for most applications.

Two channels (CH3 and CH4) of the LTC2428 are used to
accommodate a 3-wire 100

, Pt RTD in a unique circuit

that allows true RMS/RF signal power measurement from
audio to gigahertz (GHz) frequencies. The unique feature
of this circuit is that the signal power dissipated in the 50

termination in the form of heat is measured by the 100

RTD. Two readings are required to compensate for the
RTD's lead-wire resistance. The reading on CH4 is multi-
plied by 2 and subtracted from the reading on CH3 to
determine the exact value of the RTD.

While the LTC2428 is capable of measuring signals over a
range of five decades, the implementation (mechanical,
electrical and thermal) of this technique ultimately deter-
mines the performance of the circuit. The thermal resis-
tance of the assembly (the 50

/RTD mass to its enclosure)

will determine the sensitivity of the circuit. The dynamic
range of the circuit will be determined by the maximum
temperature the assembly is rated to withstand, approxi-
mately 850

C. Details of the implementation are quite

involved and are beyond the scope of this document.
Please contact LTC directly for a more comprehensive
treatment of this implementation.

In the circuit connected to the LTC2428's CH5 input, a
thermistor is configured in a half-bridge arrangement that
could be used to measure the case temperature of the
RTD-based thermal power measurement scheme described
previously. In general, thermistors yield very good resolu-
tion over a limited temperature range. For the half-bridge
arrangement shown, the LTC2428 can measure tempera-
ture changes over nearly 5 orders of magnitude.

Connected to the LTC2428's CH6 input, an infrared ther-
mocouple (Omega Engineering OS36-1) can be used in
limited range, noncontact temperature measurement ap-
plications or applications where high levels of infrared
light must be measured. Given the LTC2428's 1.2ppm

RMS

noise performance, measurement resolution using infra-
red thermocouples is approximately 0.25

C--equivalent

to the resolution of a conventional Type J thermocouple.

Teflon is a trademark of Dupont Company.

LTC2424/LTC2428

APPLICATIO

S I

FOR

ATIO

These infrared thermocouples are self-contained: 1) they
do not require external cold junction compensation; 2)
they cannot use conventional open thermocouple detec-
tion schemes; and 3) their output impedances are high,
approximately 3k

. Alternatively, conventional thermo-

couples can be connected directly to the LTC2428 (not
shown) and cold junction compensation can be provided
by an external temperature sensor connected to a different
channel (see the thermistor circuit on CH5) or by using the
LT1025, a monolithic cold-junction compensator IC.

The components connected to CH7 are used to sense
daylight or photodiode current with a resolution of 300pA.
In the figure, the photodiode is biased in photoconduc-
tive mode; however, the LTC2428 can accommodate
either photovoltaic or photoconductive configurations.

The photodiode chosen (Hammatsu S1336-5BK) pro-
duces an output of 500mA per watt of optical illumination.
The output of the photodiode is dependent on two factors:
active detector area (2.4mm · 2.4mm) and illumination
intensity. With the 5k resistor, optical intensities up to
368W/m

at 960nM (direct sunlight is approximately

1000W/m

) can be measured by the LTC2428. With a

resolution of 1nA, the optical dynamic range covers 5
orders of magnitude.

The application circuits shown connected to the LTC2428
demonstrate the mix-and-match capabilities of this multi-
plexed-input, high resolution

ADC. Very low level

signals and high level signals can be accommodated with
a minimum of additional circuitry.

Dimensions in millimeters (inches) unless otherwise noted.

PACKAGE DESCRIPTIO

G Package

28-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

G28 SSOP 1098

0.13 0.22

(0.005 0.009)

0.55 0.95

(0.022 0.037)

5.20 5.38**

(0.205 0.212)

7.65 7.90

(0.301 0.311)

2 3

6 7 8

9 10 11 12

10.07 10.33*

(0.397 0.407)

22 21 20 19 18 17 16 15

1.73 1.99

(0.068 0.078)

0.05 0.21

(0.002 0.008)

0.65

(0.0256)

BSC

0.25 0.38

(0.010 0.015)

NOTE: DIMENSIONS ARE IN MILLIMETERS
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

LTC2424/LTC2428

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1050

Precision Chopper Stabilized Op Amp

No External Components, 5

V Offset, 1.6

LT1236

Precision Bandgap Reference

0.05% Max Initial Accuracy, 5ppm/

C Drift

LT1461-2.5

Precision, Low Power, Low Drift Reference

A, 0.04%, 3ppm/

C Drift

LT1793

Low Noise JFET Input Op Amp

10pA Max Input Bias Current, Low Voltage Noise: 8nV

LTC2400

24-Bit Micropower

ADC in SO-8

< 4ppm INL, No Missing Codes, 4ppm Full Scale

LTC2404/LTC2408

4/8 Channel, 24-Bit

ADCs

< 4ppm INL, No Missing Codes, Interchangeable with the
LTC2424/LTC2428 if ZS

SET

is grounded

Fiugre 25. Measure DC to Daylight Using the LTC2428

TYPICAL APPLICATIO

LINEAR TECHNOLOGY CORPORATION 2000

24248f LT/TP 0300 4K · PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear-tech.com

24248 F25

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

8-CHANNEL

MUX

SET

GND

1, 6, 16, 18, 22, 27, 28

MPU

SERIAL DATA LINK

MICROWIRE AND

SPI COMPATABLE

LT1236CS8-5

19, 25

CSADC

CSMUX

CLK

SDO

20-BIT

ADC

LTC2428

ADCIN

MUXOUT

2, 8

SET

OUT IN

GND

0V TO 5V

100

INTERNAL OSC
SELECTED FOR
60Hz REJECTION

REF

ELECTROMETER

INPUT

(pH, PIEZO)

GUARD RING

VOLTMETER

INPUT

1mV TO 1000V

R3, 10k

5V
MAX

C1, 0.1

LT1793

LTC1050

10k, 0.1%

5k, 1%

100

, 5%

3-WIRE R-PACK

10k, 0.1%

IN914

INPUT

60Hz

60HzRF

RF POWER

R1
900k
0.1%, 1W, 1000 WVDC

R2
4.7k
0.1%

R13
5k
0.1%

DAYLIGHT

HAMAMATSU
PHOTODIODE
S1336-5BK

100

Pt RTD
(3-WIRE)

FORCE SENSE

INFRARED

THERMOCOUPLE

OMEGA

0S36-01

REF

LOAD

BONDED TO

RTD ON

INSULATED

MOUNTING

R11

24.9k, 0.1%

REF

THERMISTOR
10k

NTC

LOCAL

TEMP

R12

24.9k, 0.1%

R10

60mV TO 4V

2.7V AT 0

0.9V AT 40

2.2mV to 16mV

0V to 4V

20mV TO 80mV

<1mV

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC2424C

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC2424C