1
LTC2483
2483f
R
SOURCE
(
)
1
+FS ERROR (ppm)
20
0
20
1k
100k
40
60
80
10
100
10k
40
60
80
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 3.75V
V
IN
= 1.25V
F
O
= GND
T
A
= 25
C
C
IN
= 1
F
2483 TA02
Direct Sensor Digitizer
Weight Scales
Direct Temperature Measurement
Strain Gauge Transducers
Instrumentation
Industrial Process Control
DVMs and Meters
16-Bit
ADC with Easy Drive
Input Current Cancellation and I
2
C Interface
Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
Directly Digitizes High Impedance Sensors with
Full Accuracy
600nV RMS Noise, Independent of V
REF
GND to V
CC
Input/Reference Common Mode Range
2-Wire I
2
C Interface
Simultaneous 50Hz/60Hz Rejection
2ppm (0.25LSB) INL, No Missing Codes
1ppm Offset and 15ppm Full-Scale Error
No Latency: Digital Filter Settles in a Single Cycle
Single Supply 2.7V to 5.5V Operation
Internal Oscillator
Six Addresses Available and One Global Address for
Synchronization
Available in a Tiny (3mm
3mm) 10-Lead
DFN Package
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
The LTC
2483 combines a 16-bit plus sign No Latency
TM
analog-to-digital converter with patented Easy Drive
TM
tech-
nology and I
2
C digital interface. The patented sampling
scheme eliminates dynamic input current errors and the
shortcomings of on-chip buffering through automatic
cancellation of differential input current. This allows large
external source impedances and input signals, with rail-to-
rail input range to be directly digitized while maintaining
exceptional DC accuracy.
The LTC2483 allows a wide common mode input range
(0V to V
CC
) independent of the reference voltage. The
reference can be as low as 100mV or can be tied directly
to V
CC
. The noise level is 600nV RMS independent of V
REF
.
This allows direct digitization of low level signals with 16-
bit accuracy. The LTC2483 includes an on-chip trimmed
oscillator, eliminating the need for external crystals or
oscillators and provides 87dB rejection of 50Hz and 60Hz
line frequency noise. Absolute accuracy and low drift are
automatically maintained through continuous, transpar-
ent, offset and full-scale calibration.
+FS Error vs R
SOURCE
at IN
+
and IN
LTC2483
V
IN
+
REF
+
V
CC
V
CC
GND
V
IN
1
F
SDA
2-WIRE
I
2
C INTERFACE
1
F
10k
I
DIFF
= 0
10k
CA0/F
0
2483 TA01
CA1
SCL
6 ADDRESSES
REF
SENSE
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency
and Easy Drive are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Patent Pending.
2
LTC2483
2483f
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking:
http://www.linear.com/leadfree/
(Notes 1, 2)
Supply Voltage (V
CC
) to GND ...................... 0.3V to 6V
Analog Input Voltage to GND ....... 0.3V to (V
CC
+ 0.3V)
Reference Input Voltage to GND .. 0.3V to (V
CC
+ 0.3V)
Digital Input Voltage to GND ........ 0.3V to (V
CC
+ 0.3V)
Digital Output Voltage to GND ..... 0.3V to (V
CC
+ 0.3V)
Operating Temperature Range
LTC2483C ................................................... 0
C to 70C
LTC2483I ................................................ 40
C to 85C
Storage Temperature Range ................ 65
C to 125C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
ABSOLUTE AXI U RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
0.1
V
REF
V
CC
, FS
V
IN
+FS (Note 5)
16
Bits
Integral Nonlinearity
5V
V
CC
5.5V, V
REF
= 5V, V
IN(CM)
= 2.5V (Note 6)
2
10
ppm of V
REF
2.7V
V
CC
5.5V, V
REF
= 2.5V, V
IN(CM)
= 1.25V (Note 6)
1
ppm of V
REF
Offset Error
2.5V
V
REF
V
CC
, GND
IN
+
= IN
V
CC
(Note 13)
0.5
2.5
V
Offset Error Drift
2.5V
V
REF
V
CC
, GND
IN
+
= IN
V
CC
10
nV/
C
Positive Full-Scale Error
2.5V
V
REF
V
CC
, IN
+
= 0.75V
REF
, IN
= 0.25V
REF
25
ppm of V
REF
Positive Full-Scale Error Drift
2.5V
V
REF
V
CC
, IN
+
= 0.75V
REF
, IN
= 0.25V
REF
0.1
ppm of
V
REF
/
C
Negative Full-Scale Error
2.5V
V
REF
V
CC
, IN
= 0.75V
REF
, IN
+
= 0.25V
REF
25
ppm of V
REF
Negative Full-Scale Error Drift
2.5V
V
REF
V
CC
, IN
= 0.75V
REF
, IN
+
= 0.25V
REF
0.1
ppm of
V
REF
/
C
Total Unadjusted Error
5V
V
CC
5.5V, V
REF
= 2.5V, V
IN(CM)
= 1.25V (Note 6)
15
ppm of V
REF
5V
V
CC
5.5V, V
REF
= 5V, V
IN(CM)
= 2.5V (Note 6)
15
ppm of V
REF
2.7V
V
CC
5.5V, V
REF
= 2.5V, V
IN(CM)
= 1.25V (Note 6)
15
ppm of V
REF
Output Noise
5V
V
CC
5.5V, V
REF
= 5V, GND
IN
= IN
+
V
CC
(Note 12)
0.6
V
RMS
The
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. (Notes 3, 4)
ELECTRICAL CHARACTERISTICS
LTC2483CDD
LTC2483IDD
TOP VIEW
11
DD PACKAGE
10-LEAD (3mm
3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1
CA0/F
0
CA1
GND
SDA
SCL
REF
+
V
CC
REF
IN
+
IN
ORDER PART NUMBER
DD PART MARKING*
LBSR
T
JMAX
= 125
C,
JA
= 43
C/ W
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
3
LTC2483
2483f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IN
+
Absolute/Common Mode IN
+
Voltage
GND 0.3V
V
CC
+ 0.3V
V
IN
Absolute/Common Mode IN
Voltage
GND 0.3V
V
CC
+ 0.3V
V
FS
Full Scale of the Differential Input (IN
+
IN
)
0.5V
REF
V
LSB
Least Significant Bit of the Output Code
FS/2
16
V
IN
Input Differential Voltage Range (IN
+
IN
)
FS
+FS
V
V
REF
Reference Voltage Range (REF
+
REF
)
0.1
V
CC
V
C
S
(IN
+
)
IN
+
Sampling Capacitance
11
pF
C
S
(IN
)
IN
Sampling Capacitance
11
pF
C
S
(V
REF
)
V
REF
Sampling Capacitance
11
pF
I
DC_LEAK
(IN
+
)
IN
+
DC Leakage Current
Sleep Mode, IN
+
= GND
10
1
10
nA
I
DC_LEAK
(IN
)
IN
DC Leakage Current
Sleep Mode, IN
= GND
10
1
10
nA
I
DC_LEAK
(V
REF
)
REF
+
, REF
DC Leakage Current
Sleep Mode, V
REF
= V
CC
100
1
100
nA
The
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Common Mode Rejection DC
2.5V
V
REF
V
CC
, GND
IN
= IN
+
V
CC
(Note 5)
140
dB
Input Common Mode Rejection
2.5V
V
REF
V
CC
, GND
IN
= IN
+
V
CC
(Note 5)
140
dB
50Hz
2%
Input Common Mode Rejection
2.5V
V
REF
V
CC
, GND
IN
= IN
+
V
CC
(Note 5)
140
dB
60Hz
2%
Input Normal Mode Rejection
2.5V
V
REF
V
CC
, GND
IN
= IN
+
V
CC
(Notes 5, 7)
110
120
dB
50Hz
2%
Input Normal Mode Rejection
2.5V
V
REF
V
CC
, GND
IN
= IN
+
V
CC
(Notes 5, 8)
110
120
dB
60Hz
2%
Input Normal Mode Rejection
2.5V
V
REF
V
CC
, GND
IN
= IN
+
V
CC
(Notes 5, 9)
87
dB
50Hz/60Hz
2%
Reference Common Mode
2.5V
V
REF
V
CC
, GND
IN
= IN
+
V
CC
(Note 5)
120
140
dB
Rejection DC
Power Supply Rejection DC
V
REF
= 2.5V, IN
= IN
+
= GND
120
dB
Power Supply Rejection, 50Hz
2%
V
REF
= 2.5V, IN
= IN
+
= GND (Notes 7, 9)
120
dB
Power Supply Rejection, 60Hz
2%
V
REF
= 2.5V, IN
= IN
+
= GND (Notes 8, 9)
120
dB
CO VERTER CHARACTERISTICS
U
The
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. (Note 3)
A ALOG I PUT A
U
D REFERE CE
U
U
U
4
LTC2483
2483f
The
denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at T
A
= 25
C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
0.7V
CC
V
V
IL
Low Level Input Voltage
0.3V
CC
V
V
IL(CA1)
Low Level Input Voltage for Address Pin
0.05V
CC
V
V
IH(CA0/F0,CA1)
High Level Input Voltage for Address Pins
0.95V
CC
V
R
INH
Resistance from CA0/F
0
,CA1 to V
CC
to Set
10
k
Chip Address Bit to 1
R
INL
Resistance from CA1 to GND to Set
10
k
Chip Address Bit to 0
R
INF
Resistance from CA0/F
0
, CA1 to V
CC
or
2
M
GND to Set Chip Address Bit to Float
I
I
Digital Input Current
10
10
A
V
HYS
Hysteresis of Schmitt Trigger Inputs
(Note 5)
0.05V
CC
V
V
OL
Low Level Output Voltage SDA
I = 3mA
0.4
V
t
OF
Output Fall Time from V
IHMIN
to V
ILMAX
Bus Load C
B
10pF to 400pF (Note 14)
20+0.1C
B
250
ns
t
SP
Input Spike Suppression
50
ns
I
IN
Input Leakage
0.1V
CC
V
IN
V
CC
1
A
C
I
Capacitance for Each I/O Pin
10
pF
C
B
Capacitance Load for Each Bus Line
400
pF
C
CAX
External Capacitive Load on Chip
10
pF
Address Pins (CA0/F
0
,CA1) for Valid Float
V
IH(EXT,OSC)
High Level CA0/F
0
External Oscillator
2.7V
V
CC
< 5.5V
V
CC
0.5V
V
V
IL(EXT,OSC)
Low Level CA0/F
0
External Oscillator
2.7V
V
CC
< 5.5V
0.5
V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
Supply Voltage
2.7
5.5
V
I
CC
Supply Current
Conversion Mode (Note 11)
160
250
A
Sleep Mode (Note 11)
1
2
A
The
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
C. (Note 3)
POWER REQUIRE E TS
W
U
I
2
C DIGITAL I PUTS A D DIGITAL OUTPUTS
U
U
5
LTC2483
2483f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
EOSC
External Oscillator Frequency Range
10
4000
kHz
t
HEO
External Oscillator High Period
0.125
100
s
t
LEO
External Oscillator Low Period
0.125
100
s
t
CONV_1
Conversion Time
Simultaneous 50Hz/60Hz
144.1
146.9
149.9
ms
External Oscillator (Note 10)
41036/f
EOSC
ms
The
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
C. (Note 3)
TI I G CHARACTERISTICS
W
U
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: V
CC
= 2.7V to 5.5V unless otherwise specified.
V
REF
= REF
+
REF
, V
REFCM
= (REF
+
+ REF
)/2, FS
= 0.5V
REF
;
V
IN
= IN
+
IN
, V
INCM
= (IN
+
+ IN
)/2.
Note 4: Use internal conversion clock or external conversion clock source
with f
EOSC
= 307.2kHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: 50Hz f
EOSC
= 256kHz
2% (external oscillator).
Note 8: 60Hz f
EOSC
= 307.2kHz
2% (external oscillator).
Note 9: Simultaneous 50Hz/60Hz (internal oscillator) or f
EOSC
= 280kHz
2% (external oscillator).
Note 10: The external oscillator is connected to the CA0/F
0
pin. The
external oscillator frequency, f
EOSC
, is expressed in kHz.
Note 11: The converter uses the internal oscillator.
Note 12: The output noise includes the contribution of the internal
calibration operations.
Note 13: Guaranteed by design and test correlation.
Note 14: C
B
= capacitance of one bus line in pF.
Note 15: All values refer to V
IH(MIN)
and V
IL(MAX)
levels.
The
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. (Notes 3, 15)
I
2
C TI I G CHARACTERISTICS
U
W
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
SCL
SCL Clock Frequency
0
400
kHz
t
HD(SDA)
Hold Time (Repeated) START Condition
0.6
s
t
LOW
LOW Period of the SCL Clock Pin
1.3
s
t
HIGH
HIGH Period of the SCL Clock Pin
0.6
s
t
SU(STA)
Set-Up Time for a Repeated START Condition
0.6
s
t
HD(DAT)
Data Hold Time
0
0.9
s
t
SU(DAT)
Data Set-Up Time
100
ns
t
r
Rise Time for Both SDA and SCL Signals
(Note 14)
20+0.1C
B
300
ns
t
f
Fall Time for Both SDA and SCL Signals
(Note 14)
20+0.1C
B
300
ns
t
SU(STO)
Set-Up Time for STOP Condition
0.6
s
6
LTC2483
2483f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Total Unadjusted Error
(V
CC
= 5V, V
REF
= 5V)
Total Unadjusted Error
(V
CC
= 5V, V
REF
= 2.5V)
Total Unadjusted Error
(V
CC
= 2.7V, V
REF
= 2.5V)
Integral Nonlinearity
(V
CC
= 5V, V
REF
= 5V)
Integral Nonlinearity
(V
CC
= 5V, V
REF
= 2.5V)
Integral Nonlinearity
(V
CC
= 2.7V, V
REF
= 2.5V)
Noise Histogram (6.8sps)
Long-Term ADC Readings
Noise Histogram (7.5sps)
INPUT VOLTAGE (V)
3
INL (ppm OF V
REF
)
1
1
3
2
0
2
0.75
0.25
0.25
0.75
2483 G03
1.25
1.25
V
CC
= 2.7V
V
REF
= 2.5V
V
IN(CM)
= 1.25V
45
C, 25C, 90C
INPUT VOLTAGE (V)
12
TUE (ppm OF V
REF
)
4
4
12
8
0
8
0.75
0.25
0.25
0.75
2483 G05
1.25
1.25
V
CC
= 5V
V
REF
= 2.5V
V
IN(CM)
= 1.25V
85
C
25
C
45
C
INPUT VOLTAGE (V)
12
TUE (ppm OF V
REF
)
4
4
12
8
0
8
0.75
0.25
0.25
0.75
2483 G06
1.25
1.25
V
CC
= 2.7V
V
REF
= 2.5V
V
IN(CM)
= 1.25V
85
C
25
C
45
C
INPUT VOLTAGE (V)
12
TUE (ppm OF V
REF
)
4
4
12
8
0
8
1.5
0.5
0.5
1.5
2483 G04
2.5
2
2.5
1
0
1
2
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
85
C
25
C
45
C
OUTPUT READING (
V)
3
NUMBER OF READINGS (%)
8
10
12
0.6
2483 G07
6
4
1.8
0.6
2.4
1.2
1.2
0
1.8
2
0
14
10,000 CONSECUTIVE
READINGS
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
T
A
= 25
C
RMS = 0.60
V
AVERAGE = 0.69
V
OUTPUT READING (
V)
3
NUMBER OF READINGS (%)
8
10
12
0.6
2483 G08
6
4
1.8
0.6
2.4
1.2
1.2
0
1.8
2
0
14
10,000 CONSECUTIVE
READINGS
V
CC
= 2.7V
V
REF
= 2.5V
V
IN
= 0V
T
A
= 25
C
RMS = 0.59
V
AVERAGE = 0.19
V
TIME (HOURS)
0
5
ADC READING (
V)
3
1
1
10
20
30
40
2483 G09
50
3
5
4
2
0
2
4
60
V
CC
= 5V, V
REF
= 5V, V
IN
= 0V, V
IN(CM)
= 2.5V
T
A
= 25
C, RMS NOISE = 0.60V
INPUT VOLTAGE (V)
3
INL (ppm OF V
REF
)
1
1
3
2
0
2
1.5
0.5
0.5
1.5
2483 G01
2.5
2
2.5
1
0
1
2
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
85
C
45
C
25
C
INPUT VOLTAGE (V)
3
INL (ppm OF V
REF
)
1
1
3
2
0
2
0.75
0.25
0.25
0.75
2483 G02
1.25
1.25
V
CC
= 5V
V
REF
= 2.5V
V
IN(CM)
= 1.25V
45
C, 25C, 90C
7
LTC2483
2483f
TEMPERATURE (
C)
45
0.3
OFFSET ERROR (ppm OF V
REF
)
0.2
0
0.1
0.2
15
15
30
90
2483 G16
0.1
30
0
45
60
75
0.3
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
V
IN(CM)
= GND
V
CC
(V)
2.7
OFFSET ERROR (ppm OF V
REF
)
0.1
0.2
0.3
3.9
4.7
2483 G17
0
0.1
3.1
3.5
4.3
5.1
5.5
0.2
0.3
REF
+
= 2.5V
REF
= GND
V
IN
= 0V
V
IN(CM)
= GND
T
A
= 25
C
V
REF
(V)
0
0.3
OFFSET ERROR (ppm OF V
REF
)
0.2
0.1
0
0.1
0.2
0.3
1
2
3
4
2483.G18
5
V
CC
= 5V
REF
= GND
V
IN
= 0V
V
IN(CM)
= GND
T
A
= 25
C
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
RMS Noise
vs Input Differential Voltage
RMS Noise vs V
IN(CM)
RMS Noise vs Temperature (T
A
)
RMS Noise vs V
CC
RMS Noise vs V
REF
Offset Error vs V
IN(CM)
Offset Error vs Temperature
Offset Error vs V
CC
Offset Error vs V
REF
INPUT DIFFERENTIAL VOLTAGE (V)
0.4
RMS NOISE (ppm OF V
REF
)
0.6
0.8
1.0
0.5
0.7
0.9
1.5
0.5
0.5
1.5
2483 G10
2.5
2
2.5
1
0
1
2
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
T
A
= 25
C
V
IN(CM)
(V)
1
RMS NOISE (
V)
0.8
0.9
1.0
2
4
2483 G11
0.7
0.6
0
1
3
5
6
0.5
0.4
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
V
IN(CM)
= GND
T
A
= 25
C
TEMPERATURE (
C)
45
0.4
RMS NOISE (
V)
0.5
0.6
0.7
0.8
1.0
30 15
15
0
30
45
60
2483 G12
75
90
0.9
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
V
IN(CM)
= GND
V
CC
(V)
2.7
RMS NOISE (
V)
0.8
0.9
1.0
3.9
4.7
2483 G13
0.7
0.6
3.1
3.5
4.3
5.1
5.5
0.5
0.4
V
REF
= 2.5V
V
IN
= 0V
V
IN(CM)
= GND
T
A
= 25
C
V
REF
(V)
0
0.4
RMS NOISE (
V)
0.5
0.6
0.7
0.8
0.9
1.0
1
2
3
4
2483 G14
5
V
CC
= 5V
V
IN
= 0V
V
IN(CM)
= GND
T
A
= 25
C
V
IN(CM)
(V)
1
OFFSET ERROR (ppm OF V
REF
)
0.1
0.2
0.3
2
4
2483 G15
0
0.1
0
1
3
5
6
0.2
0.3
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
T
A
= 25
C
8
LTC2483
2483f
Conversion Current
vs Output Data Rate
OUTPUT DATA RATE (READINGS/SEC)
0
SUPPLY CURRENT (
A)
500
450
400
350
300
250
200
150
100
80
2483 G28
20
40
60
100
70
10
30
50
90
V
CC
= 5V
V
CC
= 3V
V
REF
= V
CC
IN
+
= GND
IN
= GND
CA0/F
0
= EXT OSC
T
A
= 25
C
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
On-Chip Oscillator Frequency
vs Temperature
On-Chip Oscillator Frequency
vs V
CC
PSRR vs Frequency at V
CC
PSRR vs Frequency at V
CC
Conversion Current
vs Temperature
Sleep Mode Current
vs Temperature
PSRR vs Frequency at V
CC
TEMPERATURE (
C)
45 30
300
FREQUENCY (kHz)
304
310
15
30
45
2483 G21
302
308
306
15
0
60
75
90
V
CC
= 4.1V
V
REF
= 2.5V
V
IN
= 0V
V
IN(CM)
= GND
V
CC
(V)
2.5
300
FREQUENCY (kHz)
302
304
306
308
310
3.0
3.5
4.0
4.5
2483 G22
5.0
5.5
V
REF
= 2.5V
V
IN
= 0V
V
IN(CM)
= GND
FREQUENCY AT V
CC
(Hz)
1
0
20
40
60
80
100
120
140
1k
100k
2483 G23
10
100
10k
1M
REJECTION (dB)
V
CC
= 4.1V DC
V
REF
= 2.5V
IN
+
= GND
IN
= GND
T
A
= 25
C
FREQUENCY AT V
CC
(Hz)
0
140
REJECTION (dB)
120
80
60
40
0
20
100
140
2483 G24
100
20
80
180
220
200
40 60
120
160
V
CC
= 4.1V DC
1.4V
V
REF
= 2.5V
IN
+
= GND
IN
= GND
T
A
= 25
C
TEMPERATURE (
C)
45
100
CONVERSION CURRENT (
A)
120
160
180
200
15
15
30
90
2483 G26
140
30
0
45
60
75
V
CC
= 5V
V
CC
= 2.7V
TEMPERATURE (
C)
45
0
SLEEP MODE CURRENT (
A)
0.2
0.6
0.8
1.0
2.0
1.4
15
15
30
90
2483 G27
0.4
1.6
1.8
1.2
30
0
45
60
75
V
CC
= 5V
V
CC
= 2.7V
FREQUENCY AT V
CC
(Hz)
30600
60
40
0
30750
2483 G25
80
100
30650
30700
30800
120
140
20
REJECTION (dB)
V
CC
= 4.1V DC
0.7V
V
REF
= 2.5V
IN
+
= GND
IN
= GND
T
A
= 25
C
9
LTC2483
2483f
U
U
U
PI FU CTIO S
REF
+
(Pin 1), REF
(Pin 3): Differential Reference Input.
The voltage on these pins can have any value between GND
and V
CC
as long as the reference positive input, REF
+
, is
more positive than the reference negative input, REF
, by
at least 0.1V.
V
CC
(Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 8) with a 1
F tantalum capacitor in parallel with 0.1F
ceramic capacitor as close to the part as possible.
IN
+
(Pin 4), IN
(Pin 5): Differential Analog Input. The
voltage on these pins can have any value between
GND 0.3V and V
CC
+ 0.3V. Within these limits the
converter bipolar input range (V
IN
= IN
+
IN
) extends
from 0.5 V
REF
to 0.5 V
REF
. Outside this input range
the converter produces unique overrange and underrange
output codes.
SCL (Pin 6): Serial Clock Pin of the I
2
C Interface. The
LTC2483 can only act as a slave and the SCL pin only
accepts external serial clock. Data is shifted out the SDA
pin on the falling edges of the SCL clock.
SDA (Pin 7): Serial Data Output Line of the I
2
C Interface.
In the transmitter mode (Read), the conversion result is
output through the SDA pin. It is an open-drain N-channel
driver and therefore an external pull-up resistor or current
source to V
CC
is needed.
GND (Pin 8): Ground. Connect this pin to a ground plane
through a low impedance connection.
CA1 (Pin 9): Chip Address Control Pin. The CA1 pin is
configured as a three state (LOW, HIGH, or Floating)
address control bit for the device I
2
C address.
CA0/F
0
(Pin 10): Chip Address Control Pin/External Clock
Input Pin. When no transition is detected on the CA0/F
0
pin, it is a two state (HIGH or Floating) address control bit
for the device I
2
C address. When the pin is driven by an
external clock signal with a frequency f
EOSC
of at least
10kHz, the converter uses this signal as its system clock
and the fundamental digital filter rejection null is located at
a frequency f
EOSC
/5120 and sets the Chip Address CA0
internally to a HIGH.
10
LTC2483
2483f
U
U
W
FU CTIO AL BLOCK DIAGRA
6
7
4
5
9
10
3RD ORDER
ADC
REF
+
IN
+
IN
+
1
REF
+
IN
IN
REF
I
2
C
SERIAL
INTERFACE
SCL
2
V
CC
3
REF
8
GND
CA0/F
0
2483 FB
SDA
CA1
AUTOCALIBRATION
AND CONTROL
INTERNAL
OSCILLATOR
11
LTC2483
2483f
APPLICATIO S I FOR ATIO
W
U
U
U
Figure 1. LTC2483 State Transition Diagram
CONVERSION
POWER ON RESET
SLEEP
2483 F01
YES
NO
ACKNOWLEDGE
YES
NO
STOP
OR READ
24-BITS
DATA OUTPUT
CONVERTER OPERATION
Converter Operation Cycle
The LTC2483 is a low power,
analog-to-digital con-
verter with an I
2
C interface. After power on reset, its
operation is made up of three states. The converter
operating cycle begins with the conversion, followed by
the low power sleep state and ends with the data output
(see Figure 1).
Initially, the LTC2483 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced
by two orders of magnitude. The part remains in the sleep
state as long as it is not addressed for a read operation.
The conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.
The device will not acknowledge an external request
during the conversion state. After a conversion is finished,
the device is ready to accept a read request. Once the
LTC2483 is addressed for a read operation, the device
begins outputting the conversion result under control of
the serial clock (SCL). There is no latency in the conver-
sion result. The data output is 24 bits long and contains a
16-bit plus sign conversion result. This result is shifted
out on the SDA pin under the control of the SCL. Data is
updated on the falling edges of SCL allowing the user to
reliably latch data on the rising edge of SCL. A new
conversion is initiated at the conclusion of a data read
operation (read out all 24 bits).
I
2
C INTERFACE
The LTC2483 communicates through an I
2
C interface.
The I
2
C interface is a 2-wire open-drain interface sup-
porting multiple devices and masters on a single bus. The
connected devices can only pull the bus wires LOW and
they never drive the bus HIGH. The bus wires are exter-
nally connected to a positive supply voltage via a current-
source or pull-up resistor. When the bus is free, both
lines are HIGH. Data on the I
2
C-bus can be transferred at
rates of up to 100kbit/s in the Standard-mode and up to
400kbit/s in the Fast-mode.
Each device on the I
2
C bus is recognized by a unique
address stored in that device and can operate as either a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be considered as masters or slaves when per-
forming data transfers. A master is the device which
initiates a data transfer on the bus and generates the clock
signals to permit that transfer. At the same time any device
addressed is considered a slave.
The LTC2483 can only be addressed as a slave. Once
addressed, it can transmit the last conversion result.
Therefore the serial clock line SCL is an input only and the
data line SDA is bidirectional (data out/address in). The
device supports the Standard-mode and the Fast-mode
for data transfer speeds up to 400kbit/s. Figure 2 shows
the definition of timing for Fast/Standard-mode devices
on the I
2
C-bus.
12
LTC2483
2483f
SDA
SCL
S
Sr
P
S
t
f
t
LOW
t
HD;STA
t
HD;STA
t
BUF
t
SP
t
SU;STA
t
SU;STO
t
HD;DAT
t
HIGH
t
SU;DAT
t
r
t
r
t
r
2483 F02
APPLICATIO S I FOR ATIO
W
U
U
U
Figure 2. Definition of Timing for F/S-Mode Devices on the I
2
C-Bus
The START and STOP Conditions
A START condition is generated by transitioning SDA from
HIGH to LOW while SCL is HIGH. The bus is considered to
be busy after the START condition. When the data transfer
is finished, a STOP condition is generated by transitioning
SDA from LOW to HIGH while SCL is HIGH. The bus is free
again a certain time after the STOP condition. START and
STOP conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The
repeated START (Sr) conditions are functionally identical
to the START (S).
Data Transferring
After the START condition, the I
2
C bus is busy and data
transfer is set between a master and a slave. Data is
transferred over I
2
C in groups of nine bits (one byte)
followed by an acknowledge bit, therefore each group
takes nine SCL cycles. The transmitter releases the SDA
line during the acknowledge clock pulse and the receiver
issues an Acknowledge (ACK) by pulling SDA LOW or
leaves SDA HIGH to indicate a Not Acknowledge (NAK)
condition. Change of data state can only happen while SCL
is LOW.
13
LTC2483
2483f
APPLICATIO S I FOR ATIO
W
U
U
U
LTC2483 Data Format
After a START condition, the master sends a 7-bit address
followed by a R/W bit. The bit R/W is 1 for a Read request
and 0 for a Write request. If the 7-bit address agrees with
an LTC2483's address, that device is selected. When the
device is in the conversion state, it does not accept the
request and issues a Not-Acknowledge (NAK) by leaving
SDA HIGH. A write operation will also generate an NAK
signal. If the conversion is complete, it issues an acknowl-
edge (ACK) by pulling SDA LOW.
The output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters the sleep state where the supply current is
reduced to 1
A. When the LTC2483 is addressed for a
Read operation, it acknowledges (by pulling SDA LOW)
and acts as a transmitter. The master and receiver can read
up to three bytes from the LTC2483. After a complete Read
operation (3 bytes), the output register is emptied, a new
conversion is initiated, and a following Read request in the
same output phase will be NAKed. The LTC2483 output
data stream is 24 bits long, shifted out on the falling edges
of SCL. The first bit is the conversion result sign bit (SIG),
see Tables 1 and 2. This bit is HIGH if V
IN
0. It is LOW if
V
IN
<0. The second bit is the most significant bit (MSB) of
the result. The first two bits (SIG and MSB) can be used to
indicate over range conditions. If both bits are HIGH, the
differential input voltage is above +FS and the following 16
bits are set to LOW to indicate an overrange condition. If
both bits are LOW, the input voltage is below FS and the
following 16 bits are set to HIGH to indicate an underrange
condition. The function of these two bits is summarized in
Table 1. The next 16 bits contain the conversion results in
binary two's complement format. The remaining six bits
are LOW.
Table 2. LTC2483 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
BIT 23
BIT 22
BIT 21
BIT 20
BIT 19
...
BIT 6
V
IN
*
SIG
MSB
V
IN
*
FS**
1
1
0
0
0
...
0
FS** 1LSB
1
0
1
1
1
...
1
0.5 FS**
1
0
1
0
0
...
0
0.5 FS** 1LSB
1
0
0
1
1
...
1
0
1
0
0
0
0
...
0
1LSB
0
1
1
1
1
...
1
0.5 FS**
0
1
1
0
0
...
0
0.5 FS** 1LSB
0
1
0
1
1
...
1
FS**
0
1
0
0
0
...
0
V
IN
* < FS**
0
0
1
1
1
...
1
*The differential input voltage V
IN
= IN
+
IN
. **The full-scale voltage FS = 0.5 V
REF
.
Table 1. LTC2483 Status Bits
BIT 23
BIT 22
INPUT RANGE
SIG
MSB
V
IN
0.5 V
REF
1
1
0V
V
IN
< 0.5 V
REF
1
0
0.5 V
REF
V
IN
< 0V
0
1
V
IN
< 0.5 V
REF
0
0
As long as the voltage on the IN
+
and IN
pins is main-
tained within the 0.3V to (V
CC
+ 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage
V
IN
from FS = 0.5 V
REF
to +FS
= 0.5 V
REF
. For differential input voltages greater than
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below FS, the conversion result is clamped to the value
corresponding to FS 1LSB.
14
LTC2483
2483f
Initiating a New Conversion
When the LTC2483 finishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device
is ready for a Read operation. After the device acknowl-
edges a Read request, the device exits the sleep state and
enters the data output state. The data output state con-
cludes and the LTC2483 starts a new conversion once a
STOP condition is issued by the master or all 24-bits of
data are read out of the device.
During the data read cycle, a stop command may be issued
by the master controller in order to start a new conversion
and abort the data transfer. This stop command must be
issued during the 9th clock cycle of a byte read when the
bus is free (the ACK/NAK cycle).
LTC2483 Address
The LTC2483 has two address pins, enabling one in 6
possible addresses, as shown in Table 3.
Table 3. LTC2483 Address Assignment
CA1
CA0/F
0
*
Address
LOW
HIGH
001 01 00
LOW
Floating
001 01 01
Floating
HIGH
001 01 11
Floating
Floating
010 01 00
HIGH
HIGH
010 01 10
HIGH
Floating
010 01 11
* CA0/F
0
is treated as HIGH when driven by a valid external clock.
Data Read
The data read operation sequence is shown in Figure 5.
When the conversion is finished, the device may be
addressed for a read operation. At the end of a read
operation, a new conversion begins. At the conclusion
of the conversion cycle, the next result may be read
using the method described above. If the conversion
cycle is not concluded and a valid address selects the
device, the LTC2483 generates a NAK signal indicating
the conversion cycle is in progress.
Easy Drive Input Current Cancellation
The LTC2483 combines a high precision delta-sigma ADC
with an automatic differential input current cancellation
front end. A proprietary front-end passive sampling
network transparently removes the differential input cur-
rent. This enables external RC networks and high imped-
ance sensors to directly interface to the LTC2483 without
external amplifiers. The remaining common mode input
current is eliminated by either balancing the differential
input impedances or setting the common mode input
equal to the common mode reference (see Automatic
Input Current Cancellation section). This unique architec-
ture does not require on-chip buffers enabling input
signals to swing all the way to ground and up to V
CC
.
Furthermore, the cancellation does not interfere with the
transparent offset and full-scale auto-calibration and the
absolute accuracy (full scale + offset + linearity) is main-
tained even with external RC networks.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a SINC or Comb filter). For high
resolution, low frequency applications, this filter is typically
designed to reject line frequencies of 50Hz and 60Hz plus
their harmonics. The filter rejection performance is directly
related to the accuracy of the converter system clock. The
LTC2483 incorporates a highly accurate on-chip oscillator.
This eliminates the need for external frequency setting com-
ponents such as crystals or oscillators.
APPLICATIO S I FOR ATIO
W
U
U
U
15
LTC2483
2483f
SLEEP
DATA OUTPUT
START BY
MASTER
ACK BY
LTC2483
ACK BY
MASTER
NAK BY
MASTER
LSB
R
MSB
SGN
D15
7
...
...
8
9
1
2
9
1
2
3
4
5
6
7
8
9
1
7-BIT
ADDRESS
2483 F03
automatically detects the presence of an external clock
signal at the CA0/F
0
pin and turns off the internal oscilla-
tor. The chip address for CA0 is internally set HIGH. The
frequency f
EOSC
of the external signal must be at least
10kHz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the high and low periods t
HEO
and t
LEO
are observed.
While operating with an external conversion clock of a
frequency f
EOSC
, the LTC2483 provides better than 110dB
APPLICATIO S I FOR ATIO
W
U
U
U
Frequency Rejection Selection (CA0/F
0
)
The LTC2483 internal oscillator provides better than 87dB
normal mode rejection at line frequencies of 50Hz and
60Hz and all of their harmonics (up to the 255th) from
48Hz to 62.4Hz.
When a fundamental rejection frequency different from
50Hz/60Hz is required or when the converter must be
synchronized with an outside source, the LTC2483 can
operate with an external conversion clock. The converter
Figure 4. The LTC2483 Conversion Sequence
7-BIT ADDRESS
CONVERSION
CONVERSION
CONVERSION
SLEEP
SLEEP
DATA OUTPUT
DATA OUTPUT
7-BIT ADDRESS
S
S
R
R
ACK
ACK
READ
READ
P
P
2483 F05
Figure 5. Consecutive Reading at the Same Configuration
Figure 3. Timing Diagram for Reading from the LTC2483
S
ACK
DATA
Sr
DATA TRANSFERRING
P
SLEEP
DATA INPUT/OUTPUT
CONVERSION
7-BIT ADDRESS
R/W
2483 F04
16
LTC2483
2483f
normal mode rejection in a frequency range of f
EOSC
/5120
4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f
EOSC
/5120
is shown in Figure 6.
Ease of Use
The LTC2483 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2483 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to the
user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2483 automatically enters an internal reset state
when the power supply voltage V
CC
drops below approxi-
mately 2V. This feature guarantees the integrity of the conver-
sion result.
When the V
CC
voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 4ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2483 starts a normal conversion cycle and
follows the succession of states described in Figure 1. The
first conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
The LTC2483 external reference voltage range is 0.1V to
V
CC
. The converter output noise is determined by the
APPLICATIO S I FOR ATIO
W
U
U
U
Figure 6. LTC2483 Normal Mode Rejection When
Using an External Oscillator
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
EOSC
/5120(%)
12
8
4
0
4
8
12
NORMAL MODE REJECTION (dB)
2483 F06
80
85
90
95
100
105
110
115
120
125
130
135
140
Whenever an external clock is not present at the CA0/F
0
pin, the converter automatically activates its internal os-
cillator and enters the Internal Conversion Clock mode.
CA0/F
0
may be tied HIGH or left floating in order to set the
chip address. The LTC2483 operation will not be dis-
turbed if the change of conversion clock source occurs
during the sleep state or during the data output state while
the converter uses an external serial clock. If the change
occurs during the conversion state, the result of the
conversion in progress may be outside specifications but
the following conversions will not be affected.
Table 4 summarizes the duration of the conversion state of
each state and the achievable output data rate as a function
of f
EOSC
.
Table 4. LTC2483 State Duration
STATE
OPERATING MODE
DURATION
CONVERSION
Internal Oscillator
50Hz/60Hz Rejection
147ms, Output Data Rate
6.8 Readings/s
External Oscillator
CA0/F
0
= External Oscillator with Frequency
41036/f
EOSC
s, Output Data Rate
f
EOSC
/41036 Readings/s
f
EOSC
Hz (f
EOSC
/5120 Rejection)
17
LTC2483
2483f
APPLICATIO S I FOR ATIO
W
U
U
U
thermal noise of the front-end circuits, and as such, its
value in nanovolts is nearly constant with reference volt-
age. Since the transition noise (600nV) is much less than
the quantization noise (V
REF
/2
17
), a decrease in the refer-
ence voltage will increase the converter resolution. A
reduced reference voltage will also improve the converter
performance when operated with an external conversion
clock (external F
O
signal) at substantially higher output
data rates (see the Output Data Rate section).
The reference input is differential. The differential refer-
ence input range (V
REF
= REF
+
REF
) is 100mV to V
CC
and
the common mode reference input range is 0V to V
CC
.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN
+
and IN
input pins
extending from GND 0.3V to V
CC
+ 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase rapidly.
Within these limits, the LTC2483 converts the bipolar
differential input signal, V
IN
= IN
+
IN
, from FS to +FS
where FS = 0.5 V
REF
. Beyond this range, the converter
indicates the overrange or the underrange condition using
distinct output codes. Since the differential input current
cancellation does not rely on an on-chip buffer, current
cancellation and DC performance is maintained rail-to-rail.
Input signals applied to IN
+
and IN
pins may extend by
300mV below ground and above V
CC
. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN
+
and IN
pins without affecting the perfor-
mance of the devices. The effect of the series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sec-
tions. In addition, series resistors will introduce a tem-
perature dependent offset error due to the input leakage
current. A 1nA input leakage current will develop a 1ppm
offset error on a 5k resistor if V
REF
= 5V. This error has a
very strong temperature dependency.
Driving the Input and Reference
The input and reference pins of the LTC2483 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltage and the differential reference voltage, these capaci-
tors are switching between these four pins transferring
small amounts of charge in the process. A simplified equiva-
lent circuit is shown in Figure 7.
For a simple approximation, the source impedance R
S
driving an analog input pin (IN
+
, IN
, REF
+
or REF
) can be
considered to form, together with R
SW
and C
EQ
(see
Figure 7), a first order passive network with a time constant
= (R
S
+ R
SW
) C
EQ
. The converter is able to sample the
V
REF
+
V
IN
+
V
CC
R
SW
(TYP)
10k
I
LEAK
I
LEAK
V
CC
I
LEAK
I
LEAK
V
CC
R
SW
(TYP)
10k
C
EQ
12pF
(TYP)
R
SW
(TYP)
10k
I
LEAK
I
IN
+
V
IN
I
IN
I
REF
+
I
REF
2483 F07
I
LEAK
V
CC
I
LEAK
I
LEAK
SWITCHING FREQUENCY
f
SW
= 123kHz INTERNAL OSCILLATOR
f
SW
= 0.4 f
EOSC
EXTERNAL OSCILLATOR
V
REF
R
SW
(TYP)
10k
I IN
I IN
V
V
R
I REF
V
V
V
R
V
V
R
V
D
R
V
V
V
R
V
V
R
where
AVG
AVG
IN CM
REF CM
EQ
AVG
REF
INCM
REFCM
EQ
IN
REF
EQ
REF
T
EQ
REF
REF CM
IN CM
EQ
IN
REF
EQ
+
+
REF
+
REF
( )
=
( )
=
-
( )
=
-
+
-
-
+
(
)
(
)
(
)
(
)
(
)
.
.
.
.
.
.
0 5
1 5
0 5
0 5
1 5
0 5
2
2
:
V
V
IN
IN
V
IN
IN
REFCM
IN
INCM
=
=
-
=
+
-
=
=
(
)
+
-
+
-
V
,
REF
=
REF
+
REF
+
2
2
R
2.98M
INTERNAL OSCILLATOR
R
0.833 10
/ f
EXTERNAL OSCILLATOR
D IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT
EQ
EQ
12
EOSC
T
WHERE REF
IS INTERNALLY TIED TO GND
Figure 7. LTC2483 Equivalent Analog Input Circuit
18
LTC2483
2483f
input signal with better than 1ppm accuracy if the sampling
period is at least 14 times greater than the input circuit time
constant
. The sampling process on the four input analog
pins is quasi-independent so each time constant should be
considered by itself and, under worst-case circumstances,
the errors may add.
When using the internal oscillator, the LTC2483's front-
end switched-capacitor network is clocked at 123kHz
corresponding to an 8.1
s sampling period. Thus, for
settling errors of less than 1ppm, the driving source
impedance should be chosen such that
8.1s/14 =
580ns. When an external oscillator of frequency f
EOSC
is
used, the sampling period is 2.5/f
EOSC
and, for a settling
error of less than 1ppm,
0.178/f
EOSC
.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is low
(up to 10k
with no external bypass capacitor or up to
500
with 0.001F bypass), complete settling of the input
occurs. In this case, no errors are introduced and direct
digitization of the sensor is possible.
For many applications, the sensor output impedance com-
bined with external bypass capacitors produces RC time
constants much greater than the 580ns required for 1ppm
accuracy. For example, a 10k
bridge driving a 0.1F
bypass capacitor has a time constant an order of magni-
tude greater than the required maximum. Historically,
settling issues were solved using buffers. These buffers
led to increased noise, reduced DC performance (Offset/
Drift), limited input/output swing (cannot digitize signals
near ground or V
CC
), added system cost and increased
power. The LTC2483 uses a proprietary switching algo-
rithm that forces the average differential input current to
zero independent of external settling errors. This allows
accurate direct digitization of high impedance sensors
without the need of buffers (see Figures 8 to 10). Addi-
tional errors resulting from mismatched leakage currents
must also be taken into account.
The switching algorithm forces the average input current
on the positive input (I
IN
+
) to be equal to the average input
current on the negative input (I
IN
). Over the complete
conversion cycle, the average differential input current
(I
IN
+
I
IN
) is zero. While the differential input current is
APPLICATIO S I FOR ATIO
W
U
U
U
C
EXT
2483 F08
V
INCM
+ 0.5V
IN
R
SOURCE
IN
+
LTC2483
C
PAR
20pF
C
EXT
V
INCM
0.5V
IN
R
SOURCE
IN
C
PAR
20pF
Figure 8. An RC Network at IN
+
and IN
R
SOURCE
(
)
1
+FS ERROR (ppm)
20
0
20
1k
100k
2483 F09
40
60
80
10
100
10k
40
60
80
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 3.75V
V
IN
= 1.25V
T
A
= 25
C
C
EXT
= 0pF
C
EXT
= 100pF
C
EXT
= 1nF, 0.1
F, 1F
Figure 9. +FS Error vs R
SOURCE
at IN
+
and IN
R
SOURCE
(
)
1
FS ERROR (ppm) 20
0
20
1k
100k
2483 F10
40
60
80
10
100
10k
40
60
80
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 1.25V
V
IN
= 3.75V
T
A
= 25
C
C
EXT
= 0pF
C
EXT
= 100pF
C
EXT
= 1nF, 0.1
F, 1F
Figure 10. FS Error vs R
SOURCE
at IN
+
and IN
19
LTC2483
2483f
zero, the common mode input current (I
IN
+
+ I
IN
)/2 is
proportional to the difference between the common mode
input voltage (V
INCM
) and the common mode reference
voltage (V
REFCM
).
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balance bridge type application, both the differ-
ential and common mode input current are zero. The
accuracy of the converter is unaffected by settling errors.
Mismatches in source impedances between IN
+
and IN
also do not affect the accuracy.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between V
INCM
and V
REFCM
. For a reference
common mode of 2.5V and an input common mode of
1.5V, the common mode input current is approximately
0.74
A. This common mode input current has no effect on
the accuracy if the external source impedances tied to IN
+
and IN
are matched. Mismatches in these source imped-
ances lead to a fixed offset error but do not affect the
linearity or full-scale reading. A 1% mismatch in 1k
source resistances leads to a 15ppm shift (74
V) in offset
voltage.
In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the
common mode input current varies proportionally with
input voltage. For the case of balanced input impedances,
the common mode input current effects are rejected by the
large CMRR of the LTC2483 leading to little degradation in
accuracy. Mismatches in source impedances lead to gain
errors proportional to the difference between the common
mode input voltage and the common mode reference
voltage. 1% mismatches in 1k
source resistances lead
to worst-case gain errors on the order of 15ppm or 1LSB
(for 1V differences in reference and input common mode
voltage). Table 5 summarizes the effects of mismatched
source impedance and differences in reference/input com-
mon mode voltages.
APPLICATIO S I FOR ATIO
W
U
U
U
Table 5. Suggested Input Configuration for LTC2483
BALANCED INPUT
UNBALANCED INPUT
RESISTANCES
RESISTANCES
Constant
C
EXT
> 1nF at Both
C
EXT
> 1nF at Both IN
+
V
IN(CM)
V
REF(CM)
IN
+
and IN
. Can Take
and IN
. Can Take Large
Large Source Resistance
Source Resistance.
with Negligible Error
Unbalanced Resistance
Results in an Offset
Which Can be Calibrated
Varying
C
EXT
> 1nF at Both IN
+
Minimize IN
+
and IN
V
IN(CM)
V
REF(CM)
and IN
. Can Take Large
Capacitors and Avoid
Source Resistance with
Large Source Impedance
Negligible Error
(< 5k Recommended)
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/
C) are
used for the external source impedance seen by IN
+
and
IN
, the expected drift of the dynamic current and offset
will be insignificant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (
10nA max), results
in a small offset shift. A 1k source resistance will create a
1
V typical and 10V maximum offset voltage.
Reference Current
In a similar fashion, the LTC2483 samples the differential
reference pins REF
+
and REF
transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can be
analyzed in two distinct situations.
For relatively small values of the external reference capaci-
tors (C
REF
< 1nF), the voltage on the sampling capacitor
settles almost completely and relatively large values for the
source impedance result in only small errors. Such values
for C
REF
will deteriorate the converter offset and gain
20
LTC2483
2483f
APPLICATIO S I FOR ATIO
W
U
U
U
performance without significant benefits of reference filter-
ing and the user is advised to avoid them.
Larger values of reference capacitors (C
REF
> 1nF) may be
required as reference filters in certain configurations. Such
capacitors will average the reference sampling charge and
the external source resistance will see a quasi constant
reference differential impedance.
In the following discussion, it is assumed the input and
reference common mode are the same. For the internal
oscillator, the related difference resistance is 1.1M
and
the resulting full-scale error is 0.46ppm for each ohm of
source resistance driving the REF
+
and REF
pins. When
CA0/F
0
is driven by an external oscillator with a frequency
f
EOSC
(external conversion clock operation), the typical
differential reference resistance is 0.30 10
12
/f
EOSC
and
each ohm of source resistance driving the REF
+
or REF
pins
will result in 1.67 10
6
f
EOSC
ppm gain error. The typical
+FS and FS errors for various combinations of source
resistance seen by the REF
+
or REF
pins and external
capacitance connected to that pin are shown in Figures
11-14.
R
SOURCE
(
)
0
FS ERROR (ppm)
30
10
10
10k
2483 F12
50
70
40
20
0
60
80
90
10
100
1k
100k
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 1.25V
V
IN
= 3.75V
T
A
= 25
C
C
REF
= 0.01
F
C
REF
= 0.001
F
C
REF
= 100pF
C
REF
= 0pF
Figure 12. FS Error vs R
SOURCE
at REF
+
or REF
(Small C
REF
)
R
SOURCE
(
)
0
+FS ERROR (ppm)
50
70
90
10k
2483 F11
30
10
40
60
80
20
0
10
10
100
1k
100k
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 3.75V
V
IN
= 1.25V
T
A
= 25
C
C
REF
= 0.01
F
C
REF
= 0.001
F
C
REF
= 100pF
C
REF
= 0pF
Figure 11. +FS Error vs R
SOURCE
at REF
+
or REF
(Small C
REF
)
Figure 13. +FS Error vs R
SOURCE
at REF
+
or REF
(Large C
REF
)
R
SOURCE
(
)
0
+FS ERROR (ppm)
300
400
500
800
2483 F13
200
100
0
200
400
600
1000
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 3.75V
V
IN
= 1.25V
T
A
= 25
C
C
REF
= 1
F, 10F
C
REF
= 0.1
F
C
REF
= 0.01
F
R
SOURCE
(
)
0
FS ERROR (ppm)
200
100
0
800
2483 F14
300
400
500
200
400
600
1000
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 1.25V
V
IN
= 3.75V
T
A
= 25
C
C
REF
= 1
F, 10F
C
REF
= 0.1
F
C
REF
= 0.01
F
Figure 14. FS Error vs R
SOURCE
at REF
+
or REF
(Large C
REF
)
21
LTC2483
2483f
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
The INL is caused by the input dependent terms
V
IN
2
/(V
REF
R
EQ
) (0.5 V
REF
D
T
)/R
EQ
in the reference
pin current as expressed in Figure 7. When using internal
oscillator, every 100
of reference source resistance
translates into about 0.61ppm additional INL error. When
CA0/F
0
is driven by an external oscillator with a frequency
f
EOSC
, every 100
of source resistance driving REF
+
or
REF
translates into about 2.18 10
6
f
EOSC
ppm addi-
tional INL error. Figure 15 shows the typical INL error due
to the source resistance driving the REF
+
or REF
pins
when large C
REF
values are used. The user is advised to
minimize the source impedance driving the REF
+
and
REF
pins.
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (V
REFCM
V
INCM
) and a 5V reference,
each Ohm of reference source resistance introduces an
extra (V
REFCM
V
INCM
)/(V
REF
R
EQ
) full-scale gain error,
which is 0.067ppm when using internal oscillator. If an
APPLICATIO S I FOR ATIO
W
U
U
U
external clock is used, the corresponding extra gain error
is 0.24 10
6
f
EOSC
ppm.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typically better
than 0.5%. Such a specification can also be easily achieved
by an external clock. When relatively stable resistors
(50ppm/
C) are used for the external source impedance
seen by REF
+
and REF
, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(
10nA max), results in a small gain error. A 100 source
resistance will create a 0.05
V typical and 0.5V maxi-
mum full-scale error.
Figure 15. INL vs DIFFERENTIAL Input Voltage and
Reference Source Resistance for C
REF
> 1
F
V
IN
/V
REF
(V)
0.5
INL (ppm OF V
REF
)
2
6
10
0.3
2483 F15
2
6
0
4
8
4
8
10
0.3
0.1
0.1
0.5
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
T
A
= 25
C
C
REF
= 10
F
R = 1k
R = 100
R = 500
22
LTC2483
2483f
Output Data Rate
When using its internal oscillator, the LTC2483 produces
up to 6.82sps with simultaneous 50Hz/60Hz rejection. The
actual output data rate will depend upon the length of the
sleep and data output phases which are controlled by the
user and which can be made insignificantly short. When
operated with an external conversion clock (CA0/F
0
con-
nected to an external oscillator), the LTC2483 output data
rate can be increased as desired. The duration of the
conversion phase is 41036/f
EOSC
. If f
EOSC
= 307.2kHz, the
converter notch is set at 60Hz.
An increase in f
EOSC
over the nominal 307.2kHz will
translate into a proportional increase in the maximum
APPLICATIO S I FOR ATIO
W
U
U
U
output data rate. The increase in output rate is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
First, a change in f
EOSC
will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent perfor-
mance degradation can be substantially reduced by relying
upon the LTC2483's exceptional common mode rejection
and by carefully eliminating common mode to differential
mode conversion sources in the input circuit. The user
should avoid single-ended input filters and should main-
tain a very high degree of matching and symmetry in the
circuits driving the IN
+
and IN
pins.
OUTPUT DATA RATE (READINGS/SEC)
10
OFFSET ERROR (ppm OF V
REF
)
10
30
50
0
20
40
20
40
60
80
2483 F16
100
10
0
30
50
70
90
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
V
IN
= 0V
CA0/F
0
= EXT CLOCK
T
A
= 85
C
T
A
= 25
C
OUTPUT DATA RATE (READINGS/SEC)
0
0
+FS ERROR (ppm OF V
REF
)
500
1500
2000
2500
3500
10
50
70
2483 F17
1000
3000
40
90 100
20 30
60
80
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
CA0/F
0
= EXT CLOCK
T
A
= 85
C
T
A
= 25
C
Figure 16. Offset Error vs Output Data Rate and Temperature
Figure 17. +FS Error vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
0
3500
FS ERROR (ppm OF V
REF
)
3000
2000
1500
1000
0
10
50
70
2483 F18
2500
500
40
90 100
20 30
60
80
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
CA0/F
0
= EXT CLOCK
T
A
= 85
C
T
A
= 25
C
Figure 18. FS Error vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION (BITS)
12
16
18
20
24
10
50
70
2483 F19
14
22
40
90 100
20 30
60
80
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
V
IN
= 0V
CA0/F
0
= EXT CLOCK
RES = LOG 2 (V
REF
/NOISE
RMS
)
T
A
= 85
C
T
A
= 25
C
Figure 19. Resolution (Noise
RMS
1LSB)
vs Output Data Rate and Temperature
23
LTC2483
2483f
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge trans-
ferred through the input and the reference pins. If large
external input and/or reference capacitors (C
IN
, C
REF
) are
used, the previous section provides formulae for evaluat-
ing the effect of the source resistance upon the converter
performance for any value of f
EOSC
. If small external input
and/or reference capacitors (C
IN
, C
REF
) are used, the
effect of the external source resistance upon the LTC2483
typical performance can be inferred from Figures 9, 10,
11 and 12 in which the horizontal axis is scaled by
307200/f
EOSC
.
APPLICATIO S I FOR ATIO
W
U
U
U
Third, an increase in the frequency of the external oscillator
above 1MHz (a more than 3
+
increase in the output data
rate) will start to decrease the effectiveness of the internal
autocalibration circuits. This will result in a progressive
degradation in the converter accuracy and linearity.
Typical measured performance curves for output data
rates up to 100 readings per second are shown in Fig-
ures 16 to 23. In order to obtain the highest possible level
of accuracy from this converter at output data rates above
20 readings per second, the user is advised to maximize
the power supply voltage used and to limit the maximum
ambient operating temperature. In certain circumstances,
a reduction of the differential reference voltage may
be beneficial.
OUTPUT DATA RATE (READINGS/SEC)
0
10
OFFSET ERROR (ppm OF V
REF
)
5
5
10
20
10
50
70
2483 F21
0
15
40
90 100
20 30
60
80
V
CC
= 5V, V
REF
= 2.5V
V
CC
= V
REF
= 5V
V
IN(CM)
= V
REF(CM)
V
IN
= 0V
CA0/F
0
= EXT CLOCK
T
A
= 25
C
Figure 21. Offset Error vs Output
Data Rate and Reference Voltage
Figure 23. Resolution (INL
MAX
1LSB)
vs Output Data Rate and Reference Voltage
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION (BITS)
12
16
18
22
10
50
70
2483 F23
14
20
40
90 100
20 30
60
80
V
IN(CM)
= V
REF(CM)
V
IN
= 0V
CA0/F
0
= EXT CLOCK
T
A
= 25
C
RES = LOG 2 (V
REF
/INL
MAX
)
V
CC
= 5V, V
REF
= 2.5V
V
CC
= V
REF
= 5V
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION (BITS)
12
16
18
22
10
50
70
2483 F20
14
20
40
90 100
20 30
60
80
T
A
= 85
C
T
A
= 25
C
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
CA0/F
0
= EXT CLOCK
RES = LOG 2 (V
REF
/INL
MAX
)
Figure 20. Resolution (INL
MAX
1LSB)
vs Output Data Rate and Temperature
Figure 22. Resolution (Noise
RMS
1LSB)
vs Output Data Rate and Reference Voltage
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION (BITS)
12
16
18
20
24
10
50
70
2483 F22
14
22
40
90 100
20 30
60
80
V
IN(CM)
= V
REF(CM)
V
IN
= 0V
CA0/F
0
= EXT CLOCK
T
A
= 25
C
RES = LOG 2 (V
REF
/NOISE
RMS
)
V
CC
= 5V, V
REF
= 2.5V
V
CC
= V
REF
= 5V
24
LTC2483
2483f
APPLICATIO S I FOR ATIO
W
U
U
U
Input Bandwidth
The combined effect of the internal SINC
4
digital filter and
of the analog and digital autocalibration circuits deter-
mines the LTC2483 input bandwidth. When the internal
oscillator is used, the 3dB input bandwidth is 3.3Hz. If an
external conversion clock generator of frequency f
EOSC
is
connected to the CA0/F
0
pin, the 3dB input bandwidth is
11.8 10
6
f
EOSC
.
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a first order filter with the pole located
at the 3dB frequency. When the internal oscillator is
used, the shape of the LTC2483 input bandwidth is
shown in Figure 24. When an external oscillator of fre-
quency f
EOSC
is used, the shape of the LTC2483 input
bandwidth can be derived from Figure 24, in which the
horizontal axis is scaled by f
EOSC
/279.2kHz.
The conversion noise (600nV
RMS
typical for V
REF
= 5V) can
be modeled by a white noise source connected to a noise
free converter. The noise spectral density is 47nV
Hz for
an infinite bandwidth source and 64nV
Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in order
to reduce the output referred noise and relatively high
bandwidth (at least 500kHz) necessary to drive the input
switched-capacitor network. A possible solution is a high
gain, low bandwidth amplifier stage followed by a high
bandwidth unity-gain buffer.
When external amplifiers are driving the LTC2483, the
ADC input referred system noise calculation can be
simplified by Figure 25. The noise of an amplifier driving
the LTC2483 input pin can be modeled as a band limited
white noise source. Its bandwidth can be approximated
by the bandwidth of a single pole lowpass filter with a
corner frequency f
i
. The amplifier noise spectral density
is n
i
. From Figure 25, using f
i
as the x-axis selector, we
can find on the y-axis the noise equivalent bandwidth
freq
i
of the input driving amplifier. This bandwidth in-
cludes the band limiting effects of the ADC internal
calibration and filtering. The noise of the driving ampli-
fier referred to the converter input and including all these
effects can be calculated as N = n
i
freq
i
. The total
system noise (referred to the LTC2483 input) can now be
obtained by summing as square root of sum of squares
the three ADC input referred noise sources: the LTC2483
internal noise, the noise of the IN
+
driving amplifier and
the noise of the IN
driving amplifier.
If the CA0/F
0
pin is driven by an external oscillator of
frequency f
EOSC
, Figure 25 can still be used for noise
calculation if the x-axis is scaled by f
EOSC
/307200. For
large values of the ratio f
EOSC
/307200, the Figure 25 plot
accuracy begins to decrease, but at the same time the
LTC2483 noise floor rises and the noise contribution of the
driving amplifiers lose significance.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2483 significantly
simplifies antialiasing filter requirements. Additionally,
the input current cancellation feature of the LTC2483
allows external lowpass filtering without degrading the DC
performance of the device.
The SINC
4
digital filter provides greater than 120dB nor-
mal mode rejection at all frequencies except DC and
integer multiples of the modulator sampling frequency
(f
S
). The LTC2483's autocalibration circuits further sim-
plify the antialiasing requirements by additional normal
mode signal filtering both in the analog and digital domain.
Independent of the operating mode, f
S
= 256 f
N
= 2048
f
OUTMAX
where f
N
is the notch frequency and f
OUTMAX
is
the maximum output data rate. In the internal oscillator
mode, f
S
= 13960Hz. In the external oscillator mode, f
S
=
f
EOSC
/20. The performance of the normal mode rejection
is shown in Figures 26 and 27.
The regions of low rejection occurring at integer multiples
of f
S
have a very narrow bandwidth. Magnified details of
the normal mode rejection curves are shown in Figure 28
(rejection near DC) and Figure 29 (rejection at f
S
= 256f
N
)
where f
N
represents the notch frequency. These curves
have been derived for the external oscillator mode but they
can be used in all operating modes by appropriately
selecting the f
N
value.
25
LTC2483
2483f
APPLICATIO S I FOR ATIO
W
U
U
U
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
INPUT SIGNAL ATTENUATION (dB)
3
2
1
0
4
2483 F24
4
5
6
1
2
3
5
50Hz f
EOSC
= 256kHz
60Hz f
EOSC
= 307.2kHz
INTERNAL
OSCILLATOR
Figure 24. Input Signal Using the Internal Oscillator
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
1
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
10
0.1
1
10
100
1k
10k
100k
1M
2483 F25
0.1
100
Figure 25. Input Refered Noise Equivalent Bandwidth
of an Input Connected White Noise Source
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
f
S
2f
S
3f
S
4f
S
5f
S
6f
S
7f
S
8f
S
9f
S
10f
S
11f
S
12f
S
INPUT NORMAL MODE REJECTION (dB)
2483 F26
0
10
20
30
40
50
60
70
80
90
100
110
120
Figure 26. Input Normal Mode Rejection,
External Oscillator (f
EOSC
= 256kHz)
50Hz Rejection
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
f
S
INPUT NORMAL MODE REJECTION (dB)
2483 F27
0
10
20
30
40
50
60
70
80
90
100
110
120
2f
S
3f
S
4f
S
5f
S
6f
S
7f
S
8f
S
9f
S
10f
S
Figure 27. Input Normal Mode Rejection at DC
(Internal Oscillator)
INPUT SIGNAL FREQUENCY (Hz)
INPUT NORMAL MODE REJECTION (dB)
2483 F28
0
10
20
30
40
50
60
70
80
90
100
110
120
f
N
0
2f
N
3f
N
4f
N
5f
N
6f
N
7f
N
8f
N
f
N
= f
EOSC/5120
INPUT SIGNAL FREQUENCY (Hz)
250f
N
252f
N
254f
N
256f
N
258f
N
260f
N
262f
N
INPUT NORMAL MODE REJECTION (dB)
2483 F29
0
10
20
30
40
50
60
70
80
90
100
110
120
Figure 29. Input Normal Mode Rejection at f
s
= 256f
N
Figure 28. Input Normal Mode Rejection at DC
26
LTC2483
2483f
lator resolves this problem and guarantees a predictable
stable behavior at input signal levels of up to 150% of full
scale. In many industrial applications, it is not uncommon
to have to measure microvolt level signals superimposed
on volt level perturbations and the LTC2483 is eminently
suited for such tasks. When the perturbation is differential,
the specification of interest is the normal mode rejection
for large input signal levels. With a reference voltage
V
REF
= 5V, the LTC2483 has a full-scale differential input
range of 5V peak-to-peak. Figures 33 and 34 show mea-
surement results for the LTC2483 normal mode rejection
ratio with a 7.5V peak-to-peak (150% of full scale) input
signal superimposed over the more traditional normal
mode rejection ratio results obtained with a 5V peak-to-
peak (full scale) input signal. In Figure 33, the LTC2483
uses the external oscillator with the notch set at 60Hz and
in Figure 34 it uses the external oscillator with the notch set
at 50Hz. It is clear that the LTC2483 rejection performance
is maintained with no compromises in this extreme situa-
tion. When operating with large input signal levels, the user
must observe that such signals do not violate the device
absolute maximum ratings.
APPLICATIO S I FOR ATIO
W
U
U
U
The user can expect to achieve this level of performance
using the internal oscillator as it is demonstrated by
Figures 30, 31 and 32. Typical measured values of the
normal mode rejection of the LTC2483 operating with an
external oscillator and a 60Hz notch setting are shown in
Figure 30 superimposed over the theoretical calculated
curve. Similarly, the measured normal rejection of the
LTC2483 for 50Hz rejection (f
EOSC
= 256kHz) and 50Hz/
60Hz rejection (internal oscillator) are shown in Figures 31
and 32.
As a result of these remarkable normal mode specifica-
tions, minimal (if any) antialias filtering is required in front
of the LTC2483. If passive RC components are placed in
front of the LTC2483, the input dynamic current should be
considered (see Input Current section). In this case, the
differential input current cancellation feature of the LTC2483
allows external RC networks without significant degrada-
tion in DC performance.
Traditional high order delta-sigma modulators, while pro-
viding very good linearity and resolution, suffer from
potential instabilities at large input signal levels. The propri-
etary architecture used for the LTC2483 third order modu-
27
LTC2483
2483f
APPLICATIO S I FOR ATIO
W
U
U
U
INPUT FREQUENCY (Hz)
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210 225 240
NORMAL MODE REJECTION (dB)
2483 F30
0
20
40
60
80
100
120
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
V
IN(P-P)
= 5V
T
A
= 25
C
MEASURED DATA
CALCULATED DATA
Figure 30. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale
(60Hz Notch f
EOSC
= 307.2kHz)
Figure 31. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale
(50Hz Notch f
EOSC
= 256kHz)
INPUT FREQUENCY (Hz)
0
12.5
25
37.5
50
62.5
75
87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
NORMAL MODE REJECTION (dB)
2483 F31
0
20
40
60
80
100
120
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
V
IN(P-P)
= 5V
T
A
= 25
C
MEASURED DATA
CALCULATED DATA
Figure 32. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (Internal Oscillator)
INPUT FREQUENCY (Hz)
0
20
40
60
80
100
120
140
160
180
200
220
NORMAL MODE REJECTION (dB)
2483 F32
0
20
40
60
80
100
120
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
V
IN(P-P)
= 5V
T
A
= 25
C
MEASURED DATA
CALCULATED DATA
INPUT FREQUENCY (Hz)
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210 225 240
NORMAL MODE REJECTION (dB)
2483 F33
0
20
40
60
80
100
120
V
CC
= 5V
V
REF
= 5V
V
INCM
= 2.5V
T
A
= 25
C
V
IN(P-P)
= 5V
V
IN(P-P)
= 7.5V
(150% OF FULL SCALE)
Figure 33. Measured Input Normal Mode Rejection vs
Input Frequency with Input Perturbation of 150% Full
Scale (60Hz Notch f
EOSC
= 307.2kHz)
Figure 34. Measured Input Normal Mode Rejection vs
Input Frequency with Input Perturbation of 150% Full
Scale (50Hz Notch f
EOSC
= 256kHz)
INPUT FREQUENCY (Hz)
0
NORMAL MODE REJECTION (dB)
2483 F34
0
20
40
60
80
100
120
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
T
A
= 25
C
V
IN(P-P)
= 5V
V
IN(P-P)
= 7.5V
(150% OF FULL SCALE)
12.5
25
37.5
50
62.5
75
87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
28
LTC2483
2483f
APPLICATIO S I FOR ATIO
W
U
U
U
/*
LTC248X.h
Processor setup and
Lots of useful defines for configuring the LTC2481, LTC2483, and LTC2485.
*/
#include <16F73.h> // Device
#use delay(clock=6000000) // 6MHz clock
//#fuses NOWDT,HS, PUT, NOPROTECT, NOBROWNOUT // Configuration fuses
#rom 0x2007={0x3F3A} // Equivalent and more reliable fuse config.
#use I2C(master, sda=PIN_C5, scl=PIN_C3, SLOW)// Set up i2c port
#include "PCM73A.h" // Various defines
#include "lcd.c" // LCD driver functions
#define READ 0x01 // bitwise OR with address for read or write
#define WRITE 0x00
#define LTC248XADDR 0b01001000 // The one and only LTC248X in this circuit,
// with both address lines floating.
// Useful defines for the LTC2481 and LTC2485 - OR them together to make the
// 8 bit config word.
// These do NOT apply to the LTC2483.
// Select gain - 1 to 256 (also depends on speed setting)
// Does NOT apply to LTC2485.
#define GAIN1 0b00000000 // G = 1 (SPD = 0), G = 1 (SPD = 1)
#define GAIN2 0b00100000 // G = 4 (SPD = 0), G = 2 (SPD = 1)
#define GAIN3 0b01000000 // G = 8 (SPD = 0), G = 4 (SPD = 1)
#define GAIN4 0b01100000 // G = 16 (SPD = 0), G = 8 (SPD = 1)
#define GAIN5 0b10000000 // G = 32 (SPD = 0), G = 16 (SPD = 1)
#define GAIN6 0b10100000 // G = 64 (SPD = 0), G = 32 (SPD = 1)
#define GAIN7 0b11000000 // G = 128 (SPD = 0), G = 64 (SPD = 1)
#define GAIN8 0b11100000 // G = 256 (SPD = 0), G = 128 (SPD = 1)
// Select ADC source - differential input or PTAT circuit
#define VIN 0b00000000
#define PTAT 0b00001000
// Select rejection frequency - 50, 55, or 60Hz
#define R50 0b00000010
#define R55 0b00000000
#define R60 0b00000100
// Select speed mode
#define SLOW 0b00000000 // slow output rate with autozero
#define FAST 0b00000001 // fast output rate with no autozero
29
LTC2483
2483f
/*
LTC2483.c
Basic voltmeter test program for LTC2483
Reads LTC2483, converts result to volts,
and prints voltage to a 2 line by 16 character LCD display.
Mark Thoren
Linear Technonlgy Corporation
June 23, 2005
Written for CCS PCM compiler, Version 3.182
*/
#include "LTC248X.h"
/*** read_LTC2483() ************************************************************
This is the funciton that actually does all the work of talking to the LTC2483.
Arguments: addr - device address
Returns: zero if conversion is in progress,
32 bit signed integer with lower 8 bits clear, 24 bit LTC2483
output word in the upper 24 bits. Data is left-justified for
compatibility with the 24 bit LTC2485.
the i2c_xxxx() functions do the following:
void i2c_start(void): generate an i2c start or repeat start condition
void i2c_stop(void): generate an i2c stop condition
char i2c_read(boolean): return 8 bit i2c data while generating an ack or nack
boolean i2c_write(): send 8 bit i2c data and return ack or nack from slave device
These functions are very compiler specific, and can use either a hardware i2c
port or software emulation of an i2c port. This example uses software emulation.
A good starting point when porting to other processors is to write your own
i2c functions. Note that each processor has its own way of configuring
the i2c port, and different compilers may or may not have built-in functions
for the i2c port.
When in doubt, you can always write a "bit bang" function for troubleshooting
purposes.
The "fourbytes" structure allows byte access to the 32 bit return value:
struct fourbytes // Define structure of four consecutive bytes
{ // To allow byte access to a 32 bit int or float.
int8 te0; //
int8 te1; // The make32() function in this compiler will
int8 te2; // also work, but a union of 4 bytes and a 32 bit int
int8 te3; // is probably more portable.
};
*******************************************************************************/
signed int32 read_LTC2483(char addr)
{
struct fourbytes // Define structure of four consecutive bytes
{ // To allow byte access to a 32 bit int or float.
int8 te0; //
int8 te1; // The make32() function in this compiler will
int8 te2; // also work, but a union of 4 bytes and a 32 bit int
int8 te3; // is probably more portable.
};
APPLICATIO S I FOR ATIO
W
U
U
U
30
LTC2483
2483f
union // adc_code.bits32 all 32 bits
{ // adc_code.by.te0 byte 0
signed int32 bits32; // adc_code.by.te1 byte 1
struct fourbytes by; // adc_code.by.te2 byte 2
} adc_code; // adc_code.by.te3 byte 3
// Start communication with LTC2483:
i2c_start();
if(i2c_write(addr | READ))// If no acknowledge, return zero
{
i2c_stop();
return 0;
}
adc_code.by.te3 = i2c_read();
adc_code.by.te2 = i2c_read();
adc_code.by.te1 = i2c_read();
adc_code.by.te0 = 0;
i2c_stop();
return adc_code.bits32;
} // End of read_LTC2483()
/*** initialize() **************************************************************
Basic hardware initialization of controller and LCD, send Hello message to LCD
*******************************************************************************/
void initialize(void)
{
// General initialization stuff.
setup_adc_ports(NO_ANALOGS);
setup_adc(ADC_OFF);
setup_counters(RTCC_INTERNAL,RTCC_DIV_1);
setup_timer_1(T1_DISABLED);
setup_timer_2(T2_DISABLED,0,1);
// This is the important part - configuring the SPI port
setup_spi(SPI_MASTER|SPI_L_TO_H|SPI_CLK_DIV_16|SPI_SS_DISABLED); // fast SPI clock
CKP = 0; // Set up clock edges - clock idles low, data changes on
CKE = 1; // falling edges, valid on rising edges.
lcd_init(); // Initialize LCD
delay_ms(6);
printf(lcd_putc, "Hello!"); // Obligatory hello message
delay_ms(500); // for half a second
} // End of initialize()
/*** main() ********************************************************************
Main program initializes microcontroller registers, then reads the LTC2483
repeatedly
*******************************************************************************/
void main()
{
signed int32 x; // Integer result from LTC2481
float voltage; // Variable for floating point math
int16 timeout;
initialize(); // Hardware initialization
while(1)
{
delay_ms(1); // Pace the main loop to something more than 1 ms
// This is a basic error detection scheme. The LTC2483 will never take more than
// 149.9ms to complete a conversion in the 55Hz
// rejection mode.
APPLICATIO S I FOR ATIO
W
U
U
U
31
LTC2483
2483f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm
3mm)
(Reference LTC DWG # 05-08-1698)
3.00
0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION
ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SID
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38
0.10
BOTTOM VIEW--EXPOSED PAD
1.65
0.10
(2 SIDES)
0.75
0.05
R = 0.115
TYP
2.38
0.10
(2 SIDES)
1
5
10
6
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 0.05
(DD10) DFN 1103
0.25
0.05
2.38
0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65
0.05
(2 SIDES)
2.15
0.05
0.50
BSC
0.675
0.05
3.50
0.05
PACKAGE
OUTLINE
0.25
0.05
0.50 BSC
// If read_LTC2483() does not return non-zero within this time period, something
// is wrong, such as an incorrect i2c address or bus conflict.
if((x = read_LTC2483(LTC248XADDR)) != 0)
{
// No timeout, everything is okay
timeout = 0; // reset timer
x ^= 0x80000000; // Invert MSB, result is 2's complement
voltage = (float) x; // convert to float
voltage = voltage * 5.0 / 2147483648.0;// Multiply by Vref, divide by 2^31
lcd_putc(`\f'); // Clear screen
lcd_gotoxy(1,1); // Goto home position
printf(lcd_putc, "V %01.4f", voltage); // Display voltage
}
else
{
++timeout;
}
if(timeout > 200)
{
timeout = 200; // Prevent rollover
lcd_gotoxy(1,1);
printf(lcd_putc, "ERROR - TIMEOUT");
delay_ms(500);
}
} // End of main loop
} // End of main()
APPLICATIO S I FOR ATIO
W
U
U
U
32
LTC2483
2483f
LINEAR TECHNOLOGY CORPORATION 2005
LT/LWI/TP 0805 500 PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
TYPICAL APPLICATIO
U
Figure 35. Voltage Measurement Circuit
PART NUMBER
DESCRIPTION
COMMENTS
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max Initial Accuracy, 5ppm/
C Drift
LT1460
Micropower Series Reference
0.075% Max Initial Accuracy, 10ppm/
C Max Drift
LT1790
Micropower SOT-23 Low Dropout Reference Family
0.05% Max Initial Accuracy, 10ppm/
C Max Drift
LTC2400
24-Bit, No Latency
ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200
A
LTC2410
24-Bit, No Latency
ADC with Differential Inputs
0.8
V
RMS
Noise, 2ppm INL
LTC2411/LTC2411-1 24-Bit, No Latency
ADCs with Differential Inputs in MSOP
1.45
V
RMS
Noise, 4ppm INL,
Simultaneous 50Hz/60Hz Rejection (LTC2411-1)
LTC2413
24-Bit, No Latency
ADC with Differential Inputs
Simultaneous 50Hz/60Hz Rejection, 800nV
RMS
Noise
LTC2415/
24-Bit, No Latency
ADCs with 15Hz Output Rate
Pin Compatible with the LTC2410
LTC2415-1
LTC2414/LTC2418
8-/16-Channel 24-Bit, No Latency
ADCs
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200
A
LTC2440
High Speed, Low Noise 24-Bit
ADC
3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs
LTC2480
16-Bit
ADC with Easy Drive Inputs, 600nV Noise,
Pin Compatible with LTC2482/LTC2484
Programmable Gain, and Temperature Sensor
LTC2481
16-Bit
ADC with Easy Drive Inputs, 600nV Noise,
Pin Compatible with LTC2483/LTC2485
I
2
C Interface, Programmable Gain, and Temperature Sensor
LTC2482
16-Bit
ADC with Easy Drive Inputs
Pin Compatible with LTC2480/LTC2484
LTC2484
24-Bit
ADC with Easy Drive Inputs
Pin Compatible with LTC2480/LTC2482
LTC2485
24-Bit
ADC with Easy Drive Inputs, I
2
C Interface and
Pin Compatible with LTC2481/LTC2483
Temperature Sensor
RELATED PARTS
SCL
SDA
CAO/F
O
6
7
10
18
17
16
15
14
13
12
11
28
27
26
25
24
23
22
21
7
6
5
4
3
2
V
CC
5V
LTC2483
REF
REF
IN
IN
+
3
ISOTHERMAL
2
C7
0.1
F
C8
1
F
C6
0.1
F
4
R2
2k
5
TYPE K
THERMOCOUPLE
JACK
(OMEGA MPJ-K-F)
5V
5V
3
8
9
GND
CA1
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RA5
RA4
RA3
RA2
RA1
RA0
V
DD
OSC1
OSC2
MCLR
20
9
10
1
5V
5V
Y1
6MHz
R1
10k
D1
BAT54
V
SS
9
2483 F35
V
SS
19
PIC16F73
D7
D6
D5
D4
EN
RW
RS
R5
10k
R4
10k
R3
10k
R6
5k
2
1
3
2
1
5V
CALIBRATE
CONTRAST
GND D0
V
CC
D1 D2 D3
2
16 CHARACTER
LCD DISPLAY
(OPTREX DMC162488
OR SIMILAR)
DOWN
UP
1.7k
1.7k
PDF 
ZIP