1
LTC2484
2484f
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency and Easy Drive are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Patent pending.
LTC2484
V
REF
V
CC
V
CC
GND
F
O
1F
SDO
4-WIRE
SPI INTERFACE
1F
10k
I
DIFF
= 0
10k
SCK
2484 TA01
CS
SDI
SENSE
V
IN
+
V
IN
Direct Sensor Digitizer
Weight Scales
Direct Temperature Measurement
Strain Gauge Transducers
Instrumentation
Industrial Process Control
DVMs and Meters
Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
Directly Digitizes High Impedance Sensors with
Full Accuracy
600nV RMS Noise
Integrated Temperature Sensor
GND to V
CC
Input/Reference Common Mode Range
Programmable 50Hz, 60Hz or Simultaneous
50Hz/60Hz Rejection Mode
2ppm INL, No Missing Codes
1ppm Offset and 15ppm Total Unadjusted Error
Selectable 2x Speed Mode (15Hz Using Internal
Oscillator)
No Latency: Digital Filter Settles in a Single Cycle
Single Supply 2.7V to 5.5V Operation
Internal Oscillator
Available in a Tiny (3mm 3mm) 10-Lead
DFN Package
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
The LTC
2484 combines a 24-bit No Latency TM analog-
to-digital converter with patented Easy DriveTM technol-
ogy. The patented sampling scheme eliminates dynamic
input current errors and the shortcomings of on-chip
buffering through automatic cancellation of differential
input current. This allows large external source
impedances and input signals with rail-to-rail input range
to be directly digitized while maintaining exceptional
DC accuracy.
The LTC2484 includes an on-chip temperature sensor and
oscillator. The LTC2484 can be configured to measure an
external signal or internal temperature sensor and reject
line frequencies. 50Hz, 60Hz or simultaneous 50Hz/60Hz
line frequency rejection can be selected as well as a 2x
speed-up mode.
The LTC2484 allows a wide common mode input range
(0V to V
CC
) independent of the reference voltage. The
reference can be as low as 100mV or can be tied directly
to V
CC
. The LTC2484 includes an on-chip trimmed oscil-
lator, eliminating the need for external crystals or oscilla-
tors. Absolute accuracy and low drift are automatically
maintained through continuous, transparent, offset and
full-scale calibration.
R
SOURCE
()
1
+FS ERROR (ppm)
20
0
20
1k
100k
2484 TA02
40
60
80
10
100
10k
40
60
80
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 3.75V
V
IN
= 1.25V
F
O
= GND
T
A
= 25C
C
IN
= 1F
+FS Error vs R
SOURCE
at IN
+
and IN
24-Bit ADC with
Easy Drive Input Current Cancellation
2
LTC2484
2484f
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is indicated by a label on the shipping container.
(Notes 1, 2)
Supply Voltage (V
CC
) to GND ...................... 0.3V to 6V
Analog Input Voltage to GND ....... 0.3V to (V
CC
+ 0.3V)
Reference Input Voltage to GND .. 0.3V to (V
CC
+ 0.3V)
Digital Input Voltage to GND ........ 0.3V to (V
CC
+ 0.3V)
Digital Output Voltage to GND ..... 0.3V to (V
CC
+ 0.3V)
Operating Temperature Range
LTC2484C ................................................... 0C to 70C
LTC2484I ................................................ 40C to 85C
Storage Temperature Range ................ 65C to 125C
ABSOLUTE AXI U RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
LTC2484CDD
LTC2484IDD
ORDER PART
NUMBER
DD PART MARKING*
LBSS
T
JMAX
= 125C,
JA
= 43C/ W
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
TOP VIEW
11
DD PACKAGE
10-LEAD (3mm 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1
F
O
SCK
GND
SDO
CS
SDI
V
CC
V
REF
IN
+
IN
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
0.1 V
REF
V
CC
, FS V
IN
+FS (Note 5)
24
Bits
Integral Nonlinearity
5V V
CC
5.5V, V
REF
= 5V, V
IN(CM)
= 2.5V (Note 6)
2
10
ppm of V
REF
2.7V V
CC
5.5V, V
REF
= 2.5V, V
IN(CM)
= 1.25V (Note 6)
1
ppm of V
REF
Offset Error
2.5V V
REF
V
CC
, GND IN
+
= IN
V
CC
(Note 14)
0.5
2.5
V
Offset Error Drift
2.5V V
REF
V
CC
, GND IN
+
= IN
V
CC
10
nV/C
Positive Full-Scale Error
2.5V V
REF
V
CC
, IN
+
= 0.75V
REF
, IN
= 0.25V
REF
25
ppm of V
REF
Positive Full-Scale Error Drift
2.5V V
REF
V
CC
, IN
+
= 0.75V
REF
, IN
= 0.25V
REF
0.1
ppm of
V
REF
/C
Negative Full-Scale Error
2.5V V
REF
V
CC
, IN
+
= 0.75V
REF
, IN
= 0.25V
REF
25
ppm of V
REF
Negative Full-Scale Error Drift
2.5V V
REF
V
CC
, IN
+
= 0.75V
REF
, IN
= 0.25V
REF
0.1
ppm of
V
REF
/C
Total Unadjusted Error
5V V
CC
5.5V, V
REF
= 2.5V, V
IN(CM)
= 1.25V
15
ppm of V
REF
5V V
CC
5.5V, V
REF
= 5V, V
IN(CM)
= 2.5V
ppm of V
REF
2.7V V
CC
5.5V, V
REF
= 2.5V, V
IN(CM)
= 1.25V
ppm of V
REF
Output Noise
5V V
CC
5.5V, V
REF
= 5V, GND IN
= IN
+
V
CC
(Note 13)
0.6
V
RMS
Internal PTAT Signal
T
A
= 27C
420
mV
Internal PTAT Temperature Coefficient
1.4
mV/C
The
denotes specifications which apply
over the full operating temperature range, otherwise specifications are T
A
= 25C. (Notes 3, 4)
ELECTRICAL CHARACTERISTICS ( OR AL SPEED)
U
W
3
LTC2484
2484f
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
0.1 V
REF
V
CC
, FS V
IN
+FS (Note 5)
24
Bits
Integral Nonlinearity
5V V
CC
5.5V, V
REF
= 5V, V
IN(CM)
= 2.5V (Note 6)
2
10
ppm of V
REF
2.7V V
CC
5.5V, V
REF
= 2.5V, V
IN(CM)
= 1.25V (Note 6)
1
Offset Error
2.5V V
REF
V
CC
, GND IN
+
= IN
V
CC
(Note 14)
0.5
2
mV
Offset Error Drift
2.5V V
REF
V
CC
, GND IN
+
= IN
V
CC
100
nV/C
Positive Full-Scale Error
2.5V V
REF
V
CC
, IN
+
= 0.75V
REF
, IN
= 0.25V
REF
25
ppm of V
REF
Positive Full-Scale Error Drift
2.5V V
REF
V
CC
, IN
+
= 0.75V
REF
, IN
= 0.25V
REF
0.1
ppm of
V
REF
/C
Negative Full-Scale Error
2.5V V
REF
V
CC
, IN
+
= 0.75V
REF
, IN
= 0.25V
REF
25
ppm of V
REF
Negative Full-Scale Error Drift
2.5V V
REF
V
CC
, IN
+
= 0.75V
REF
, IN
= 0.25V
REF
0.1
ppm of
V
REF
/C
Output Noise
5V V
CC
5.5V, V
REF
= 5V, GND IN
= IN
+
V
CC
(Note 13)
0.84
V
RMS
The
denotes specifications which apply over the full
operating temperature range, otherwise specifications are T
A
= 25C. (Notes 3, 4)
The
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Common Mode Rejection DC
2.5V V
REF
V
CC
, GND IN
= IN
+
V
CC
(Note 5)
140
dB
Input Common Mode Rejection
2.5V V
REF
V
CC
, GND IN
= IN
+
V
CC
(Note 5)
140
dB
50Hz 2%
Input Common Mode Rejection
2.5V V
REF
V
CC
, GND IN
= IN
+
V
CC
(Note 5)
140
dB
60Hz 2%
Input Normal Mode Rejection
2.5V V
REF
V
CC
, GND IN
= IN
+
V
CC
(Notes 5, 7)
110
120
dB
50Hz 2%
Input Normal Mode Rejection
2.5V V
REF
V
CC
, GND IN
= IN
+
V
CC
(Notes 5, 8)
110
120
dB
60Hz 2%
Input Normal Mode Rejection
2.5V V
REF
V
CC
, GND IN
= IN
+
V
CC
(Notes 5, 9)
87
dB
50Hz/60Hz 2%
Reference Common Mode
2.5V V
REF
V
CC
, GND IN
= IN
+
V
CC
(Note 5)
120
140
dB
Rejection DC
Power Supply Rejection DC
V
REF
= 2.5V, IN
= IN
+
= GND
120
dB
Power Supply Rejection, 50Hz 2%
V
REF
= 2.5V, IN
= IN
+
= GND (Note 7)
120
dB
Power Supply Rejection, 60Hz 2%
V
REF
= 2.5V, IN
= IN
+
= GND (Note 8)
120
dB
CO VERTER CHARACTERISTICS
U
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IN
+
Absolute/Common Mode IN
+
Voltage
GND 0.3V
V
CC
+ 0.3V
V
IN
Absolute/Common Mode IN
Voltage
GND 0.3V
V
CC
+ 0.3V
V
FS
Full Scale of the Differential Input (IN
+
IN
)
0.5V
REF
V
LSB
Least Significant Bit of the Output Code
FS/2
24
V
IN
Input Differential Voltage Range (IN
+
IN
)
FS
+FS
V
V
REF
Reference Voltage Range
0.1
V
CC
V
The
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25C. (Note 3)
A ALOG I PUT A
U
D REFERE CE
U
U
U
ELECTRICAL CHARACTERISTICS (2x SPEED)
4
LTC2484
2484f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
S
(IN
+
)
IN
+
Sampling Capacitance
11
pF
C
S
(IN
)
IN
Sampling Capacitance
11
pF
C
S
(V
REF
)
V
REF
Sampling Capacitance
11
pF
I
DC_LEAK
(IN
+
)
IN
+
DC Leakage Current
Sleep Mode, IN
+
= GND
10
1
10
nA
I
DC_LEAK
(IN
)
IN
DC Leakage Current
Sleep Mode, IN
= GND
10
1
10
nA
I
DC_LEAK
(V
REF
)
V
REF
DC Leakage Current
Sleep Mode, V
REF
= V
CC
100
1
100
nA
The
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25C. (Note 3)
A ALOG I PUT A
U
D REFERE CE
U
U
U
The
denotes specifications which apply over the full
operating temperature range, otherwise specifications are at T
A
= 25C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
IH
High Level Input Voltage
2.7V V
CC
5.5V
V
CC
0.5
V
CS, F
O
, SDI
V
IL
Low Level Input Voltage
2.7V V
CC
5.5V
0.5
V
CS, F
O
, SDI
V
IH
High Level Input Voltage
2.7V V
CC
5.5V (Note 10)
V
CC
0.5
V
SCK
V
IL
Low Level Input Voltage
2.7V V
CC
5.5V (Note 10)
0.5
V
SCK
I
IN
Digital Input Current
0V V
IN
V
CC
10
10
A
CS, F
O
, SDI
I
IN
Digital Input Current
0V V
IN
V
CC
(Note 10)
10
10
A
SCK
C
IN
Digital Input Capacitance
10
pF
CS, F
O
, SDI
C
IN
Digital Input Capacitance
10
pF
SCK
V
OH
High Level Output Voltage
I
O
= 800A
V
CC
0.5
V
SDO
V
OL
Low Level Output Voltage
I
O
= 1.6mA
0.4
V
SDO
V
OH
High Level Output Voltage
I
O
= 800A
V
CC
0.5
V
SCK
V
OL
Low Level Output Voltage
I
O
= 1.6mA
0.4
V
SCK
I
OZ
Hi-Z Output Leakage
10
10
A
SDO
DIGITAL I PUTS A D DIGITAL OUTPUTS
U
U
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
Supply Voltage
2.7
5.5
V
I
CC
Supply Current
Conversion Mode (Note 12)
160
250
A
Sleep Mode (Note 12)
1
2
A
The
denotes specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25C. (Note 3)
POWER REQUIRE E TS
W
U
5
LTC2484
2484f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
EOSC
External Oscillator Frequency Range
(Note 15)
10
4000
kHz
t
HEO
External Oscillator High Period
0.125
100
s
t
LEO
External Oscillator Low Period
0.125
100
s
t
CONV_1
Conversion Time for 1x Speed Mode
50Hz Mode
157.2
160.3
163.5
ms
60Hz Mode
131.0
133.6
136.3
ms
Simultaneous 50Hz/60Hz Mode
144.1
146.9
149.9
ms
External Oscillator
41036/f
EOSC
(in kHz)
ms
t
CONV_2
Conversion Time for 2x Speed Mode
50Hz Mode
78.7
80.3
81.9
ms
60Hz Mode
65.6
66.9
68.2
ms
Simultaneous 50Hz/60Hz Mode
72.2
73.6
75.1
ms
External Oscillator
20556/f
EOSC
(in kHz)
ms
f
ISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
38.4
kHz
External Oscillator (Notes 10, 11)
f
EOSC
/8
kHz
D
ISCK
Internal SCK Duty Cycle
(Note 10)
45
55
%
f
ESCK
External SCK Frequency Range
(Note 10)
4000
kHz
t
LESCK
External SCK Low Period
(Note 10)
125
ns
t
HESCK
External SCK High Period
(Note 10)
125
ns
t
DOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
0.81
0.83
0.85
ms
External Oscillator (Notes 10, 11)
256/f
EOSC
(in kHz)
ms
t
DOUT_ESCK
External SCK 32-Bit Data Output Time
(Note 10)
32/f
ESCK
(in kHz)
ms
t
1
CS to SDO Low
0
200
ns
t2
CS to SDO High Z
0
200
ns
t3
CS to SCK
(Note 10)
0
200
ns
t4
CS to SCK
(Note 10)
50
ns
t
KQMAX
SCK to SDO Valid
200
ns
t
KQMIN
SDO Hold After SCK
(Note 5)
15
ns
t
5
SCK Set-Up Before CS
50
ns
t
6
SCK Hold After CS
50
ns
t
7
SDI Setup Before SCK
(Note 5)
100
ns
t
8
SDI Hold After SCK
(Note 5)
100
ns
The
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25C. (Note 3)
TI I G CHARACTERISTICS
W
U
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: V
CC
= 2.7V to 5.5V unless otherwise specified.
V
REFCM
= V
REF
/2, FS = 0.5V
REF
V
IN
= IN
+
IN
, V
IN(CM)
= (IN
+
+ IN
)/2
Note 4: Use internal conversion clock or external conversion clock source
with f
EOSC
= 307.2kHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: 50Hz mode (internal oscillator) or f
EOSC
= 256kHz 2% (external
oscillator).
Note 8: 60Hz mode (internal oscillator) or f
EOSC
= 307.2kHz 2% (external
oscillator).
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or f
EOSC
=
280kHz 2% (external oscillator).
Note 10: The SCK can be configured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as digital input and the
driving clock is f
ESCK
. In internal SCK mode, the SCK pin is used as digital
output and the output clock signal during the data output is f
ISCK
.
Note 11: The external oscillator is connected to the F
O
pin. The external
oscillator frequency, f
EOSC
, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: Refer to Applications Information section for performance vs
data rate graphs.
6
LTC2484
2484f
INPUT VOLTAGE (V)
3
INL (ppm OF V
REF
)
1
1
3
2
0
2
0.75
0.25
0.25
0.75
2484 G03
1.25
1.25
V
CC
= 2.7V
V
REF
= 2.5V
V
IN(CM)
= 1.25V
F
O
= GND
45C, 25C, 90C
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Total Unadjusted Error
(V
CC
= 5V, V
REF
= 5V)
INPUT VOLTAGE (V)
3
INL (ppm OF V
REF
)
1
1
3
2
0
2
1.5
0.5
0.5
1.5
2484 G01
2.5
2
2.5
1
0
1
2
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
F
O
= GND
85C
45C
25C
INPUT VOLTAGE (V)
3
INL (ppm OF V
REF
)
1
1
3
2
0
2
0.75
0.25
0.25
0.75
2484 G02
1.25
1.25
V
CC
= 5V
V
REF
= 2.5V
V
IN(CM)
= 1.25V
F
O
= GND
45C, 25C, 90C
Total Unadjusted Error
(V
CC
= 5V, V
REF
= 2.5V)
Total Unadjusted Error
(V
CC
= 2.7V, V
REF
= 2.5V)
Integral Nonlinearity
(V
CC
= 5V, V
REF
= 5V)
Integral Nonlinearity
(V
CC
= 5V, V
REF
= 2.5V)
Integral Nonlinearity
(V
CC
= 2.7V, V
REF
= 2.5V)
INPUT VOLTAGE (V)
12
TUE (ppm OF V
REF
)
4
4
12
8
0
8
1.5
0.5
0.5
1.5
2484 G04
2.5
2
2.5
1
0
1
2
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
F
O
= GND
85C
25C
45C
INPUT VOLTAGE (V)
12
TUE (ppm OF V
REF
)
4
4
12
8
0
8
0.75
0.25
0.25
0.75
2484 G05
1.25
1.25
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 1.25V
F
O
= GND
85C
25C
45C
INPUT VOLTAGE (V)
12
TUE (ppm OF V
REF
)
4
4
12
8
0
8
0.75
0.25
0.25
0.75
2484 G06
1.25
1.25
V
CC
= 2.7V
V
REF
= 2.5V
V
IN(CM)
= 1.25V
F
O
= GND
85C
25C
45C
Noise Histogram (6.8sps)
Long-Term ADC Readings
OUTPUT READING (V)
3
NUMBER OF READINGS (%)
8
10
12
0.6
2484 G07
6
4
1.8
0.6
2.4
1.2
1.2
0
1.8
2
0
14
10,000 CONSECUTIVE
READINGS
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
T
A
= 25C
RMS = 0.60V
AVERAGE = 0.69V
Noise Histogram (7.5sps)
OUTPUT READING (V)
3
NUMBER OF READINGS (%)
8
10
12
0.6
2484 G08
6
4
1.8
0.6
2.4
1.2
1.2
0
1.8
2
0
14
10,000 CONSECUTIVE
READINGS
V
CC
= 2.7V
V
REF
= 2.5V
V
IN
= 0V
T
A
= 25C
RMS = 0.59V
AVERAGE = 0.19V
TIME (HOURS)
0
5
ADC READING (
V)
3
1
1
10
20
30
40
2484 G09
50
3
5
4
2
0
2
4
60
V
CC
= 5V, V
REF
= 5V, V
IN
= 0V, V
IN(CM)
= 2.5V
T
A
= 25C, RMS NOISE = 0.60V
7
LTC2484
2484f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
RMS Noise
vs Input Differential Voltage
RMS Noise vs V
IN(CM)
RMS Noise vs Temperature (T
A
)
INPUT DIFFERENTIAL VOLTAGE (V)
0.4
RMS NOISE (ppm OF V
REF
)
0.6
0.8
1.0
0.5
0.7
0.9
1.5
0.5
0.5
1.5
2484 G10
2.5
2
2.5
1
0
1
2
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
T
A
= 25C
V
IN(CM)
(V)
1
RMS NOISE (
V)
0.8
0.9
1.0
2
4
2484 G11
0.7
0.6
0
1
3
5
6
0.5
0.4
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
V
IN(CM)
= GND
T
A
= 25C
TEMPERATURE (C)
45
0.4
RMS NOISE (
V)
0.5
0.6
0.7
0.8
1.0
30 15
15
0
30
45
60
2484 G12
75
90
0.9
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
V
IN(CM)
= GND
RMS Noise vs V
CC
RMS Noise vs V
REF
Offset Error vs V
IN(CM)
V
CC
(V)
2.7
RMS NOISE (
V)
0.8
0.9
1.0
3.9
4.7
2484 G13
0.7
0.6
3.1
3.5
4.3
5.1
5.5
0.5
0.4
V
REF
= 2.5V
V
IN
= 0V
V
IN(CM)
= GND
T
A
= 25C
V
REF
(V)
0
0.4
RMS NOISE (
V)
0.5
0.6
0.7
0.8
0.9
1.0
1
2
3
4
2484 G14
5
V
CC
= 5V
V
IN
= 0V
V
IN(CM)
= GND
T
A
= 25C
V
IN(CM)
(V)
1
OFFSET ERROR (ppm OF V
REF
)
0.1
0.2
0.3
2
4
2484 G15
0
0.1
0
1
3
5
6
0.2
0.3
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
T
A
= 25C
Offset Error vs Temperature
Offset Error vs V
CC
Offset Error vs V
REF
TEMPERATURE (C)
45
0.3
OFFSET ERROR (ppm OF V
REF
)
0.2
0
0.1
0.2
15
15
30
90
2484 G16
0.1
30
0
45
60
75
0.3
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
V
IN(CM)
= GND
F
O
= GND
V
CC
(V)
2.7
OFFSET ERROR (ppm OF V
REF
)
0.1
0.2
0.3
3.9
4.7
2484 G17
0
0.1
3.1
3.5
4.3
5.1
5.5
0.2
0.3
REF
+
= 2.5V
REF
= GND
V
IN
= 0V
V
IN(CM)
= GND
T
A
= 25C
V
REF
(V)
0
0.3
OFFSET ERROR (ppm OF V
REF
)
0.2
0.1
0
0.1
0.2
0.3
1
2
3
4
2484 G18
5
V
CC
= 5V
REF
= GND
V
IN
= 0V
V
IN(CM)
= GND
T
A
= 25C
8
LTC2484
2484f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Temperature Sensor
vs Temperature
TEMPERATURE (C)
60
V
PTAT
/V
REF
(V)
0.35
0.40
120
2484 G19
0.30
0.20
30
0
90
30
60
0.25
V
CC
= 5V
V
REF
= 1.4V
F
O
= GND
Temperature Sensor Error
vs Temperature
TEMPERATURE (C)
60
TEMPERATURE ERROR (
C)
1
3
5
60
2484 G20
1
3
0
2
4
2
4
5
30
0
30
90
120
V
CC
= 5V
F
O
= GND
V
REF
= 1.4V
On-Chip Oscillator Frequency
vs Temperature
TEMPERATURE (C)
45 30
300
FREQUENCY (kHz)
304
310
15
30
45
2484 G21
302
308
306
15
0
60
75
90
V
CC
= 4.1V
V
REF
= 2.5V
V
IN
= 0V
V
IN(CM)
= GND
F
O
= GND
On-Chip Oscillator Frequency
vs V
CC
V
CC
(V)
2.5
300
FREQUENCY (kHz)
302
304
306
308
310
3.0
3.5
4.0
4.5
2484 G22
5.0
5.5
V
REF
= 2.5V
V
IN
= 0V
V
IN(CM)
= GND
F
O
= GND
FREQUENCY AT V
CC
(Hz)
1
0
20
40
60
80
100
120
140
1k
100k
2484 G23
10
100
10k
1M
REJECTION (dB)
V
CC
= 4.1V DC
V
REF
= 2.5V
IN
+
= GND
IN
= GND
F
O
= GND
T
A
= 25C
PSRR vs Frequency at V
CC
FREQUENCY AT V
CC
(Hz)
0
140
REJECTION (dB)
120
80
60
40
0
20
100
140
2484 G24
100
20
80
180
220
200
40 60
120
160
V
CC
= 4.1V DC 1.4V
V
REF
= 2.5V
IN
+
= GND
IN
= GND
F
O
= GND
T
A
= 25C
PSRR vs Frequency at V
CC
FREQUENCY AT V
CC
(Hz)
30600
60
40
0
30750
2484 G25
80
100
30650
30700
30800
120
140
20
REJECTION (dB)
V
CC
= 4.1V DC 0.7V
V
REF
= 2.5V
IN
+
= GND
IN
= GND
F
O
= GND
T
A
= 25C
Conversion Current
vs Temperature
Sleep Mode Current
vs Temperature
TEMPERATURE (C)
45
100
CONVERSION CURRENT (
A)
120
160
180
200
15
15
30
90
2484 G26
140
30
0
45
60
75
V
CC
= 5V
V
CC
= 2.7V
F
O
= GND
CS = GND
SCK = NC
SDO = NC
SDI = GND
TEMPERATURE (C)
45
0
SLEEP MODE CURRENT (
A)
0.2
0.6
0.8
1.0
2.0
1.4
15
15
30
90
2484 G27
0.4
1.6
1.8
1.2
30
0
45
60
75
V
CC
= 5V
V
CC
= 2.7V
F
O
= GND
CS = V
CC
SCK = NC
SDO = NC
SDI = GND
PSRR vs Frequency at V
CC
9
LTC2484
2484f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Conversion Current
vs Output Data Rate
OUTPUT DATA RATE (READINGS/SEC)
0
SUPPLY CURRENT (
A)
500
450
400
350
300
250
200
150
100
80
2484 G28
20
40
60
100
70
10
30
50
90
V
CC
= 5V
V
CC
= 3V
V
REF
= V
CC
IN
+
= GND
IN
= GND
SCK = NC
SDO = NC
SDI = GND
CS GND
F
O
= EXT OSC
T
A
= 25C
Integral Nonlinearity (2x Speed
Mode; V
CC
= 5V, V
REF
= 5V)
INPUT VOLTAGE (V)
3
INL (ppm OF V
REF
)
1
1
3
2
0
2
1.5
0.5
0.5
1.5
2484 G29
2.5
2
2.5
1
0
1
2
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
F
O
= GND
25C, 90C
45C
Integral Nonlinearity (2x Speed
Mode; V
CC
= 5V, V
REF
= 2.5V)
INPUT VOLTAGE (V)
3
INL (ppm OF V
REF
)
1
1
3
2
0
2
0.75
0.25
0.25
0.75
2484 G30
1.25
1.25
V
CC
= 5V
V
REF
= 2.5V
V
IN(CM)
= 1.25V
F
O
= GND
90C
45C, 25C
Integral Nonlinearity (2x Speed
Mode; V
CC
= 2.7V, V
REF
= 2.5V)
INPUT VOLTAGE (V)
3
INL (ppm OF V
REF
)
1
1
3
2
0
2
0.75
0.25
0.25
0.75
2484 G31
1.25
1.25
V
CC
= 2.7V
V
REF
= 2.5V
V
IN(CM)
= 1.25V
F
O
= GND
90C
45C, 25C
Noise Histogram
(2x Speed Mode)
RMS Noise vs V
REF
(2x Speed Mode)
OUTPUT READING (V)
179
NUMBER OF READINGS (%)
8
10
12
186.2
2484 G32
6
4
181.4
183.8
188.6
2
0
16
14
10,000 CONSECUTIVE
READINGS
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
GAIN = 256
T
A
= 25C
RMS = 0.86V
AVERAGE = 0.184mV
V
REF
(V)
0
RMS NOISE (
V)
0.6
0.8
1.0
4
2484 G33
0.4
0.2
0
1
2
3
5
V
CC
= 5V
V
IN
= 0V
V
IN(CM)
= GND
F
O
= GND
T
A
= 25C
Offset Error vs V
IN(CM)
(2x Speed Mode)
V
IN(CM)
(V)
1
180
OFFSET ERROR (
V)
182
186
188
190
200
194
1
3
4
2484 G34
184
196
198
192
0
2
5
6
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
F
O
= GND
T
A
= 25C
Offset Error vs Temperature
(2x Speed Mode)
TEMPERATURE (C)
45
OFFSET ERROR (
V)
200
210
220
75
2484 G35
190
180
160
15
15
45
30
90
0
30
60
170
240
230
V
CC
= 5V
V
REF
= 5V
V
IN
= 0V
V
IN(CM)
= GND
F
O
= GND
10
LTC2484
2484f
SDI (Pin 1): Serial Data Input. This pin is used to select the
line frequency rejection, input, temperature sensor and 2x
speed mode. Data is shifted into the SDI pin on the rising
edge of serial clock (SCK).
V
CC
(Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 8) with a 1F tantalum capacitor in parallel with 0.1F
ceramic capacitor as close to the part as possible.
V
REF
(Pin 3): Positive Reference Input. The voltage on this
pin can have any value between 0.1V and V
CC
. The negative
reference input is GND (Pin 8).
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Offset Error vs V
CC
(2x Speed Mode)
V
CC
(V)
2
2.5
0
OFFSET ERROR (
V)
100
250
3
4
4.5
2484 G36
50
200
150
3.5
5
5.5
V
REF
= 2.5V
V
IN
= 0V
V
IN(CM)
= GND
F
O
= GND
T
A
= 25C
Offset Error vs V
REF
(2x Speed Mode)
V
REF
(V)
0
OFFSET ERROR (
V)
190
200
210
3
5
2484 G37
180
170
160
1
2
4
220
230
240
V
CC
= 5V
V
IN
= 0V
V
IN(CM)
= GND
F
O
= GND
T
A
= 25C
PSRR vs Frequency at V
CC
(2x Speed Mode)
FREQUENCY AT V
CC
(Hz)
1
0
20
40
60
80
100
120
140
1k
100k
2484 G38
10
100
10k
1M
REJECTION (dB)
V
CC
= 4.1V DC
REF
+
= 2.5V
REF
= GND
IN
+
= GND
IN
= GND
F
O
= GND
T
A
= 25C
PSRR vs Frequency at V
CC
(2x Speed Mode)
FREQUENCY AT V
CC
(Hz)
0
140
RREJECTION (dB)
120
80
60
40
0
20
100
140
2484 G39
100
20
80
180
220
200
40 60
120
160
V
CC
= 4.1V DC 1.4V
REF
+
= 2.5V
REF
= GND
IN
+
= GND
IN
= GND
F
O
= GND
T
A
= 25C
PSRR vs Frequency at V
CC
(2x Speed Mode)
FREQUENCY AT V
CC
(Hz)
30600
60
40
0
30750
2484 G40
80
100
30650
30700
30800
120
140
20
REJECTION (dB)
V
CC
= 4.1V DC 0.7V
REF
+
= 2.5V
REF
= GND
IN
+
= GND
IN
= GND
F
O
= GND
T
A
= 25C
U
U
U
PI FU CTIO S
IN
+
(Pin 4), IN
(Pin 5): Differential Analog Inputs.
The voltage on these pins can have any value between GND
0.3V and V
CC
+ 0.3V. Within these limits the converter
bipolar input range (V
IN
= IN
+
IN
) extends from
0.5 V
REF
to 0.5 V
REF
. Outside this input range the
converter produces unique overrange and underrange
output codes.
CS (Pin 6): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as long
11
LTC2484
2484f
1
9
4
5
8
7
6
3RD ORDER
ADC
REF
+
IN
+
IN
+
3
2
V
REF
V
CC
GND
IN
IN
REF
SERIAL
INTERFACE
TEMP
SENSOR
MUX
SDI
CS
2484 FB
SCK
SD0
AUTOCALIBRATION
AND CONTROL
INTERNAL
OSCILLATOR
U
U
U
PI FU CTIO S
as CS is HIGH. A LOW-to-HIGH transition on CS during the
Data Output transfer aborts the data transfer and starts a
new conversion.
SDO (Pin 7): Three-State Digital Output. During the Data
Output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = V
CC
), the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
GND (Pin 8): Ground. Shared pin for analog ground,
digital ground and reference ground. Should be connected
directly to a ground plane through a minimum impedance.
SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
output for the internal serial interface clock during the Data
Input/Output period. In External Serial Clock Operation
mode, SCK is used as the digital input for the external
serial interface clock during the Data Output period. A weak
internal pull-up is automatically activated in Internal Serial
Clock Operation mode. The Serial Clock Operation mode is
determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.
F
O
(Pin 10): Frequency Control Pin. Digital input that
controls the conversion clock. When F
O
is connected to
GND the converter uses its internal oscillator running at
307.2kHz. The conversion clock may also be overridden
by driving the F
O
pin with an external clock in order to
change the output rate or the digital filter rejection null.
Exposed Pad (Pin 11): This pin is ground and should be
soldered to the PCB, GND plane. For prototyping purposes
this pin may remain floating.
U
U
W
FU CTIO AL BLOCK DIAGRA
TEST CIRCUITS
1.69k
SDO
2484 TC01
Hi-Z TO V
OH
V
OL
TO V
OH
V
OH
TO Hi-Z
C
LOAD
= 20pF
1.69k
SDO
2484 TC02
Hi-Z TO V
OL
V
OH
TO V
OL
V
OL
TO Hi-Z
C
LOAD
= 20pF
V
CC
12
LTC2484
2484f
CS
SDO
SCK
SDI
t
1
t
3
t
7
t
8
SLEEP
t
KQMAX
CONVERSION
DATA IN/OUT
t
KQMIN
t
2
2484 TD1
TI I G DIAGRA S
W
U
W
Timing Diagram Using Internal SCK
APPLICATIO S I FOR ATIO
W
U
U
U
Timing Diagram Using External SCK
CS
SDO
SCK
SDI
t
1
t
5
t
6
t
4
t
7
t
8
SLEEP
t
KQMAX
CONVERSION
DATA IN/OUT
t
KQMIN
t
2
2484 TD2
CONVERTER OPERATION
Converter Operation Cycle
The LTC2484 is a low power, delta-sigma analog-to-
digital converter with an easy to use 4-wire serial interface
and automatic differential input current cancellation. Its
operation is made up of three states. The converter oper-
ating cycle begins with the conversion, followed by the low
power sleep state and ends with the data output (see
Figure 1). The 4-wire interface consists of serial data
output (SDO), serial clock (SCK), chip select (CS) and
serial data input (SDI).
Initially, the LTC2484 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
CONVERT
SLEEP
DATA OUTPUT
CONFIGURATION INPUT
2484 F01
TRUE
FALSE CS = LOW
AND
SCK
Figure 1. LTC2484 State Transition Diagram
13
LTC2484
2484f
APPLICATIO S I FOR ATIO
W
U
U
U
While in this sleep state, power consumption is reduced by
two orders of magnitude. The part remains in the sleep
state as long as CS is HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
after the first rising edge of SCK, the device begins
outputting the conversion result. Taking CS high at this
point will terminate the data input and output state and
start a new conversion. The conversion result is shifted
out of the device through the serial data output pin (SDO)
on the falling edge of the serial clock (SCK) (see Figure 2).
The LTC2484 includes a serial data input pin (SDI) in
which data is latched by the device on the rising edge of
SCK (Figure 2). The bit stream applied to this pin can be
used to select various features of the LTC2484, including
an on-chip temperature sensor, line frequency rejection
and output data rate. Alternatively, this pin may be tied to
ground and the part will perform conversions in a default
state. In the default state (SDI grounded) the device simply
performs conversions on the user applied input with
simultaneous rejection of 50Hz and 60Hz line frequencies.
Through timing control of the CS and SCK pins, the
LTC2484 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
Easy Drive Input Current Cancellation
The LTC2484 combines a high precision delta-sigma ADC
with an automatic differential input current cancellation
front end. A proprietary front-end passive sampling
network transparently removes the differential input cur-
rent. This enables external RC networks and high imped-
ance sensors to directly interface to the LTC2484 without
external amplifiers. The remaining common mode input
current is eliminated by either balancing the differential
input impedances or setting the common mode input
equal to the common mode reference (see Automatic
Input Current Cancellation section). This unique architec-
ture does not require on-chip buffers enabling input sig-
nals to swing all the way to ground and up to V
CC
.
Furthermore, the cancellation does not interfere with the
transparent offset and full-scale autocalibration and the
absolute accuracy (full scale + offset + linearity) is main-
tained with external RC networks.
Accessing the Special Features of the LTC2484
The LTC2484 combines a high resolution, low noise
analog-to-digital converter with an on-chip selectable tem-
perature sensor, programmable digital filter and output
rate control. These special features are selected through a
single 8-bit serial input word during the data input/output
cycle (see Figure 2).
The LTC2484 powers up in a default mode commonly
used for most measurements. The device will remain in
this mode as long as the serial data input (SDI) is low. In
this default mode, the measured input is external, the
digital filter simultaneously rejects 50Hz and 60Hz line
frequency noise, and the speed mode is 1x (offset auto-
matically, continuously calibrated).
A simple serial interface grants access to any or all special
functions contained within the LTC2484. In order to
change the mode of operation, an enable bit (EN) followed
by up to 7 bits of data are shifted into the device
(see Table 1). The first 3 bits, in order to remain pin
compatible with the LTC2480, are DON'T CARE and can
be either HIGH or LOW. The 4th bit (IM) is used to select
the internal temperature sensor as the conversion input,
while the 5th and 6th bits (FA, FB) combine to determine
the line frequency rejection mode. The 7th bit (SPD) is
used to double the output rate by disabling the offset auto
calibration.
14
LTC2484
2484f
EN
2484 TBL1
IM FoA FoB
SPD
Comments
Keep Previous Mode
External Input, 50Hz and 60Hz Rejection, Autocalibration
External Input, 50Hz Rejection, Autocalibration
External Input, 60Hz Rejection, Autocalibration
External Input, 50Hz and 60Hz Rejection, 2x Speed
External Input, 50Hz Rejection, 2x Speed
External Input, 60Hz Rejection, 2x Speed
Temperature Input, 50Hz and 60Hz Rejection, Autocalibration
Temperature Input, 50Hz Rejection, Autocalibration
Temperature Input, 60Hz Rejection, Autocalibration
Reserved, Do Not Use
0
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
0
1
1
1
X
X
0
0
0
1
1
1
X
X
X
X
X
0
1
0
0
1
0
0
1
0
1
X
0
0
1
0
0
1
0
0
1
1
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Table 1. Selecting Special Modes
Figure 2. Input/Output Data Timing
CS
SDO
Hi-Z
SIG
DMY
BIT 29
MSB
CONVERSION RESULT
BIT 28
BIT 27
BIT 26
LSB24
BIT 4
BIT 5
BIT 3
BIT 1
BIT 0
BIT 2
BIT 30
SCK
SDI
SLEEP
DATA INPUT/OUTPUT
BIT 31
EOC
EN
DON'T CARE
IM
FOB
FOA
SPD
DON'T CARE
CONVERSION
2484 F02
SUB LSBs
15
LTC2484
2484f
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Temperature Sensor (IM)
The LTC2484 includes an on-chip temperature sensor. The
temperature sensor is selected by setting IM = 1 in the serial
input data stream. Conversions are performed directly on
the temperature sensor by the converter. While operating
in this mode, the device behaves as a temperature to bits
converter. The digital reading is proportional to the
absolute temperature of the device. This feature allows the
converter to linearize temperature sensors or continuously
remove temperature effects from external sensors. Several
applications leveraging this feature are presented in more
detail in the applications section. While operating in
this mode, the speed is set to normal independent of
control bit SPD.
Rejection Mode (FA, FB)
The LTC2484 includes a high accuracy on-chip oscillator
with no required external components. Coupled with a 4th
order digital lowpass filter, the LTC2484 rejects line fre-
quency noise. In the default mode, the LTC2484 simulta-
neously rejects 50Hz and 60Hz by at least 87dB. The
LTC2484 can also be configured to selectively reject 50Hz
or 60Hz to better than 110dB.
Speed Mode (SPD)
The LTC2484 continuously performs offset calibrations.
Every conversion cycle, two conversions are automati-
cally performed (default) and the results combined. This
result is free from offset and drift. In applications where
the offset is not critical, the autocalibration feature can be
disabled with the benefit of twice the output rate.
Linearity, full-scale accuracy, full-scale drift are identical for
both 2x and 1x speed modes. In both the 1x and 2x speed
there is no latency. This enables input steps or multiplexer
channel changes to settle in a single conversion cycle easing
system overhead and increasing the effective conversion
rate.
Output Data Format
The LTC2484 serial output data stream is 32 bits long. The
first 3 bits represent status information indicating the sign
and conversion state. The next 24 bits are the conversion
result, MSB first. The remaining 5 bits are sub LSBs below
the 24-bit level. The third and fourth bit together are also
used to indicate an underrange condition (the differential
input voltage is below FS) or an overrange condition (the
differential input voltage is above +FS).
CS may be pulled high prior to outputting all
32 bits, aborting the data out transfer and initiating a new
conversion.
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW.
16
LTC2484
2484f
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below FS.
The function of these bits is summarized in Table 2.
Table 2. LTC2484 Status Bits
BIT 31 BIT 30 BIT 29 BIT 28
INPUT RANGE
EOC
DMY
SIG
MSB
V
IN
0.5 V
REF
0
0
1
1
0V V
IN
< 0.5 V
REF
0
0
1
0
0.5 V
REF
V
IN
< 0V
0
0
0
1
V
IN
< 0.5 V
REF
0
0
0
0
Bits 28-5 are the 24-bit conversion result MSB first.
Bits 40 are sub LSBs below the 24-bit level. Bits 40 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK) (see Figure 2). Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes in real time
from HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on the
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 31st SCK and may be latched
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 3 summarizes
the output data format.
As long as the voltage on the IN
+
and IN
pins is maintained
within the 0.3V to (V
CC
+ 0.3V) absolute maximum
operating range, a conversion result is generated
for any differential input voltage
V
IN
from
FS = 0.5 V
REF
to +FS = 0.5 V
REF
. For differential input
voltages greater than +FS, the conversion result is clamped
to the value corresponding to the +FS + 1LSB. For
differential input voltages below FS, the conversion re-
sult is clamped to the value corresponding to FS 1LSB.
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Table 3. LTC2484 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
BIT 31
BIT 30
BIT 29
BIT 28
BIT 27
BIT 26
BIT 25
...
BIT 0
V
IN
*
EOC
DMY
SIG
MSB
V
IN
* FS**
0
0
1
1
0
0
0
...
0
FS** 1LSB
0
0
1
0
1
1
1
...
1
0.5 FS**
0
0
1
0
1
0
0
...
0
0.5 FS** 1LSB
0
0
1
0
0
1
1
...
1
0
0
0
1
0
0
0
0
...
0
1LSB
0
0
0
1
1
1
1
...
1
0.5 FS**
0
0
0
1
1
0
0
...
0
0.5 FS** 1LSB
0
0
0
1
0
1
1
...
1
FS**
0
0
0
1
0
0
0
...
0
V
IN
* < FS**
0
0
0
0
1
1
1
...
1
*The differential input voltage V
IN
= IN
+
IN
. **The full-scale voltage FS = 0.5 V
REF
.
17
LTC2484
2484f
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a SINC or Comb filter). For high
resolution, low frequency applications, this filter is typically
designed to reject line frequencies of 50Hz or 60Hz plus their
harmonics. The filter rejection performance is directly
related to the accuracy of the converter system clock.
The LTC2484 incorporates a highly accurate on-chip
oscillator. This eliminates the need for external frequency
setting components such as crystals or oscillators.
Frequency Rejection Selection (F
O
)
The LTC2484 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics (up to the 255th) for 50Hz 2% or 60Hz 2%,
or better than 87dB normal mode rejection from 48Hz to
62.4Hz. The rejection mode is selected by writing to the
on-chip configuration register and the default mode at
POR is simultaneous 50Hz/60Hz rejection.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2484 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the F
O
pin and turns off the internal oscillator. The
frequency f
EOSC
of the external signal must be at least
10kHz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the high and low periods t
HEO
and t
LEO
are observed.
Whenever an external clock is not present at the F
O
pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2484
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 4 summarizes the duration of each state and the
achievable output data rate as a function of F
O
.
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Figure 3. LTC2484 Normal Mode Rejection When Using
an External Oscillator
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
EOSC
/5120(%)
12
8
4
0
4
8
12
NORMAL MODE REJECTION (dB)
2484 F03
80
85
90
95
100
105
110
115
120
125
130
135
140
While operating with an external conversion clock of a
frequency f
EOSC
, the LTC2484 provides better than 110dB
normal mode rejection in a frequency range of f
EOSC
/5120
4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f
EOSC
/5120
is shown in Figure 3.
18
LTC2484
2484f
Ease of Use
The LTC2484 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2484 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to time,
supply voltage change and temperature drift.
Power-Up Sequence
The LTC2484 automatically enters an internal reset
state when the power supply voltage V
CC
drops below
approximately 2V. This feature guarantees the integrity of
the conversion result and of the serial interface mode
selection.
When the V
CC
voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 4ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2484 starts a normal conversion cycle and
follows the succession of states described in Figure 1. The
first conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
On-Chip Temperature Sensor
The LTC2484 contains an on-chip PTAT (proportional to
absolute temperature) signal that can be used as a
temperature sensor. The internal PTAT has a typical value
of 420mV at 27C and is proportional to the absolute tem-
perature value with a temperature coefficient of
420/(27 + 273) = 1.40mV/C (SLOPE), as shown in Figure
4. The internal PTAT signal is used in a single-ended mode
referenced to device ground internally. The 1x speed mode
with automatic offset calibration is automatically selected
for the internal PTAT signal measurement as well.
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Table 4. LTC2484 State Duration
STATE
OPERATING MODE
DURATION
CONVERT
Internal Oscillator
60Hz Rejection
133ms, Output Data Rate 7.5 Readings/s for 1x Speed Mode
67ms, Output Data Rate 15 Readings/s for 2x Speed Mode
50Hz Rejection
160ms, Output Data Rate 6.2 Readings/s for 1x Speed Mode
80ms, Output Data Rate 12.5 Readings/s for 2x Speed Mode
50Hz/60Hz Rejection
147ms, Output Data Rate 6.8 Readings/s for 1x Speed Mode
73.6ms, Output Data Rate 13.6 Readings/s for 2x Speed Mode
External Oscillator
F
O
= External Oscillator
41036/f
EOSC
s, Output Data Rate f
EOSC
/41036 Readings/s for
with Frequency f
EOSC
kHz
1x Speed Mode
(f
EOSC
/5120 Rejection)
20556/f
EOSC
s, Output Data Rate f
EOSC
/20556 Readings/s for
2x Speed Mode
SLEEP
As Long As CS = HIGH, After a Conversion is Complete
DATA OUTPUT
Internal Serial Clock
F
O
= LOW/HIGH
As Long As CS = LOW But Not Longer Than 0.83ms
(Internal Oscillator)
(32 SCK Cycles)
F
O
= External Oscillator with
As Long As CS = LOW But Not Longer Than 256/f
EOSC
ms
Frequency f
EOSC
kHz
(32 SCK Cycles)
External Serial Clock with
As Long As CS = LOW But Not Longer Than 32/f
SCK
ms
Frequency f
SCK
kHz
(32 SCK Cycles)
19
LTC2484
2484f
When using the internal temperature sensor, if the output
code is normalized to R
SDO
= V
PTAT
/V
REF
, the temperature
is calculated using the following formula:
T
R
V
SLOPE
T
R
V
SLOPE
K
SDO
REF
C
SDO
REF
=
=
in Kelvin
and
in C
273
where SLOPE is nominally 1.4mV/C
Since the PTAT signal can have an initial value variation
which results in errors in SLOPE, to achieve better tem-
perature measurements, a one-time calibration is needed
to adjust the SLOPE value. The converter output of the
PTAT signal, R0
SDO
, is measured at a known temperature
T0 (in C) and the SLOPE is calculated as:
SLOPE
R
V
T
SDO
REF
=
+
0
0 273
This calibrated SLOPE can be used to calculate the
temperature.
If the same V
REF
source is used during calibration and
temperature measurement, the actual value of the V
REF
is
not needed to measure the temperature as shown in the
calculation below:
T
R
V
SLOPE
R
R
T
C
SDO
REF
SDO
SDO
=
=
+
(
)
273
0
0
273
273
Reference Voltage Range
The LTC2484 external reference voltage range is 0.1V to
V
CC
. The converter output noise is determined by the
thermal noise of the front-end circuits, and as such, its
value in nanovolts is nearly constant with reference volt-
age. A reduced reference voltage will improve the con-
verter performance when operated with an external con-
version clock (external F
O
signal) at substantially higher
output data rates (see the Output Data Rate section). V
REF
must be 1.1V to use the internal temperature sensor.
The negative reference input to the converter is internally
tied to GND. GND (Pin 8) should be connected to a ground
plane through as short a trace as possible to minimize
voltage drop. The LTC2484 has an average operational
current of 160A and for 0.1 parasitic resistance, the
voltage drop of 16V causes a gain error of 3.2ppm for
V
REF
= 5V.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN
+
and IN
input pins
extending from GND 0.3V to V
CC
+ 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2484 converts the
bipolar differential input signal, V
IN
= IN
+
IN
, from
FS to +FS where FS = 0.5 V
REF
. Outside this range, the
converter indicates the overrange or the underrange con-
dition using distinct output codes. Since the differential
input current cancellation does not rely on an on-chip
buffer, current cancellation as well as DC performance is
maintained rail-to-rail.
Input signals applied to IN
+
and IN
pins may extend by
300mV below ground and above V
CC
. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN
+
and IN
pins without affecting the perfor-
mance of the devices. The effect of the series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sec-
tions. In addition, series resistors will introduce a tem-
perature dependent offset error due to the input leakage
current. A 1nA input leakage current will develop a 1ppm
offset error on a 5k resistor if V
REF
= 5V. This error has a
very strong temperature dependency.
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Figure 4. Internal PTAT Signal vs Temperature
TEMPERATURE (C)
60
V
PTAT
(mV)
500
600
120
2484 F04
400
200
30
0
90
30
60
300
V
CC
= 5V
IM = 1
F
O
= GND
SLOPE = 1.40mV/C
20
LTC2484
2484f
SERIAL INTERFACE TIMING MODES
The LTC2484's 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
operation. These include internal/external serial clock,
3- or 4-wire I/O, single cycle or continuous conversion.
The following sections describe each of these serial inter-
face timing modes in detail. In all these cases, the con-
verter can use the internal oscillator (F
O
= LOW or F
O
=
HIGH) or an external oscillator connected to the F
O
pin.
Refer to Table 5 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle (see Figure 5).
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. Independent of CS, the
device automatically enters the low power sleep state once
the conversion is complete.
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device
remains in the sleep state until the first rising edge of SCK
is seen while CS is LOW. The input data is then shifted in
via the SDI pin on the rising edge of SCK (including the
first rising edge) and the output data is shifted out of the
SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 32nd rising edge of SCK. On the 32nd falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the 32nd
falling edge of SCK (see Figure 6). On the rising edge of CS,
the device aborts the data output state and immediately
initiates a new conversion. If the device has not finished
loading the last input bit SPD of SDI by the time CS is pulled
HIGH, the SDI information is discarded and the previous
configuration is kept. This is useful for systems not requir-
ing all 32 bits of output data, aborting an invalid conversion
cycle or synchronizing the start of a conversion.
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Table 5. LTC2484 Interface Timing Modes
CONVERSION
DATA
CONNECTION
SCK
CYCLE
OUTPUT
and
CONFIGURATION
SOURCE
CONTROL
CONTROL
WAVEFORMS
External SCK, Single Cycle Conversion
External
CS and SCK
CS and SCK
Figures 5, 6
External SCK, 3-Wire I/O
External
SCK
SCK
Figure 7
Internal SCK, Single Cycle Conversion
Internal
CS
CS
Figures 8, 9
Internal SCK, 3-Wire I/O, Continuous Conversion
Internal
Continuous
Internal
Figure 10
21
LTC2484
2484f
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Figure 5. External Serial Clock, Single Cycle Operation
Figure 6. External Serial Clock, Reduced Data Output Length
EOC
BIT 31
SDO
SCK
(EXTERNAL)
CS
EN
DON'T CARE
IM
FOA
FOB
SPD
SDI
DON'T CARE
TEST EOC
MSB
SIG
BIT 0
LSB
BIT 5
BIT 27
BIT 26
BIT 25
BIT 24
BIT 28
BIT 29
BIT 30
SLEEP
SLEEP
DATA OUTPUT
CONVERSION
2484 F05
CONVERSION
Hi-Z
Hi-Z
Hi-Z
TEST EOC
V
CC
F
O
V
REF
IN
+
IN
SCK
SDI
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
7
8
6
1
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1F
2.7V TO 5.5V
LTC2484
4-WIRE
SPI INTERFACE
DON'T CARE
TEST EOC
(OPTIONAL)
EN
DON'T CARE
IM
FOA
FOB
SPD
SDI
DON'T CARE
DON'T CARE
SDO
SCK
(EXTERNAL)
CS
DATA
OUTPUT
CONVERSION
SLEEP
SLEEP
SLEEP
TEST EOC
DATA OUTPUT
Hi-Z
Hi-Z
Hi-Z
CONVERSION
2484 F06
MSB
SIG
BIT 8
BIT 27
BIT 26
BIT 25
BIT 24
BIT 9
BIT 28
BIT 29
BIT 30
EOC
BIT 31
BIT 0
EOC
Hi-Z
TEST EOC
TEST EOC
(OPTIONAL)
V
CC
F
O
V
REF
IN
+
IN
SCK
SDI
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
7
8
6
1
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1F
2.7V TO 5.5V
LTC2484
4-WIRE
SPI INTERFACE
22
LTC2484
2484f
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Figure 7. External Serial Clock, CS = 0 Operation
External Serial Clock, 3-Wire I/O
This timing mode utilizes a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal (see Figure 7). CS
may be permanently tied to ground, simplifying the user
interface or transmission over an isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
typically 4ms after V
CC
exceeds approximately 2V. The level
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. The input data is then shifted in via the SDI
pin on the rising edge of SCK (including the first rising
edge) and the output data is shifted out of the SDO pin on
each falling edge of SCK. EOC can be latched on the
first rising edge of SCK. On the 32nd falling edge of SCK,
SDO goes HIGH (EOC = 1) indicating a new conversion
has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle (see Figure 8).
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
EN
GS2
GS1
GS0
IM
FA
FB
SPD
SDI*
DON'T CARE
DON'T CARE
EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
MSB
SIG
BIT 0
IM
LSB
BIT 4
BIT 19
BIT 18
BIT 17
BIT 16
BIT 20
BIT 21
BIT 22
DATA OUTPUT
CONVERSION
2484 F07
CONVERSION
V
CC
F
O
V
REF
IN
+
IN
SCK
SDI
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
7
8
6
1
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1F
2.7V TO 5.5V
LTC2484
3-WIRE
SPI INTERFACE
23
LTC2484
2484f
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result on the 32nd rising edge of
SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1), SCK stays HIGH and a new conversion starts.
CS remains LOW during the data output state. However,
the data output state may be aborted by pulling CS HIGH
anytime between the first and 32nd rising edge of SCK (see
Figure 9). On the rising edge of CS, the device aborts the
data output state and immediately initiates a new conver-
sion. If the device has not finished loading the last input bit
(SPD) of SDI by the time CS is pulled HIGH, the SDI
information is discarded and the previous configuration is
still kept. This is useful for systems not requiring all 32 bits
of output data, aborting an invalid conversion cycle, or
synchronizing the start of a conversion. If CS is pulled
HIGH while the converter is driving SCK LOW, the internal
pull-up is not available to restore SCK to a logic HIGH state.
This will cause the device to exit the internal serial clock
mode on the next falling edge of CS. This can be avoided
by adding an external 10k pull-up resistor to the SCK pin
or by never pulling CS HIGH when SCK is LOW.
APPLICATIO S I FOR ATIO
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When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the low power mode during the EOC
test. In order to allow the device to return to the low power
sleep state, CS must be pulled HIGH before the first rising
edge of SCK. In the internal SCK timing mode, SCK goes
HIGH and the device begins outputting data at time t
EOCtest
after the falling edge of CS (if EOC = 0) or t
EOCtest
after EOC
goes LOW (if CS is LOW during the falling edge of EOC).
The value of t
EOCtest
is 12s if the device is using its internal
oscillator. If F
O
is driven by an external oscillator of
frequency f
EOSC
, then t
EOCtest
is 3.6/f
EOSC
in seconds. If CS
is pulled HIGH before time t
EOCtest
, the device returns to
the sleep state and the conversion result is held in the
internal static shift register.
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 32nd rising edge. The input data is shifted in via
the SDI pin on the rising edge of SCK (including the first
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
Figure 8. Internal Serial Clock, Single Cycle Operation
EN
DON'T CARE
IM
FOA
FOB
SPD
SDI
DON'T CARE
DON'T CARE
SDO
SCK
(INTERNAL)
CS
MSB
SIG
BIT 0
LSB
BIT 5
TEST EOC
BIT 27
BIT 26
BIT 25
BIT 24
BIT 28
BIT 29
BIT 30
EOC
BIT 31
SLEEP
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
2484 F08
<t
EOCtest
Hi-Z
Hi-Z
Hi-Z
Hi-Z
TEST EOC
V
CC
F
O
V
REF
IN
+
IN
SCK
SDI
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
10k
V
CC
7
8
6
1
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1F
2.7V TO 5.5V
LTC2484
4-WIRE
SPI INTERFACE
24
LTC2484
2484f
APPLICATIO S I FOR ATIO
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Whenever SCK is LOW, the LTC2484's internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2484's internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH once
the external driver goes Hi-Z. On the next CS falling edge,
the device will remain in the internal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as t
EOCtest
), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 3-Wire I/O,
Continuous Conversion
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal, see Figure 10. CS may be perma-
nently tied to ground, simplifying the user interface or
transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V
CC
exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
Figure 9. Internal Serial Clock, Reduce Data Output Length
EN
DON'T CARE
IM
FOA
FOB
SPD
SDI
DON'T CARE
DON'T CARE
SDO
SCK
(INTERNAL)
CS
> t
EOCtest
MSB
SIG
BIT 8
TEST EOC
(OPTIONAL)
TEST EOC
BIT 27
BIT 26
BIT 25
BIT 24
BIT 28
BIT 29
BIT 30
EOC
BIT 31
EOC
BIT 0
SLEEP
SLEEP
DATA OUTPUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DATA
OUTPUT
CONVERSION
CONVERSION
SLEEP
2484 F09
<t
EOCtest
TEST EOC
V
CC
F
O
V
REF
IN
+
IN
SCK
SDI
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
10k
V
CC
7
8
6
1
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1F
2.7V TO 5.5V
LTC2484
4-WIRE
SPI INTERFACE
25
LTC2484
2484f
APPLICATIO S I FOR ATIO
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then immediately begins outputting data. The data input/
output cycle begins on the first rising edge of SCK and
ends after the 32nd rising edge. The input data is then
shifted in via the SDI pin on the rising edge of SCK
(including the first rising edge) and the output data is
shifted out of the SDO pin on each falling edge of SCK.
The internally generated serial clock is output to the SCK
pin. This signal may be used to shift the conversion result
into external circuitry. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1) indicating a
new conversion is in progress. SCK remains HIGH during
the conversion.
PRESERVING THE CONVERTER ACCURACY
The LTC2484 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line frequency perturba-
tions and so on. Nevertheless, in order to preserve the
24-bit accuracy capability of this part, some simple pre-
cautions are required.
Digital Signal Levels
The LTC2484's digital interface is easy to use. Its digital
inputs (SDI, F
O
, CS and SCK in External SCK mode of
operation) accept standard CMOS logic levels and the in-
ternal hysteresis receivers can tolerate edge transition times
as slow as 100s. However, some considerations are re-
quired to take advantage of the exceptional accuracy and
low supply current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(V
CC
0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (SDI, F
O
, CS
and SCK in External SCK mode of operation) is within
this range, the power supply current may increase even
if the signal in question is at a valid logic level. For
micropower operation, it is recommended to drive all
digital input signals to full CMOS levels [V
IL
< 0.4V and
V
OH
> (V
CC
0.4V)].
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
EN
GS2
GS1
GS0
IM
FA
FB
SPD
SDI*
DON'T CARE
DON'T CARE
SDO
SCK
(INTERNAL)
CS
LSB
MSB
SIG
BIT 4
BIT 0
IM
BIT 19
BIT 18
BIT 17
BIT 16
BIT 20
BIT 21
BIT 22
EOC
BIT 23
DATA OUTPUT
CONVERSION
CONVERSION
2484 F10
V
CC
F
O
V
REF
IN
+
IN
SCK
SDI
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
7
8
6
1
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1F
2.7V TO 5.5V
LTC2484
3-WIRE
SPI INTERFACE
10k
V
CC
26
LTC2484
2484f
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the pins can
severely disturb the analog to digital conversion process.
Undershoot and overshoot occur because of the imped-
ance mismatch at the converter pin when the transition
time of an external control signal is less than twice the
propagation delay from the driver to the LTC2484. For
reference, on a regular FR-4 board, signal propagation
velocity is approximately 183ps/inch for internal traces
and 170ps/inch for surface traces. Thus, a driver gener-
ating a control signal with a minimum transition time of
1ns must be connected to the converter pin through a
trace shorter than 2.5 inches. This problem becomes
particularly difficult when shared control lines are used
and multiple reflections may occur. The solution is to
carefully terminate all transmission lines close to their
characteristic impedance.
Parallel termination near the LTC2484 pin will eliminate
this problem but will increase the driver power dissipation.
A series resistor between 27 and 56 placed near the
driver output pin will also eliminate this problem without
additional power dissipation. The actual resistor value
depends upon the trace impedance and connection
topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The differential input archi-
tecture reduces the converter's sensitivity to ground
currents.
Particular attention must be given to the connection of the
F
O
signal when the LTC2484 is used with an external
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals can result in DC gain and INL errors.
A normal mode signal of this frequency at the converter
input terminals can result in a DC offset error. Such
perturbations can occur due to asymmetric capacitive
coupling between the F
O
signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the F
O
signal trace and the input/reference sig-
nals. When the F
O
signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formed by the F
O
connection trace, the termination and the
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the F
O
signal as well as the loop area for
the differential input and reference connections. Even
when F
O
is not driven, other nearby signals pose similiar
EMI threats which will be minimized by following good
layout practices.
Driving the Input and Reference
The input and reference pins of the LTC2484 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltage and the differential reference voltage, these ca-
pacitors are switching between these four pins transfer-
ring small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 11.
For a simple approximation, the source impedance R
S
driving an analog input pin (IN
+
, IN
, V
REF
+
or GND) can be
considered to form, together with R
SW
and C
EQ
(see
Figure 11), a first order passive network with a time
constant = (R
S
+ R
SW
) C
EQ
. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant . The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
When using the internal oscillator, the LTC2484's front-
end switched-capacitor network is clocked at 123kHz
corresponding to an 8.1s sampling period. Thus, for
settling errors of less than 1ppm, the driving source
impedance should be chosen such that 8.1s/14 =
580ns. When an external oscillator of frequency f
EOSC
is
used, the sampling period is 2.5/f
EOSC
and, for a settling
error of less than 1ppm, 0.178/f
EOSC
.
APPLICATIO S I FOR ATIO
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27
LTC2484
2484f
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is low
(up to 10k with no external bypass capacitor or up to
500 with 0.001F bypass), complete settling of the input
occurs. In this case, no errors are introduced and direct
digitization of the sensor is possible.
For many applications, the sensor output impedance com-
bined with external bypass capacitors produces RC time
constants much greater than the 580ns required for 1ppm
accuracy. For example, a 10k bridge driving a 0.1F
bypass capacitor has a time constant an order of magni-
tude greater than the required maximum. Historically,
settling issues were solved using buffers. These buffers
led to increased noise, reduced DC performance (Offset/
Drift), limited input/output swing (cannot digitize signals
near ground or V
CC
), added system cost and increased
power. The LTC2484 uses a proprietary switching algo-
rithm that forces the average differential input current to
zero independent of external settling errors. This allows
accurate direct digitization of high impedance sensors
without the need for buffers. Additional errors resulting
from mismatched leakage currents must also be taken into
account.
The switching algorithm forces the average input current
on the positive input (I
IN
+
) to be equal to the average input
current on the negative input (I
IN
). Over the complete
conversion cycle, the average differential input current
(I
IN
+
I
IN
) is zero. While the differential input current is
zero, the common mode input current (I
IN
+
+ I
IN
)/2 is
proportional to the difference between the common mode
input voltage (V
INCM
) and the common mode reference
voltage (V
REFCM
).
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balance bridge type application, both the differ-
ential and common mode input current are zero. The
accuracy of the converter is unaffected by settling errors.
Mismatches in source impedances between IN
+
and IN
also do not affect the accuracy.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between V
INCM
and V
REFCM
. For a reference
common mode of 2.5V and an input common mode of
1.5V, the common mode input current is approximately
0.74A (in simultaneous 50Hz/60Hz rejection mode). This
common mode input current has no effect on the accuracy
if the external source impedances tied to IN
+
and IN
are
matched. Mismatches in these source impedances lead to
a fixed offset error but do not affect the linearity or full-
scale reading. A 1% mismatch in 1k source resistances
leads to a 15ppm shift (74V) in offset voltage.
APPLICATIO S I FOR ATIO
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Figure 11. LTC2484 Equivalent Analog Input Circuit
V
REF
+
V
IN
+
V
CC
R
SW
(TYP)
10k
I
LEAK
I
LEAK
V
CC
I
LEAK
I
LEAK
V
CC
R
SW
(TYP)
10k
C
EQ
12pF
(TYP)
R
SW
(TYP)
10k
I
LEAK
I
IN
+
V
IN
I
IN
I
REF
+
I
REF
2484 F11
I
LEAK
V
CC
I
LEAK
I
LEAK
SWITCHING FREQUENCY
f
SW
= 123kHz INTERNAL OSCILLATOR
f
SW
= 0.4 f
EOSC
EXTERNAL OSCILLATOR
GND
R
SW
(TYP)
10k
I IN
I IN
V
V
R
I REF
V
V
V
R
V
V
R
V
D
R
V
V
V
R
V
V
R
where
AVG
AVG
IN CM
REF CM
EQ
AVG
REF
V
REF
INCM
REFCM
EQ
IN
REF
EQ
REF
T
EQ
REF
REF CM
IN CM
EQ
IN
REF
EQ
+
+
( )
=
( )
=
-
( )
=
-
+
-
-
+
(
)
(
)
(
)
(
)
(
)
.
.
.
.
.
.
0 5
1 5
0 5
0 5
1 5
0 5
2
2
:
.
V
V
IN
IN
V
IN
IN
R
M
INTERNAL OSCILLATOR
Hz MODE
REFCM
IN
INCM
EQ
=
=
-
=
+
=
=
=
(
)
+
+
-
+
-
2
2
2 71
60
R
2.98M
INTERNAL OSCILLATOR 50Hz AND 60Hz MODE
R
0.833 10
/ f
EXTERNAL OSCILLATOR
D IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT
EQ
EQ
12
EOSC
T
WHERE REF
IS INTERNALLY TIED TO GND
28
LTC2484
2484f
APPLICATIO S I FOR ATIO
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Figure 12. An RC Network at IN
+
and IN
Figure 13. +FS Error vs R
SOURCE
at IN
+
or IN
Figure 14. FS Error vs R
SOURCE
at IN
+
or IN
C
IN
2484 F12
V
INCM
+ 0.5V
IN
R
SOURCE
IN
+
LTC2484
C
PAR
20pF
C
IN
V
INCM
0.5V
IN
R
SOURCE
IN
C
PAR
20pF
R
SOURCE
()
1
+FS ERROR (ppm)
20
0
20
1k
100k
2484 F13
40
60
80
10
100
10k
40
60
80
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 3.75V
V
IN
= 1.25V
F
O
= GND
T
A
= 25C
C
IN
= 0pF
C
IN
= 100pF
C
IN
= 1nF, 0.1F, 1F
R
SOURCE
()
1
FS ERROR (ppm) 20
0
20
1k
100k
2484 F14
40
60
80
10
100
10k
40
60
80
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 1.25V
V
IN
= 3.75V
F
O
= GND
T
A
= 25C
C
IN
= 0pF
C
IN
= 100pF
C
IN
= 1nF, 0.1F, 1F
common mode input current varies proportionally with
input voltage. For the case of balanced input impedances,
the common mode input current effects are rejected by the
large CMRR of the LTC2484 leading to little degradation in
accuracy. Mismatches in source impedances lead to gain
errors proportional to the difference between the common
mode input voltage and the common mode reference
voltage. 1% mismatches in 1k source resistances lead
to gain worst-case gain errors on the order of 15ppm (for
1V differences in reference and input common mode
voltage). Table 6 summarizes the effects of mismatched
source impedance and differences in reference/input com-
mon mode voltages.
Table 6. Suggested Input Configuration for LTC2484
BALANCED INPUT
UNBALANCED INPUT
RESISTANCES
RESISTANCES
Constant
C
IN
> 1nF at Both
C
IN
> 1nF at Both IN
+
V
IN(CM)
V
REF(CM)
IN
+
and IN
. Can Take
and IN
. Can Take Large
Large Source Resistance
Source Resistance.
with Negligible Error
Unbalanced Resistance
Results in an Offset
Which Can be Calibrated
Varying
C
IN
> 1nF at Both IN
+
Minimize IN
+
and IN
V
IN(CM)
V
REF(CM)
and IN
. Can Take Large
Capacitors and Avoid
Source Resistance with
Large Source Impedance
Negligible Error
(< 5k Recommended)
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/C) are
used for the external source impedance seen by IN
+
and
IN
, the expected drift of the dynamic current and offset
will be insignificant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (10nA max), results
in a small offset shift. A 1k source resistance will create a
1V typical and 10V maximum offset voltage.
In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the
29
LTC2484
2484f
Reference Current
In a similar fashion, the LTC2484 samples the differential
reference pins V
REF
+
and GND transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can be
analyzed in two distinct situations.
For relatively small values of the external reference capaci-
tors (C
REF
< 1nF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C
REF
will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (C
REF
> 1nF) may be
required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance.
In the following discussion, it is assumed the input and
reference common mode are the same. Using internal
oscillator for 60Hz mode, the typical differential refer-
ence resistance is 1M which generates a full-scale
(V
REF
/2) gain error of 0.51ppm for each ohm of source
resistance driving the V
REF
pin. For 50Hz/60Hz mode, the
related difference resistance is 1.1M and the resulting
full-scale error is 0.46ppm for each ohm of source
resistance driving the V
REF
pin. For 50Hz mode, the
related difference resistance is 1.2M and the resulting
full-scale error is 0.42ppm for each ohm of source
resistance driving the V
REF
pin. When F
O
is driven by an
external oscillator with a frequency f
EOSC
(external con-
version clock operation), the typical differential reference
resistance is 0.30 10
12
/f
EOSC
and each ohm of source
resistance driving the V
REF
pin will result in 1.67 10
6
f
EOSC
ppm gain error. The typical +FS and FS errors for
various combinations of source resistance seen by the
V
REF
pin and external capacitance connected to that pin
are shown in Figures 15-18.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
The INL is caused by the input dependent terms
V
IN
2
/(V
REF
R
EQ
) (0.5 V
REF
D
T
)/R
EQ
in the reference
pin current as expressed in Figure 11. When using internal
oscillator and 60Hz mode, every 100 of reference source
resistance translates into about 0.67ppm additional INL
error. When using internal oscillator and 50Hz/60Hz mode,
every 100 of reference source resistance translates into
about 0.61ppm additional INL error. When using internal
oscillator and 50Hz mode, every 100 of reference source
resistance translates into about 0.56ppm additional INL
error. When F
O
is driven by an external oscillator with a
frequency f
EOSC
, every 100 of source resistance driving
V
REF
translates into about 2.18 10
6
f
EOSC
ppm addi-
tional INL error. Figure 19 shows the typical INL error due
to the source resistance driving the V
REF
pin when large
C
REF
values are used. The user is advised to minimize the
source impedance driving the V
REF
pin.
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (V
REFCM
V
INCM
) and a 5V reference,
each Ohm of reference source resistance introduces an
extra (V
REFCM
V
INCM
)/(V
REF
R
EQ
) full-scale gain error,
which is 0.074ppm when using internal oscillator and
60Hz mode. When using internal oscillator and 50Hz/60Hz
mode, the extra full-scale gain error is 0.067ppm. When
using internal oscillator and 50Hz mode, the extra gain
error is 0.061ppm. If an external clock is used, the corre-
sponding extra gain error is 0.24 10
6
f
EOSC
ppm.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typically better
than 0.5%. Such a specification can also be easily achieved
by an external clock. When relatively stable resistors
(50ppm/C) are used for the external source impedance
seen by V
REF
+
and GND, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
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30
LTC2484
2484f
leakage current. This leakage current, nominally 1nA
(10nA max), results in a small gain error. A 100 source
resistance will create a 0.05V typical and 0.5V maxi-
mum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2484 produces
up to 7.5 samples per second (sps) with a notch frequency
of 60Hz, 6.25sps with a notch frequency of 50Hz and 6.8ps
with the 50Hz/60Hz rejection mode. The actual output data
rate will depend upon the length of the sleep and data
output phases which are controlled by the user and which
can be made insignificantly short. When operated with an
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Figure 15. +FS Error vs R
SOURCE
at V
REF
(Small C
REF
)
Figure 16. FS Error vs R
SOURCE
at V
REF
(Small C
REF
)
Figure 17. +FS Error vs R
SOURCE
at V
REF
(Large C
REF
)
Figure 18. FS Error vs R
SOURCE
at V
REF
(Large C
REF
)
Figure 19. INL vs Differential Input Voltage and
Reference Source Resistance for C
REF
> 1F
R
SOURCE
()
0
+FS ERROR (ppm)
50
70
90
10k
2484 F15
30
10
40
60
80
20
0
10
10
100
1k
100k
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 3.75V
V
IN
= 1.25V
F
O
= GND
T
A
= 25C
C
REF
= 0.01F
C
REF
= 0.001F
C
REF
= 100pF
C
REF
= 0pF
R
SOURCE
()
0
FS ERROR (ppm)
200
100
0
800
2484 F18
300
400
500
200
400
600
1000
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 1.25V
V
IN
= 3.75V
F
O
= GND
T
A
= 25C
C
REF
= 1F, 10F
C
REF
= 0.1F
C
REF
= 0.01F
R
SOURCE
()
0
FS ERROR (ppm)
30
10
10
10k
2484 F16
50
70
40
20
0
60
80
90
10
100
1k
100k
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 1.25V
V
IN
= 3.75V
F
O
= GND
T
A
= 25C
C
REF
= 0.01F
C
REF
= 0.001F
C
REF
= 100pF
C
REF
= 0pF
R
SOURCE
()
0
+FS ERROR (ppm)
300
400
500
800
2484 F17
200
100
0
200
400
600
1000
V
CC
= 5V
V
REF
= 5V
V
IN
+
= 3.75V
V
IN
= 1.25V
F
O
= GND
T
A
= 25C
C
REF
= 1F, 10F
C
REF
= 0.1F
C
REF
= 0.01F
V
IN
/V
REF
(V)
0.5
INL (ppm OF V
REF
)
2
6
10
0.3
2484 F19
2
6
0
4
8
4
8
10
0.3
0.1
0.1
0.5
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
T
A
= 25C
C
REF
= 10F
R = 1k
R = 100
R = 500
31
LTC2484
2484f
external conversion clock (F
O
connected to an external
oscillator), the LTC2484 output data rate can be increased
as desired. The duration of the conversion phase is 41036/
f
EOSC
. If f
EOSC
= 307.2kHz, the converter behaves as if the
internal oscillator is used and the notch is set at 60Hz.
An increase in f
EOSC
over the nominal 307.2kHz will
translate into a proportional increase in the maximum
output data rate. The increase in output rate is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
First, a change in f
EOSC
will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent perfor-
mance degradation can be substantially reduced by rely-
ing upon the LTC2484's exceptional common mode rejec-
tion and by carefully eliminating common mode to differ-
ential mode conversion sources in the input circuit. The
user should avoid single-ended input filters and should
maintain a very high degree of matching and symmetry in
the circuits driving the IN
+
and IN
pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (C
IN
, C
REF
) are used, the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter perfor-
mance for any value of f
EOSC
. If small external input and/or
reference capacitors (C
IN
, C
REF
) are used, the effect of the
external source resistance upon the LTC2484 typical
performance can be inferred from Figures 13, 14, 15 and
16 in which the horizontal axis is scaled by 307200/f
EOSC
.
Third, an increase in the frequency of the external oscilla-
tor above 1MHz (a more than 3 increase in the output data
rate) will start to decrease the effectiveness of the internal
autocalibration circuits. This will result in a progressive
degradation in the converter accuracy and linearity. Typi-
cal measured performance curves for output data rates up
to 100 readings per second are shown in Figures 20 to 27.
In order to obtain the highest possible level of accuracy from
this converter at output data rates above 20 readings per
second, the user is advised to maximize the power supply
voltage used and to limit the maximum ambient operating
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Figure 20. Offset Error vs Output Data Rate and Temperature
Figure 21. +FS Error vs Output Data Rate and Temperature
Figure 22. FS Error vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
10
OFFSET ERROR (ppm OF V
REF
)
10
30
50
0
20
40
20
40
60
80
2484 F20
100
10
0
30
50
70
90
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
V
IN
= 0V
F
O
= EXT CLOCK
T
A
= 85C
T
A
= 25C
OUTPUT DATA RATE (READINGS/SEC)
0
0
+FS ERROR (ppm OF V
REF
)
500
1500
2000
2500
3500
10
50
70
2484 F21
1000
3000
40
90 100
20 30
60
80
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
F
O
= EXT CLOCK
T
A
= 85C
T
A
= 25C
OUTPUT DATA RATE (READINGS/SEC)
0
3500
FS ERROR (ppm OF V
REF
)
3000
2000
1500
1000
0
10
50
70
2484 F22
2500
500
40
90 100
20 30
60
80
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
F
O
= EXT CLOCK
T
A
= 85C
T
A
= 25C
32
LTC2484
2484f
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Figure 23. Resolution (Noise
RMS
1LSB)
vs Output Data Rate and Temperature
Figure 24. Resolution (INL
MAX
1LSB)
vs Output Data Rate and Temperature
Figure 25. Offset Error vs Output
Data Rate and Reference Voltage
Figure 26. Resolution (Noise
RMS
1LSB)
vs Output Data Rate and Reference Voltage
Figure 27. Resolution (INL
MAX
1LSB) vs
Output Data Rate and Reference Voltage
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION (BITS)
12
16
18
20
24
10
50
70
2484 F23
14
22
40
90 100
20 30
60
80
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
V
IN
= 0V
F
O
= EXT CLOCK
RES = LOG 2 (V
REF
/NOISE
RMS
)
T
A
= 85C
T
A
= 25C
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION (BITS)
12
16
18
22
10
50
70
2484 F24
14
20
40
90 100
20 30
60
80
T
A
= 85C
T
A
= 25C
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
F
O
= EXT CLOCK
RES = LOG 2 (V
REF
/INL
MAX
)
OUTPUT DATA RATE (READINGS/SEC)
0
10
OFFSET ERROR (ppm OF V
REF
)
5
5
10
20
10
50
70
2484 F25
0
15
40
90 100
20 30
60
80
V
CC
= 5V, V
REF
= 2.5V
V
CC
= V
REF
= 5V
V
IN(CM)
= V
REF(CM)
V
IN
= 0V
F
O
= EXT CLOCK
T
A
= 25C
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION (BITS)
12
16
18
20
24
10
50
70
2484 F26
14
22
40
90 100
20 30
60
80
V
IN(CM)
= V
REF(CM)
V
IN
= 0V
F
O
= EXT CLOCK
T
A
= 25C
RES = LOG 2 (V
REF
/NOISE
RMS
)
V
CC
= 5V, V
REF
= 2.5V
V
CC
= V
REF
= 5V
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION (BITS)
12
16
18
22
10
50
70
2484 F27
14
20
40
90 100
20 30
60
80
V
CC
= 5V, V
REF
= 2.5V
V
CC
= V
REF
= 5V
V
IN(CM)
= V
REF(CM)
V
IN
= 0V
REF
= GND
F
O
= EXT CLOCK
T
A
= 25C
RES = LOG 2 (V
REF
/INL
MAX
)
temperature. In certain circumstances, a reduction of the
differential reference voltage may be beneficial.
Input Bandwidth
The combined effect of the internal SINC
4
digital filter and
of the analog and digital autocalibration circuits deter-
mines the LTC2484 input bandwidth. When the internal
oscillator is used with the notch set at 60Hz, the 3dB input
bandwidth is 3.63Hz. When the internal oscillator is used
with the notch set at 50Hz, the 3dB input bandwidth is
3.02Hz. If an external conversion clock generator of fre-
quency f
EOSC
is connected to the F
O
pin, the 3dB input
bandwidth is 11.8 10
6
f
EOSC
.
33
LTC2484
2484f
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Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a first order filter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2484 input bandwidth is shown in
Figure 28. When an external oscillator of frequency f
EOSC
is used, the shape of the LTC2484 input bandwidth can be
derived from Figure 28, 60Hz mode curve in which the
horizontal axis is scaled by f
EOSC
/307200.
The conversion noise (600nV
RMS
typical for V
REF
= 5V)
can be modeled by a white noise source connected to a
noise free converter. The noise spectral density is 47nVHz
for an infinite bandwidth source and 64nVHz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is a
high gain, low bandwidth amplifier stage followed by a
high bandwidth unity-gain buffer.
When external amplifiers are driving the LTC2484, the
ADC input referred system noise calculation can be sim-
plified by Figure 29. The noise of an amplifier driving the
LTC2484 input pin can be modeled as a band limited white
noise source. Its bandwidth can be approximated by the
bandwidth of a single pole lowpass filter with a corner
frequency f
i
. The amplifier noise spectral density is n
i
.
From Figure 29, using f
i
as the x-axis selector, we can find
on the y-axis the noise equivalent bandwidth freq
i
of the
input driving amplifier. This bandwidth includes the band
limiting effects of the ADC internal calibration and filter-
ing. The noise of the driving amplifier referred to the
converter input and including all these effects can be
calculated as N = n
i
freq
i
. The total system noise
(referred to the LTC2484 input) can now be obtained by
summing as square root of sum of squares the three ADC
input referred noise sources: the LTC2484 internal noise,
the noise of the IN
+
driving amplifier and the noise of the
IN
driving amplifier.
If the F
O
pin is driven by an external oscillator of frequency
f
EOSC
, Figure 29 can still be used for noise calculation if the
x-axis is scaled by f
EOSC
/307200. For large values of the
ratio f
EOSC
/307200, the Figure 29 plot accuracy begins to
decrease, but at the same time the LTC2484 noise floor
rises and the noise contribution of the driving amplifiers
lose significance.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2484 significantly
simplifies antialiasing filter requirements. Additionally,
the input current cancellation feature of the LTC2484
allows external lowpass filtering without degrading the DC
performance of the device.
Figure 29. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
INPUT SIGNAL ATTENUATION (dB)
3
2
1
0
4
2484 F28
4
5
6
1
2
3
5
50Hz MODE
60Hz MODE
50Hz AND
60Hz MODE
Figure 28. Input Signal Bandwidth Using the Internal Oscillator
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
1
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
10
0.1
1
10
100
1k
10k
100k
1M
2484 F29
0.1
100
50Hz MODE
60Hz MODE
34
LTC2484
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Figure 30. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch Mode
Figure 31. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Notch Mode or External Oscillator
The SINC
4
digital filter provides greater than 120dB nor-
mal mode rejection at all frequencies except DC and
integer multiples of the modulator sampling frequency
(f
S
). The LTC2484's autocalibration circuits further sim-
plify the antialiasing requirements by additional normal
mode signal filtering both in the analog and digital domain.
Independent of the operating mode, f
S
= 256 f
N
= 2048
f
OUTMAX
where f
N
is the notch frequency and f
OUTMAX
is
the maximum output data rate. In the internal oscillator
mode with a 50Hz notch setting, f
S
= 12800Hz, with
50Hz/60Hz rejection, f
S
= 13960Hz and with a 60Hz notch
setting f
S
= 15360Hz. In the external oscillator mode, f
S
=
f
EOSC
/20. The performance of the normal mode rejection
is shown in Figures 30 and 31.
In 1x speed mode, the regions of low rejection occurring
at integer multiples of f
S
have a very narrow bandwidth.
Magnified details of the normal mode rejection curves are
shown in Figure 32 (rejection near DC) and Figure 33
(rejection at f
S
= 256f
N
) where f
N
represents the notch
frequency. These curves have been derived for the exter-
nal oscillator mode but they can be used in all operating
modes by appropriately selecting the f
N
value.
The user can expect to achieve this level of performance
using the internal oscillator as it is demonstrated by Fig-
ures 34, 35 and 36. Typical measured values of the normal
mode rejection of the LTC2484 operating with an internal
oscillator and a 60Hz notch setting are shown in Figure 34
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
f
S
2f
S
3f
S
4f
S
5f
S
6f
S
7f
S
8f
S
9f
S
10f
S
11f
S
12f
S
INPUT NORMAL MODE REJECTION (dB)
2484 F30
0
10
20
30
40
50
60
70
80
90
100
110
120
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
f
S
INPUT NORMAL MODE REJECTION (dB)
2484 F31
0
10
20
30
40
50
60
70
80
90
100
110
120
2f
S
3f
S
4f
S
5f
S
6f
S
7f
S
8f
S
9f
S
10f
S
Figure 32. Input Normal Mode Rejection at DC
Figure 33. Input Normal Mode Rejection at f
S
= 256f
N
INPUT SIGNAL FREQUENCY (Hz)
INPUT NORMAL MODE REJECTION (dB)
2484 F32
0
10
20
30
40
50
60
70
80
90
100
110
120
f
N
0
2f
N
3f
N
4f
N
5f
N
6f
N
7f
N
8f
N
INPUT SIGNAL FREQUENCY (Hz)
250f
N
252f
N
254f
N
256f
N
258f
N
260f
N
262f
N
INPUT NORMAL MODE REJECTION (dB)
2484 F33
0
10
20
30
40
50
60
70
80
90
100
110
120
35
LTC2484
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Figure 34. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (60Hz Notch)
Figure 35. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (50Hz Notch)
Figure 36. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (50Hz/60Hz Mode)
INPUT FREQUENCY (Hz)
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210 225 240
NORMAL MODE REJECTION (dB)
2484 F34
0
20
40
60
80
100
120
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
V
IN(P-P)
= 5V
T
A
= 25C
MEASURED DATA
CALCULATED DATA
INPUT FREQUENCY (Hz)
0
12.5
25
37.5
50
62.5
75
87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
NORMAL MODE REJECTION (dB)
2484 F35
0
20
40
60
80
100
120
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
V
IN(P-P)
= 5V
T
A
= 25C
MEASURED DATA
CALCULATED DATA
INPUT FREQUENCY (Hz)
0
20
40
60
80
100
120
140
160
180
200
220
NORMAL MODE REJECTION (dB)
2484 F36
0
20
40
60
80
100
120
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
V
IN(P-P)
= 5V
T
A
= 25C
MEASURED DATA
CALCULATED DATA
As a result of these remarkable normal mode specifica-
tions, minimal (if any) antialias filtering is required in front
of the LTC2484. If passive RC components are placed in
front of the LTC2484, the input dynamic current should be
considered (see Input Current section). In this case, the
differential input current cancellation feature of the LTC2484
allows external RC networks without significant degrada-
tion in DC performance.
Traditional high order delta-sigma modulators, while pro-
viding very good linearity and resolution, suffer from po-
tential instabilities at large input signal levels. The
proprietary architecture used for the LTC2484 third order
modulator resolves this problem and guarantees a pre-
dictable stable behavior at input signal levels of up to 150%
of full scale. In many industrial applications, it is not un-
common to have to measure microvolt level signals super-
imposed over volt level perturbations and the LTC2484 is
eminently suited for such tasks. When the perturbation is
differential, the specification of interest is the normal mode
rejection for large input signal levels. With a reference
voltage V
REF
= 5V, the LTC2484 has a full-scale differen-
tial input range of 5V peak-to-peak. Figures 37 and 38
show measurement results for the LTC2484 normal mode
rejection ratio with a 7.5V peak-to-peak (150% of full scale)
input signal superimposed over the more traditional nor-
mal mode rejection ratio results obtained with a 5V peak-
to-peak (full scale) input signal. In Figure 37, the LTC2484
uses the internal oscillator with the notch set at 60Hz (F
O
= LOW) and in Figure 38 it uses the internal oscillator with
the notch set at 50Hz. It is clear that the LTC2484 rejection
performance is maintained with no compromises in this
extreme situation. When operating with large input signal
levels, the user must observe that such signals do not
violate the device absolute maximum ratings.
Using the 2x speed mode of the LTC2484, the device
bypasses the digital offset calibration operation to double
the output data rate. The superior normal mode rejection
is maintained as shown in Figures 30 and 31. However, the
magnified details near DC and f
S
= 256f
N
are different, see
Figures 39 and 40. In 2x speed mode, the bandwidth is
11.4Hz for the 50Hz rejection mode, 13.6Hz for the 60Hz
rejection mode and 12.4Hz for the 50Hz/60Hz rejection
superimposed over the theoretical calculated curve. Simi-
larly, the measured normal mode rejection of the LTC2484
for the 50Hz rejection mode and 50Hz/60Hz rejection mode
are shown in Figures 35 and 36.
36
LTC2484
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Figure 37. Measured Input Normal Mode Rejection vs
Input Frequency with Input Perturbation of 150% Full
Scale (60Hz Notch)
INPUT FREQUENCY (Hz)
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210 225 240
NORMAL MODE REJECTION (dB)
2484 F37
0
20
40
60
80
100
120
V
CC
= 5V
V
REF
= 5V
V
INCM
= 2.5V
T
A
= 25C
V
IN(P-P)
= 5V
V
IN(P-P)
= 7.5V
(150% OF FULL SCALE)
Figure 38. Measured Input Normal Mode Rejection vs
Input Frequency with Input Perturbation of 150% Full
Scale (50Hz Notch)
INPUT FREQUENCY (Hz)
0
NORMAL MODE REJECTION (dB)
2484 F38
0
20
40
60
80
100
120
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
T
A
= 25C
V
IN(P-P)
= 5V
V
IN(P-P)
= 7.5V
(150% OF FULL SCALE)
12.5
25
37.5
50
62.5
75
87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
Figure 39. Input Normal Mode Rejection 2x Speed Mode
Figure 40. Input Normal Mode Rejection 2x Speed Mode
Figure 41. Input Normal Mode Rejection vs Input Frequency,
2x Speed Mode and 50Hz/60Hz Mode
Figure 42. Input Normal Mode Rejection 2x Speed Mode
INPUT SIGNAL FREQUENCY (f
N
)
INPUT NORMAL REJECTION (dB)
2484 F39
0
20
40
60
80
100
120
0
f
N
2f
N
3f
N
4f
N
5f
N
6f
N
7f
N
8f
N
INPUT SIGNAL FREQUENCY (f
N
)
INPUT NORMAL REJECTION (dB)
2484 F40
0
20
40
60
80
100
120
250
248
252 254 256 258 260 262 264
INPUT FREQUENCY (Hz)
0
NORMAL MODE REJECTION (dB)
50
100 125
225
2484 F41
25
75
150 175 200
0
20
40
60
80
100
120
V
CC
= 5V
V
REF
= 5V
V
INCM
= 2.5V
V
IN(P-P)
= 5V
F
O
= GND
T
A
= 25C
MEASURED DATA
CALCULATED DATA
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
48
70
80
90
100
110
120
130
140
54
58
2484 F42
50
52
56
60
62
NORMAL MODE REJECTION (dB)
NO AVERAGE
WITH
RUNNING
AVERAGE
mode. Typical measured values of the normal mode
rejection of the LTC2484 operating with the internal oscil-
lator and 2x speed mode is shown in Figure 41.
When the LTC2484 is configured in 2x speed mode, by
performing a running average, a SINC
1
notch is combined
with the SINC
4
digital filter, yielding the normal mode
37
LTC2484
2484f
APPLICATIO S I FOR ATIO
W
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rejection identical as that for the 1x speed mode. The
averaging operation still keeps the output rate with the
following algorithm:
Result 1 = average (sample 0, sample 1)
Result 2 = average (sample 1, sample 2)
......
Result n = average (sample n 1, sample n)
The main advantage of the running average is that it
achieves simultaneous 50Hz/60Hz rejection at twice the
effective output rate, as shown in Figure 42. The raw
output data provides a better than 70dB rejection over
48Hz to 62.4Hz, which covers both 50Hz 2% and 60Hz
2%. With running average on, the rejection is better than
87dB for both 50Hz 2% and 60Hz 2%.
Complete Thermocouple Measurement System with
Cold Junction Compensation
The LTC2484 is ideal for direct digitization of thermocouples
and other low voltage output sensors. The input has a typical
offset error of 500nV (2.5V max) offset drift of 10nV/C
and a noise level of 600nV
RMS
.
Figure 44 (last page of this data sheet) is a complete type
K thermocouple meter. The only signal conditioning is a
simple surge protection network. In any thermocouple
meter, the cold junction temperature sensor must be at the
Figure 43. Calibration Setup
same temperature as the junction between the thermo-
couple materials and the copper printed circuit board
traces. The tiny LTC2484 can be tucked neatly underneath
an Omega MPJ-K-F thermocouple socket ensuring close
thermal coupling.
The LTC2484's 1.4mV/C PTAT circuit measures the cold
junction temperature. Once the thermocouple voltage and
cold junction temperature are known, there are many
ways of calculating the thermocouple temperature includ-
ing a straight-line approximation, lookup tables or a
polynomial curve fit. Calibration is performed by applying
an accurate 500mV to the ADC input derived from an
LT
1236 reference and measuring the local temperature
with an accurate thermometer as shown in Figure 43. In
calibration mode, the up and down buttons are used to
adjust the local temperature reading until it matches an
accurate thermometer. Both the voltage and temperature
calibration are easily automated.
The complete microcontroller code for this application is
available on the LTC2484 product webpage at:
http://www.linear.com
It can be used as a template for may different instruments
and it illustrates how to generate calibration coefficients
for the onboard temperature sensor. Extensive comments
detail the operation of the program. The read_LTC2484()
function controls the operation of the LTC2484 and is
listed below for reference.
CS
SCK
SDO
SDI
F
O
6
9
7
1
10
V
CC
5V
LTC2484
REF
GND
IN
IN
+
3
ISOTHERMAL
2
C7
0.1F
C8
1F
4
R2
2k
R7
8k
6
2
5
4
R8
1k
5
2484 F43
26.3C
TYPE K
THERMOCOUPLE
JACK
(OMEGA MPJ-K-F)
11
8
GND
IN OUT
G1
NC1M4V0
TRIM
GND
LT1236
+
38
LTC2484
2484f
APPLICATIO S I FOR ATIO
W
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/*** read_LTC2484() ************************************************************
This is the function that actually does all the work of talking to the LTC2484.
The spi_read() function performs an 8 bit bidirectional transfer on the SPI bus.
Data changes state on falling clock edges and is valid on rising edges, as
determined by the setup_spi() line in the initialize() function.
A good starting point when porting to other processors is to write your own
spi_write function. Note that each processor has its own way of configuring
the SPI port, and different compilers may or may not have built-in functions
for the SPI port. Also, since the state of the LTC2484's SDO line indicates
when a conversion is complete you need to be able to read the state of this line
through the processor's serial data input. Most processors will let you read
this pin as if it were a general purpose I/O line, but there may be some that
don't.
When in doubt, you can always write a "bit bang" function for troubleshooting
purposes.
The "fourbytes" structure allows byte access to the 32 bit return value:
struct fourbytes // Define structure of four consecutive bytes
{ // To allow byte access to a 32 bit int or float.
int8 te0; //
int8 te1; // The make32() function in this compiler will
int8 te2; // also work, but a union of 4 bytes and a 32 bit int
int8 te3; // is probably more portable.
};
Also note that the lower 4 bits are the configuration word from the previous
conversion. The 4 LSBs are cleared so that
they don't affect any subsequent mathematical operations. While you can do a
right shift by 4, there is no point if you are going to convert to floating point
numbers - just adjust your scaling constants appropriately.
*******************************************************************************/
signed int32 read_LTC2484(char config)
{
union // adc_code.bits32 all 32 bits
{ // adc_code.by.te0 byte 0
signed int32 bits32; // adc_code.by.te1 byte 1
struct fourbytes by; // adc_code.by.te2 byte 2
} adc_code; // adc_code.by.te3 byte 3
output_low(CS); // Enable LTC2484 SPI interface
while(input(PIN_C4)) {} // Wait for end of conversion. The longest
// you will ever wait is one whole conversion period
// Now is the time to switch any multiplexers because the conversion is finished
// and you have the whole data output time for things to settle.
adc_code.by.te3 = 0; // Set upper byte to zero.
adc_code.by.te2 = spi_read(config); // Read first byte, send config byte
adc_code.by.te1 = spi_read(0); // Read 2nd byte, send speed bit
adc_code.by.te0 = spi_read(0); // Read 3rd byte. `0' argument is necessary
// to act as SPI master!! (compiler
// and processor specific.)
output_high(CS); // Disable LTC2484 SPI interface
// Clear configuration bits and subtract offset. This results in
// a 2's complement 32 bit integer with the LTC2484's MSB in the 2^20 position
adc_code.by.te0 = adc_code.by.te0 & 0xF0;
adc_code.bits32 = adc_code.bits32 - 0x00200000;
return adc_code.bits32;
} // End of read_LTC2484()
39
LTC2484
2484f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
PACKAGE DESCRIPTIO
DD Package
10-Lead Plastic DFN (3mm 3mm)
(Reference LTC DWG # 05-08-1698)
3.00 0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.38 0.10
BOTTOM VIEW--EXPOSED PAD
1.65 0.10
(2 SIDES)
0.75 0.05
R = 0.115
TYP
2.38 0.10
(2 SIDES)
1
5
10
6
PIN 1
TOP MARK
(SEE NOTE 5)
0.200 REF
0.00 0.05
(DD10) DFN 0403
0.25 0.05
2.38 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 0.05
(2 SIDES)
2.15 0.05
0.50
BSC
0.675 0.05
3.50 0.05
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
40
LTC2484
2484f
LT/TP 0505 500 PRINTED IN THE USA
TYPICAL APPLICATIO
U
Figure 44. Complete Type K Thermocouple Meter
PART NUMBER
DESCRIPTION
COMMENTS
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5V Offset, 1.6V
P-P
Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max Initial Accuracy, 5ppm/C Drift
LT1460
Micropower Series Reference
0.075% Max Initial Accuracy, 10ppm/C Max Drift
LTC2400
24-Bit, No Latency ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A
LTC2401/LTC2402
1-/2-Channel, 24-Bit, No Latency ADCs in MSOP
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency ADCs
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A
with Differential Inputs
LTC2410
24-Bit, No Latency ADC with Differential Inputs
0.8V
RMS
Noise, 2ppm INL
LTC2411/LTC2411-1 24-Bit, No Latency ADCs with Differential Inputs in MSOP
1.45V
RMS
Noise, 4ppm INL,
Simultaneous 50Hz/60Hz Rejection (LTC2411-1)
LTC2413
24-Bit, No Latency ADC with Differential Inputs
Simultaneous 50Hz/60Hz Rejection, 800nV
RMS
Noise
LTC2415/
24-Bit, No Latency ADCs with 15Hz Output Rate
Pin Compatible with the LTC2410
LTC2415-1
LTC2414/LTC2418
8-/16-Channel 24-Bit, No Latency ADCs
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200A
LTC2420
20-Bit, No Latency ADC in SO-8
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2430/LTC2431
20-Bit, No Latency ADCs with Differential Inputs
2.8V Noise, SSOP-16/MSOP Package
LTC2435/LTC2435-1 20-Bit, No Latency ADCs with 15Hz Output Rate
3ppm INL, Simultaneous 50Hz/60Hz Rejection
LTC2440
High Speed, Low Noise 24-Bit ADC
3.5kHz Output Rate, 200mV Noise, 24.6 ENOBs
LTC2480
16-Bit, No Latency ADC with PGA/Temperature Sensor
Pin Compatible with LTC2484
LTC2482
16-Bit, No Latency ADC
Pin Compatible with LTC2484
RELATED PARTS
CS
SCK
SDO
SDI
F
O
6
9
7
1
10
18
17
16
15
14
13
12
11
28
27
26
25
24
23
22
21
7
6
5
4
3
2
V
CC
5V
LTC2484
REF
GND
IN
IN
+
3
ISOTHERMAL
2
C7
0.1F
C8
1F
C6
0.1F
4
R2
2k
5
TYPE K
THERMOCOUPLE
JACK
(OMEGA MPJ-K-F)
5V
5V
11
8
GND
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RA5
RA4
RA3
RA2
RA1
RA0
V
DD
OSC1
OSC2
MCLR
20
9
10
1
5V
5V
Y1
6MHz
R1
10k
D1
BAT54
V
SS
9
2484 F44
V
SS
19
PIC16F73
D7
D6
D5
D4
EN
RW
RS
R5
10k
R4
10k
R3
10k
R6
5k
2
1
3
2
1
5V
CALIBRATE
CONTRAST
GND D0
V
CC
D1 D2 D3
2 16 CHARACTER
LCD DISPLAY
(OPIREX DMC162488
OR SIMILAR)
DOWN
UP
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2005
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