LTC2605/LTC2615/LTC2625

2605f

Octal 16-/14-/12-Bit

Rail-to-Rail DACs in 16-Lead SSOP

The LTC

2605/LTC2615/LTC2625 are octal 16-, 14-

and 12-bit, 2.7V to 5.5V rail-to-rail voltage-output DACs in
16-lead narrow SSOP packages. They have built-in
high performance output buffers and are guaranteed
monotonic.

These parts establish new board-density benchmarks
for 16- and 14-bit DACs and advance performance
standards for output drive, crosstalk and load regulation
in single-supply, voltage-output multiples.

The parts use the 2-wire I

C compatible serial interface.

The LTC2605/LTC2615/LTC2625 operate in both the
standard mode (maximum clock rate of 100kHz) and the
fast mode (maximum clock rate of 400kHz).

The LTC2605/LTC2615/LTC2625 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise
less than 10mV above zero scale; and after power-up, they
stay at zero scale until a valid write and update take place.
The power-on reset circuit resets the LTC2605-1/
LTC2615-1/LTC2625-1 to midscale. The voltage output
stays at midscale until a valid write and update
takes place.

Smallest Pin-Compatible Octal DACs:
LTC2605: 16 Bits
LTC2615: 14 Bits
LTC2625: 12 Bits

Guaranteed Monotonic Over Temperature

400kHz I

C Interface

Wide 2.7V to 5.5V Supply Range

Low Power Operation: 250

µA per DAC at 3V

Individual Channel Power-Down to 1

µA, Max

Ultralow Crosstalk Between DACs (<10

µV)

High Rail-to-Rail Output Drive (

±15mA, Min)

Double-Buffered Digital Inputs

27 Selectable Addresses

LTC2605/LTC2615/LTC2625: Power-On Reset to
Zero Scale

LTC2605-1/LTC2615-1/LTC2625-1: Power-On Reset
to Midscale

Tiny 16-Lead Narrow SSOP Package

Mobile Communications

Process Control and Industrial Automation

Instrumentation

Automatic Test Equipment

Differential Nonlinearity (LTC2605)

APPLICATIO S

FEATURES

DESCRIPTIO

BLOCK DIAGRA

CODE

16384

32768

49152

65535

DNL (LSB)

2605 G02

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

= 5V

REF

= 4.096V

GND

OUT A

OUT B

OUT C

OUT D

REF

CA2

SCL

OUT H

OUT G

OUT F

OUT E

CA0

CA1

SDA

2605/15/25 BD

DAC A

2-WIRE INTERFACE

32-BIT SHIFT REGISTER

DAC H

DAC B

DAC G

DAC C

DAC F

DAC D

DAC E

, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.

LTC2605/LTC2615/LTC2625

2605f

BSOLUTE

ORDER PART NUMBER

PACKAGE/ORDER I FOR ATIO

Any Pin to GND ........................................... 0.3V to 6V
Any Pin to V

............................................. 6V to 0.3V

Maximum Junction Temperature .......................... 125

°C

Storage Temperature Range ................ 65

°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300

°C

TOP VIEW

GND

OUT A

OUT B

OUT C

OUT D

GN PACKAGE

16-LEAD PLASTIC SSOP

REF

CA2

SCL

OUT H

OUT G

OUT F

OUT E

CA0

CA1

SDA

JMAX

= 125

°C,

= 150

°C/W

LTC2605CGN
LTC2605CGN-1
LTC2605IGN
LTC2605IGN-1
LTC2615CGN
LTC2615CGN-1
LTC2615IGN
LTC2615IGN-1
LTC2625CGN
LTC2625CGN-1
LTC2625IGN
LTC2625IGN-1

Consult LTC Marketing for parts specified with wider operating temperature ranges.

2605
26051
2605I
26O5I1
2615
26151
2615I
2615I1
2625
26251
2625I
2625I1

(Note 1)

Operating Temperature Range

LTC2605C/LTC2615C/LTC2625C ............. 0

°C to 70°C

LTC2605C-1/LTC2615C-1/LTC2625C-1 ... 0

°C to 70°C

LTC2605I/LTC2615I/LTC2625I ............ 40

°C to 85°C

LTC2605I-1/LTC2615I-1/LTC2625I-1 .. 40

°C to 85°C

GN PART MARKING

ELECTRICAL C

HARA TERISTICS

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

°C. REF = 4.096V (V

= 5V), REF = 2.048V (V

= 2.7V), V

OUT

unloaded,

unless otherwise noted.

LTC2625/-1

LTC2615/-1

LTC2605/-1

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

DC Performance

Resolution

Bits

Monotonicity

(Note 2)

Bits

DNL

Differential Nonlinearity

(Note 2)

±0.5

±1

LSB

INL

Integral Nonlinearity

(Note 2)

±1

±4

±16

±18 ±64

LSB

Load Regulation

REF

= V

= 5V, Midscale

OUT

= 0mA to 15mA Sourcing

0.02 0.125

0.07

0.5

0.3

LSB/mA

OUT

= 0mA to 15mA Sinking

0.03 0.125

0.10

0.5

0.4

LSB/mA

REF

= V

= 2.7V, Midscale

OUT

= 0mA to 7.5mA Sourcing

0.04

0.25

0.15

0.6

LSB/mA

OUT

= 0mA to 7.5mA Sinking

0.07

0.25

0.20

0.8

LSB/mA

ZSE

Zero-Scale Error

Code = 0

1.7

Offset Error

(Note 4)

±1

±9

±1

±9

±1

±9

Temperature

±5

µV/°C

Coefficient

Gain Error

±0.1 ±0.7

%FSR

Gain Temperature

±8

ppm/

°C

Coefficient

LTC2605/LTC2615/LTC2625

2605f

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

°C. REF = 4.096V (V

= 5V), REF = 2.048V (V

= 2.7V), V

OUT

unloaded,

unless otherwise noted. (Note 9)

ELECTRICAL C

HARA TERISTICS

PSR

Power Supply Rejection

±10%

OUT

DC Output Impedance

REF

= V

= 5V, Midscale; 15mA

OUT

15mA

0.02

0.15

REF

= V

= 2.7V, Midscale; 7.5mA

OUT

7.5mA

0.03

0.15

DC Crosstalk (Note 10)

Due to Full Scale Output Change (Note 11)

±10

µV

Due to Load Current Change

±3.5

µV/mA

Due to Powering Down (per Channel)

±7

µV

Short-Circuit Output Current

= 5.5V, V

REF

= 5.5V

Code: Zero Scale; Forcing Output to V

Code: Full Scale; Forcing Output to GND

= 2.7V, V

REF

= 2.7V

Code: Zero Scale; Forcing Output to V

7.5

Code: Full Scale; Forcing Output to GND

7.5

Reference Input

Input Voltage Range

Resistance

Normal Mode

Capacitance

REF

Reference Current, Power Down Mode

DAC Powered Down

0.001

µA

Power Supply

Positive Supply Voltage

For Specified Performance

2.7

5.5

Supply Current

= 5V (Note 3)

2.50

4.0

= 3V (Note 3)

2.00

3.2

DAC Powered Down (Note 3) V

= 5V

0.38

1.0

µA

DAC Powered Down (Note 3) V

= 3V

0.16

1.0

µA

Digital I/O (Note 9)

Low Level Input Voltage

0.3V

(SDA and SCL)

High Level Input Voltage

0.7V

(SDA and SCL)

IL(CA)

Low Level Input Voltage (CA0 to CA2)

See Test Circuit 1

0.15V

IH(CA)

High Level Input Voltage (CA0 to CA2)

See Test Circuit 1

0.85V

INH

Resistance from CA

(n = 0,1,2)

See Test Circuit 2

to V

to Set CA

= V

INL

Resistance from CA

(n = 0,1,2)

See Test Circuit 2

to GND to Set CA

= GND

INF

Resistance from CA

(n = 0,1,2)

See Test Circuit 2

to V

or GND to Set CA

= FLOAT

Low Level Output Voltage

Sink Current = 3mA

0.4

Output Fall Time

= V

IH(MIN)

to V

= V

IL(MAX)

20 + 0.1C

250

= 10pF to 400pF (Note 7)

Pulse Width of Spikes Surpassed

by Input Filter

Input Leakage

0.1V

0.9V

µA

I/O Pin Capacitance

(Note 12)

Capacitance Load for Each Bus Line

400

CAn

External Capacitive Load on

Address Pins CA0, CA1 and CA2

LTC2605/LTC2615/LTC2625

2605f

TI I G CHARACTERISTICS

The

denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T

= 25

°C. (See Figure 1) (Notes 8, 9)

Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.

Note 2: Linearity and monotonicity are defined from code k

to code

1, where N is the resolution and k

is given by k

= 0.016(2

REF

rounded to the nearest whole code. For V

REF

= 4.096V and N = 16,

= 256 and linearity is defined from code 256 to code 65,535.

Note 3: SDA, SCL at 0V or V

, CA0, CA1 and CA2 floating.

Note 4: Inferred from measurement at code 256 (LTC2605/LTC2605-1),
code 64 (LTC2615/LTC2615-1) or code 16 (LTC2625/LTC2625-1) and
at full scale.

Note 5: V

= 5V, V

REF

= 4.096V. DAC is stepped 1/4 scale to 3/4 scale

and 3/4 scale to 1/4 scale. Load is 2k

in parallel with 200pF to GND.

Note 6: V

= 5V, V

REF

= 4.096V. DAC is stepped

±1LSB between half

scale and half scale 1. Load is 2k

in parallel with 200pF to GND.

Note 7: C

= capacitance of one bus line in pF.

Note 8: All values refer to V

IH(MIN)

and V

IL(MAX)

levels.

Note 9: These specifications apply to LTC2605/LTC2605-1, LTC2615/
LTC2615-1 and LTC2625/LTC2625-1.

Note 10: DC Crosstalk is measured with V

= 5V and V

REF

= 4096V, with

the measured DAC at midscale, unless otherwise noted.

Note 11: R

= 2k

to GND or V

Note 12: Guaranteed by design and not production tested.

ELECTRICAL C

HARA TERISTICS

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

°C. REF = 4.096V (V

= 5V), REF = 2.048V (V

= 2.7V), V

OUT

unloaded,

unless otherwise noted.

LTC2625/-1

LTC2615/-1

LTC2605/-1

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

AC Performance

Settling Time (Note 5)

±0.024% (±1LSB at 12 Bits)

µs

±0.006% (±1LSB at 14 Bits)

µs

±0.0015% (±1LSB at 16 Bits)

µs

Settling Time for 1LSB Step

±0.024% (±1LSB at 12 Bits)

2.7

µs

(Note 6)

±0.006% (±1LSB at 14 Bits)

4.8

µs

±0.0015% (±1LSB at 16 Bits)

5.2

µs

Voltage Output Slew Rate

0.80

µs

Capacitive Load Driving

1000

Glitch Impulse

At Midscale Transition

nV · s

Multiplying Bandwidth

180

kHz

Output Voltage Noise Density

At f = 1kHz

120

nV/

At f = 10kHz

100

nV/

Output Voltage Noise

0.1Hz to 10Hz

µV

P-P

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

= 2.7V to 5.5V

SCL

SCL Clock Frequency

400

kHz

HD(STA)

Hold Time (Repeated) Start Condition

0.6

µs

LOW

Low Period of the SCL Clock Pin

1.3

µs

HIGH

High Period of the SCL Clock Pin

0.6

µs

SU(STA)

Set-Up Time for a Repeated Start Program

0.6

µs

HD(DAT)

Data Hold Time

0.9

µs

SU(DAT)

Data Set-Up Time

100

Rise Time of Both SDA and SCL Signals

(Note 7)

20 + 0.1C

300

Fall Time of Both SDA and SCL Signals

(Note 7)

20 + 0.1C

300

SU(STO)

Set-Up Time for Stop Condition

0.6

µs

BUF

Bus Free Time Between a Stop and Start Condition

1.3

µs

LTC2605/LTC2615/LTC2625

2605f

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2605

Integal Nonlinearity (INL)

IH(CA

)

IL(CA

)

100

2605/15/25 EC01

ELECTRICAL C

HARA TERISTICS

Test Circuit 1

Test Circuit 2

CODE

16384

32768

49152

65535

INL (LSB)

2605 G01

= 5V

REF

= 4.096V

CODE

16384

32768

49152

65535

DNL (LSB)

2605 G02

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

= 5V

REF

= 4.096V

TEMPERATURE (

°C)

INL (LSB)

2605 G03

= 5V

REF

= 4.096V

INL (POS)

INL (NEG)

TEMPERATURE (

°C)

DNL (LSB)

2605 G04

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

= 5V

REF

= 4.096V

DNL (POS)

DNL (NEG)

REF

(V)

INL (LSB)

2605 G05

= 5.5V

INL (POS)

INL (NEG)

REF

(V)

DNL (LSB)

2605 G06

1.5

1.0

0.5

1.0

1.5

= 5.5V

DNL (POS)

DNL (NEG)

Differential Nonlinearity (DNL)

INL vs Temperature

DNL vs Temperature

INL vs V

REF

DNL vs V

REF

GND

INH

INL

INF

2605/15/25 EC02

LTC2605/LTC2615/LTC2625

2605f

LTC2625

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2605

Settling to

±1LSB

Settling of Full-Scale Step

µs/DIV

2605 G08

OUT

100

µV/DIV

SCR

2V/DIV

SETTLING TO

±1LSB

= 5V, V

REF

= 4.096V

CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS

12.3

µs

9TH CLOCK OF
3RD DATA BYTE

LTC2615

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Settling to

±1LSB

Settling to

±1LSB

CODE

4096

8192

12288

16383

INL (LSB)

2605 G09

= 5V

REF

= 4.096V

CODE

4096

8192

12288

16383

DNL (LSB)

2605 G10

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

= 5V

REF

= 4.096V

µs/DIV

2605 G11

OUT

100

µV/DIV

SCL

2V/DIV

= 5V, V

REF

= 4.096V

1/4-SCALE TO 3/4-SCALE STEP
R

= 2k, C

= 200pF

AVERAGE OF 2048 EVENTS

8.9

µs

9TH CLOCK
OF 3RD DATA
BYTE

CODE

1024

2048

3072

4095

INL (LSB)

2605 G12

2.0

1.5

1.0

0.5

1.0

1.5

2.0

= 5V

REF

= 4.096V

CODE

1024

2048

3072

4095

DNL (LSB)

2605 G13

= 5V

REF

= 4.096V

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

µs/DIV

2605 G14

OUT

1mV/DIV

SCL

2V/DIV

= 5V, V

REF

= 4.096V

1/4-SCALE TO 3/4-SCALE STEP
R

= 2k, C

= 200pF

AVERAGE OF 2048 EVENTS

6.8

µs

9TH CLOCK
OF 3RD DATA
BYTE

µs/DIV

2605 G07

OUT

100

µV/DIV

SCL

2V/DIV

= 5V, V

REF

= 4.096V

1/4-SCALE TO 3/4-SCALE STEP
R

= 2k, C

= 200pF

AVERAGE OF 2048 EVENTS

9.7

µs

9TH CLOCK
OF 3RD DATA
BYTE

LTC2605/LTC2615/LTC2625

2605f

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2605/LTC2615/LTC2625

Current Limiting

Gain Error vs Temperature

Offset Error vs V

Zero-Scale Error vs Temperature

Shutdown vs V

Gain Error vs V

Load Regulation

Offset Error vs Temperature

OUT

(mA)

40 30 20 10

OUT

(V)

2605 G15

0.10

0.08

0.06

0.04

0.02

0.04

0.06

0.08

0.10

REF

= V

= 5V

REF

= V

= 3V

REF

= V

= 5V

REF

= V

= 3V

CODE = MIDSCALE

OUT

(mA)

OUT

(mV)

2606 G16

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

REF

= V

= 5V

CODE = MIDSCALE

REF

= V

= 3V

TEMPERATURE (

°C)

OFFSET ERROR (mV)

2605 G17

TEMPERATURE (

°C)

ZERO-SCALE ERROR (mV)

2605 G18

2.5

2.0

1.5

1.0

0.5

TEMPERATURE (

°C)

GAIN ERROR (%FSR)

2605 G19

0.4

0.3

0.2

0.1

0.2

0.3

0.4

(V)

2.5

3.5

4.5

5.5

OFFSET ERROR (mV)

2605 G20

(V)

2.5

3.5

4.5

5.5

GAIN ERROR (%FSR)

2605 G21

0.4

0.3

0.2

0.1

0.2

0.3

0.4

(V)

2.5

3.5

4.5

5.5

(nA)

2605 G22

450

400

350

300

250

200

150

100

Large-Signal Response

2.5

µs/DIV

OUT

0.5V/DIV

2605 G23

REF

= V

= 5V

1/4-SCALE TO 3/4-SCALE

LTC2605/LTC2615/LTC2625

2605f

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2605/LTC2615/LTC2625

Midscale Glitch Impulse

Power-On Reset Glitch

Headroom at Rails
vs Output Current

OUT

10mV/DIV

SCL

2V/DIV

2.5

µs/DIV

2605 G24

TRANSITION FROM

MS-1 TO MS

TRANSITION FROM

MS TO MS-1

9TH CLOCK
OF 3RD DATA
BYTE

OUT

10mV/DIV

250

µs/DIV

2605 G25

1V/DIV

4mV PEAK

OUT

(mA)

OUT

(V)

2605 G26

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

5V SOURCING

3V SOURCING

3V SINKING

5V SINKING

Power-On Reset to Midscale

1V/DIV

500

µs/DIV

2605 G27

OUT

REF

= V

2605 G28

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

LOGIC VOLTAGE (V)

(mA)

= 5V

SWEEP SCL
AND SDA 0V
TO V

AND

TO 0V

Supply Current vs Logic Voltage

Multiplying Bandwidth

FREQUENCY (Hz)

2605 G29

10k

100k

= 5V

REF

(DC) = 2V

REF

(AC) = 0.2V

P-P

CODE = FULL SCALE

Short-Circuit Output Current vs
V

OUT

(Sinking)

Short-Circuit Output Current vs
V

OUT

(Sourcing)

Output Voltage Noise,
0.1Hz to 10Hz

OUT

µV/DIV

SECONDS

2605 G30

10mA/DIV

0mA

10mA

20mA

30mA

40mA

1V/DIV

2605 G31

= 5.5V

REF

= 5.6V

CODE = 0
V

OUT

SWEPT 0V TO V

10mA/DIV

0mA

10mA

20mA

30mA

40mA

50mA

1V/DIV

2605 G32

= 5.5V

REF

= 5.6V

CODE = FULL SCALE
V

OUT

SWEPT V

TO 0V

LTC2605/LTC2615/LTC2625

2605f

BLOCK DIAGRA

TI I G DIAGRA

Figure 1

GND

OUT A

OUT B

OUT C

OUT D

REF

CA2

SCL

OUT H

OUT G

OUT F

OUT E

CA0

CA1

SDA

2605/15/25 BD01

DAC A

2-WIRE INTERFACE

32-BIT SHIFT REGISTER

DAC

INPUT

DAC H

DAC B

DAC G

DAC C

DAC F

DAC D

DAC E

SDA

LOW

HD(STA)

ALL VOLTAGE LEVELS REFER TO V

IH(MIN)

AND V

IL(MAX)

LEVELS

HD(DAT)

SU(DAT)

SU(STA)

HD(STA)

SU(STO)

BUF

HIGH

SCL

2605/15/25 TD01

CTIO

GND (Pin 1): Analog Ground.

OUT A

to V

OUT H

(Pins 2-5 and 12-15): DAC Analog

Voltage Output. The output range is 0V to V

REF

REF (Pin 6): Reference Voltage Input. 0V

REF

CA2 (Pin 7): Chip Address Bit 2. Tie this pin to V

, GND

or leave it floating to select an I

C slave address for the part

(Table 2).

SCL (Pin 8): Serial Clock Input Pin. Data is shifted into the
SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current
source to V

SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This is
a high impedance pin while data is shifted in. It is an open-
drain N-channel output during acknowledgment. This pin
requires a pull-up resistor or current source to V

CA1 (Pin 10): Chip Address Bit 1. Tie this pin to V

, GND

or leave it floating to select an I

C slave address for the part

(Table 2).

CA0 (Pin 11): Chip Address Bit 0. Tie this pin to V

, GND

or leave it floating to select an I

C slave address for the part

(Table 2).

(Pin 16): Supply Voltage Input. 2.7V

5.5V.

LTC2605/LTC2615/LTC2625

2605f

Table 1.

COMMAND*

Write to Input Register n

Update (Power Up) DAC Register n

Write to Input Register n, Update (Power Up) All n

Write to and Update (Power Up) n

Power Down n

No Operation

*Address and command codes not shown are reserved and should not be used.

ADDRESS (n)*

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

DAC H

All DACs

where k is the decimal equivalent of the binary DAC input
code, N is the resolution and V

REF

is the voltage at REF

(Pin 6).

Serial Digital Interface

The LTC2605/LTC2615/LTC2625 communicate with a
host using the standard 2-wire digital interface. The
Timing Diagram (Figure 1) shows the timing relationship
of the signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
resistors or current sources are required on these lines.
The value of these pull-up resistors is dependent on the
power supply and can be obtained from the I

C specifica-

tions. For an I

C bus operating in the fast mode, an active

pull-up will be necessary if the bus capacitance is greater
than 200pF.

The LTC2605/LTC2615/LTC2625 are receive-only (slave)
devices. The master can write to the LTC2605/LTC2615/
LTC2625. The LTC2605/LTC2615/LTC2625 do not
respond to a read from the master.

The START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA from
high to low while SCL is high.

When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while SCL
is high. The bus is then free for communication with
another I

C device.

OPERATIO

Power-On Reset

The LTC2605/LTC2615/LTC2625 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2605-1/
LTC2615-1/LTC2625-1 set the voltage outputs to midscale
when power is first applied.

For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2605/
LTC2615/LTC2625 contain circuitry to reduce the
power-on glitch: the analog outputs typically rise less
than 10mV above zero scale during power on if the
power supply is ramped to 5V in 1ms or more. In general,
the glitch amplitude decreases as the power supply ramp
time is increased. See Power-On Reset Glitch in the
Typical Performance Characteristics section.

Power Supply Sequencing

The voltage at REF (Pin 6) should be kept within the range
0.3V

REF

+ 0.3V (see Absolute Maximum

Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V

(Pin 16) is in transition.

Transfer Function

The digital-to-analog transfer function is

OUT IDEAL

REF

(

)

LTC2605/LTC2615/LTC2625

2605f

OPERATIO

Acknowledge

The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
during the Acknowledge clock pulse so that it remains a
stable LOW during the HIGH period of this clock pulse. The
LTC2605/LTC2615/LTC2625 respond to a write by a mas-
ter in this manner. The LTC2605/LTC2615/LTC2625 do
not acknowledge a read (it retains SDA HIGH during the
period of the Acknowledge clock pulse).

Chip Address

The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set to
any one of three states: V

, GND or FLOAT. This results

in 27 selectable addresses for the part. The addresses
corresponding to the states of CA0, CA1 and CA2 and the
global address are shown in Table 2.

In addition to the address selected by the address pins, the
parts also respond to a global address. This address allows
a common write to all LTC2605, LTC2615 and LTC2625
parts to be accomplished with one 3-byte write transaction
on the I

C bus. The global address is a 7-bit hardwired

address and is not selectable by CA0, CA1 and CA2. The

maximum capacitive load allowed on the address pins
(CA0, CA1 and CA2) is 10pF.

Write Word Protocol

The master initiates communication with the LTC2605/
LTC2615/LTC2625 with a START condition and a 7-bit
slave address followed by the Write bit (W) = 0. The
LTC2605/LTC2615/LTC2625 acknowledges by pulling the
SDA pin low at the 9th clock if the 7-bit slave address
matches the address of the parts (set by CA0, CA1 and
CA2) or the global address. The master then transmits
three bytes of data. The LTC2605/LTC2615/LTC2625
acknowledges each byte of data by pulling the SDA line low
at the 9th clock of each data byte transmission. After
receiving three complete bytes of data, the LTC2605/
LTC2615/LTC2625 executes the command specified in
the 24-bit input word.

If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2605/LTC2615/LTC2625 do
not acknowledge the extra bytes of data (SDA is high
during the 9th clock).

The format of the three data bytes is shown in Figure 2. The first
byte of the input word consists of the 4-bit command and 4-
bit DAC address. The next two bytes consist of the 16-bit data
word. The 16-bit data word consists of the 16-, 14- or 12-bit
input code, MSB to LSB, followed by 0, 2 or 4 don't care bits
(LTC2605, LTC2615 and LTC2625 respectively). A typical I

write transaction is shown in Figure 3.

INPUT WORD

WRITE WORD PROTOCOL FOR LTC2605/LTC2615/LTC2625

INPUT WORD (LTC2605)

SLAVE ADDRESS

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

2605/2615/2625 O01

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

1ST DATA BYTE

2ND DATA BYTE

3RD DATA BYTE

C0 A3 A2 A1

D13

D14

D15

D12 D11 D10 D9

D7 D6

D1 D0

INPUT WORD (LTC2615)

C0 A3 A2 A1

D11

D12

D13

D10 D9

D5 D4

INPUT WORD (LTC2625)

C0 A3 A2 A1

D10

D11

D3 D2

Figure 2

LTC2605/LTC2615/LTC2625

2605f

The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The first four commands in the table
consist of write and update operations. A write operation
loads the 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path and
registers are shown in the block diagram.

Table 2. Slave Address Map

CA2

CA1

CA0

SA6

SA5

SA4

SA3

SA2

SA1

SA0

GND

FLOAT

GND

FLOAT

GND

FLOAT FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT FLOAT

GND

FLOAT FLOAT FLOAT

FLOAT FLOAT

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT FLOAT

FLOAT

GND

FLOAT

GLOBAL ADDRESS

Power Down Mode

For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than eight outputs are needed. When in power-down, the
buffer amplifiers and reference inputs are disabled and
draw essentially zero current. The DAC outputs are put into
a high-impedance state, and the output pins are passively
pulled to ground through individual 90k resistors. When
all eight DACs are powered down, the bias generation
circuit is also disabled. Input- and DAC- registers are not
disturbed during power-down.

Any channel or combination of channels can be put into
power-down mode by using command 0100

combination with the appropriate DAC address, (n). The
16-bit data word is ignored. The supply and reference
currents are reduced by approximately 1/8 for each DAC
powered down; the effective resistance at REF (Pin 6) rises
accordingly, becoming a high-impedance input (typically
>1G

) when all eight DACs are powered down.

Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 1.
The selected DAC is powered up as its voltage output
is updated.

There is an initial delay as the DAC powers up before it
begins its usual settling behavior. If less than eight DACs
are in a powered-down state prior to the updated
command, the power-up delay is 5

µs. If, on the other

hand, all eight DACs are powered down, then the bias
generation circuit is also disabled and must be restarted.
In this case, the power-up delay is greater: 12

µs for

= 5V, 30

µs for V

= 3V.

Voltage Outputs

Each of the eight rail-to-rail amplifiers contained in these
parts has guaranteed load regulation when sourcing or
sinking up to 15mA at 5V (7.5mA at 3V).

Load regulation is a measure of the amplifier's ability
to maintain the rated voltage accuracy over a wide range
of load conditions. The measured change in output voltage
per milliampere of forced load current change is
expressed in LSB/mA.

OPERATIO

LTC2605/LTC2615/LTC2625

2605f

DC output impedance is equivalent to load regulation and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifier's DC output
impedance is 0.020

when driving a load well away from

the rails.

When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by the
30

typical channel resistance of the output devices;

e.g., when sinking 1mA, the minimum output voltage =
30

· 1mA = 30mV. See the graph Headroom at Rails vs

Output Current in the Typical Performance Characteristics
section.

The amplifiers are stable driving capacitive loads of up
to 1000pF.

Board Layout

The excellent load regulation and DC crosstalk perfor-
mance of these devices is achieved in part by keeping
"signal" and "power" grounds separated internally and by
reducing shared internal resistance to just 0.005

The GND pin functions both as the node to which the
reference and output voltages are referred and as a return
path for power currents in the device. Because of this,
careful thought should be given to the grounding scheme
and board layout in order to ensure rated performance.

The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each other.

OPERATIO

Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device's ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continu-
ous and uninterrupted plane, except for necessary lead
pads and vias, with signal traces on another layer.

The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. Resistance here will
add directly to the effective DC output impedance of the
device (typically 0.020

), and will degrade DC crosstalk.

Note that the LTC2605/LTC2615/LTC2625 are no more
susceptible to these effects than other parts of their type;
on the contrary, they allow layout-based performance
improvements to shine rather than limiting attainable
performance with excessive internal resistance.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.

Since the analog outputs of the device cannot go below
ground, they may limit for the lowest codes as shown in
Figure 4b. Similarly, limiting can occur near full scale
when the REF pin is tied to V

. If V

REF

= V

and the DAC

full-scale error (FSE) is positive, the output for the highest
codes limits at V

as shown in Figure 4c. No full-scale

limiting can occur if V

REF

is less than V

FSE.

Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting
can occur.

LTC2605/LTC2615/LTC2625

2605f

PACKAGE DESCRIPTIO

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function, (b) Effect
of Negative Offset for Codes Near Zero Scale, (c) Effect of Positive Full-Scale Error for Codes Near Full Scale

OPERATIO

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

2605/15/25 O05

INPUT CODE

(b)

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

32, 768

65, 535

INPUT CODE

OUTPUT

VOLTAGE

(a)

REF

= V

REF

= V

(c)

INPUT CODE

OUTPUT
VOLTAGE

POSITIVE
FSE

GN16 (SSOP) 0502

.229 .244

(5.817 6.198)

.150 .157**

(3.810 3.988)

16 15 14 13

.189 .196*

(4.801 4.978)

12 11 10 9

.016 .050

(0.406 1.270)

.015 .004

(0.38 0.10)

× 45°

0 8 TYP

.007 .0098

(0.178 0.249)

.053 .068

(1.351 1.727)

.008 .012

(0.203 0.305)

.004 .0098

(0.102 0.249)

.0250

(0.635)

BSC

.009

(0.229)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 .165

.0250 TYP

.0165 .0015

.045 .005

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:
1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

LTC2605/LTC2615/LTC2625

2605f

PART NUMBER

DESCRIPTION

COMMENTS

LTC1458/LTC1458L

Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality

LTC1458: V

= 4.5V to 5.5V, V

OUT

= 0V to 4.096V

LTC1458L: V

= 2.7V to 5.5V, V

OUT

= 0V to 2.5V

LTC1654

Dual 14-Bit Rail-to-Rail V

OUT

DAC

Programmable Speed/Power, 3.5

µs/750µA, 8µs/450µA

LTC1655/LTC1655L

Single 16-Bit V

OUT

DAC with Serial Interface in SO-8

= 5V(3V), Low Power, Deglitched

LTC1657/LTC1657L

Parrallel 5V/3V 16-Bit V

OUT

DAC

Low Power, Deglitched, Rail-to-Rail V

OUT

LTC1660/LTC1665

Octal 10-/8-Bit V

OUT

DAC in 16-Pin Narrow SSOP

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

LTC1821

Parallel 16-Bit Voltage Output DAC

Precision 16-Bit Settling in 2

µs for 10V Step

LTC2600/LTC2610/

Octal 16-/14-/12-Bit V

OUT

DACs in 16-Lead SSOP

250

µA per DAC, 2.5V5.5V Supply Range, Rail-to-Rail

LTC2620

Output, SPI Interface

LTC2601/LTC2611/

Single 16-/14-/12-Bit V

OUT

DACs in 10-Lead DFN

300

µA per DAC, 2.5V5.5V Supply Range, Rail-to-Rail

LTC2621

Output, SPI Interface

LTC2602/LTC2612/

Dual 16-/14-/12-Bit V

OUT

DACs in 8-Lead MSOP

300

µA per DAC, 2.5V5.5V Supply Range, Rail-to-Rail

LTC2622

Output, SPI Interface

LTC2604/LTC2614/

Quad 16-/14-/12-Bit V

OUT

DACs in 16-Lead SSOP

250

µA per DAC, 2.5V5.5V Supply Range, Rail-to-Rail

LTC2624

Output, SPI Interface

LTC2606/LTC2616/

Single 16-/14-/12-Bit V

OUT

DACs with I

C Interface in 10-Lead DFN

270

µA per DAC, 2.7V5.5V Supply Range, Rail-to-Rail

LTC2626

Output, I

C Interface

LT/LWI/TP 0405 500 · PRINTED IN THE USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear.com

RELATED PARTS

TYPICAL APPLICATIO

DISABLE
ADC

4.096V

10k

SCK

SPI
BUS

REF

7.5k

DAC OUTPUTS

7.5k

C10

100pF

R8
22

TP4
DAC B

LT1461ACS8-4

GND

OUT

SHDN

TP5
DAC C

TP6
DAC D

TP7
DAC E

U3
LTC2428CG

2605 TA01

CH4

CH3

GND

SET

GND

MUXOUT

CH0

CH1

CH6

ADCIN

REF

CH2

CH5

CH7

GND

CLK

CSMUX

GND

CSADC

SD0

SCK

GND GND

GND

JP1
ON/OFF

0.1

µF

0.1

µF

C5
0.1

µF

C4
0.1

µF

TP8
DAC F

TP9
DAC G

TP3
DAC A

JP2
V

REF

TP10
DAC H

U2
LTC2605CGN

BUS

OUT

GND

OUT

REF

SDA

SCL

OUT

CA2

CA1

CA0

OUT

4-/8-CHANNEL

MUX

ADDRESS SELECTION

7.5k

20-BIT

ADC

TP13
GND

TP11
V

REF

C8
1

µF

16V

C9
0.1

µF

LT1236ACS8-5

GND

OUT

C6
0.1

µF

C7
4.7

µF

6.3V

REGULATOR

REF

JP3
V

TP12
V

Demonstration Circuit--LTC2428 20-Bit ADC Measures Key Performance Parameters

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC2605