LTC2606/LTC2616/LTC2626

26061626f

16-/14-/12-Bit Rail-to-Rail DACs

with I

C Interface

The LTC

2606/LTC2616/LTC2626 are single 16-, 14-

and 12-bit, 2.7V-to-5.5V rail-to-rail voltage output DACs
in a 10-lead DFN package. They have built-in high perfor-
mance output buffers and are guaranteed monotonic.

These parts establish new board-density benchmarks for
16- and 14-bit DACs and advance performance standards
for output drive and load regulation in single-supply,
voltage-output DACs.

The parts use a 2-wire, I

C compatible serial interface. The

LTC2606/LTC2616/LTC2626 operate in both the standard
mode (clock rate of 100kHz) and the fast mode (clock rate
of 400kHz). An asynchronous DAC update pin (LDAC) is
also included.

The LTC2606/LTC2616/LTC2626 incorporate a power-on
reset circuit. During power-up, the voltage outputs rise less
than 10mV above zero scale; and after power-up, they stay
at zero scale until a valid write and update take place. The
power-on reset circuit resets the LTC2606-1/LTC2616-1/
LTC2626-1 to midscale. The voltage outputs stay at
midscale until a valid write and update take place.

Smallest Pin-Compatible Single DACs:
LTC2606: 16 Bits
LTC2616: 14 Bits
LTC2626: 12 Bits

Guaranteed 16-Bit Monotonic Over Temperature

27 Selectable Addresses

400kHz I

Interface

Wide 2.7V to 5.5V Supply Range

Low Power Operation: 270µA at 3V

Power Down to 1µA, Max

High Rail-to-Rail Output Drive (±15mA, Min)

Double-Buffered Data Latches

Asynchronous DAC Update Pin

LTC2606/LTC2616/LTC2626: Power-On Reset to
Zero Scale

LTC2606-1/LTC2616-1/LTC2626-1: Power-On Reset
to Midscale

Tiny (3mm × 3mm) 10-Lead DFN Package

Mobile Communications

Process Control and Industrial Automation

Instrumentation

Automatic Test Equipment

Differential Nonlinearity

(LTC2606)

APPLICATIO S

FEATURES

DESCRIPTIO

BLOCK DIAGRA

CODE

16384

32768

49152

65535

DNL (LSB)

2606 G02

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

= 5V

REF

= 4.096V

DAC

INPUT

INTERFACE

16-BIT DAC

OUT

CONTROL

LOGIC

ADDRESS

DECODE

LDAC

SCL

SDA

CA0

CA1

CA2

2606 BD

GND

REF

, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.

LTC2606/LTC2616/LTC2626

26061626f

BSOLUTE

ORDER PART

NUMBER

PACKAGE/ORDER I FOR ATIO

JMAX

= 125°C,

= 43°C/W

EXPOSED PAD (PIN 11) IS GND

MUST BE SOLDERED TO PCB

Any Pin to GND ........................................... 0.3V to 6V
Any Pin to V

............................................. 6V to 0.3V

Maximum Junction Temperature ......................... 125°C
Storage Temperature Range ................ 65°C to 125°C
Lead Temperature (Soldering, 10 sec)................ 300°C

DD PART MARKING

LTC2606CDD
LTC2606IDD

LAJX

Consult LTC Marketing for parts specified with wider operating temperature ranges.

TOP VIEW

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

LDAC

GND

OUT

REF

CA2

SDA

SCL

CA0

CA1

(Note 1)

Operating Temperature Range:

LTC2606C/LTC2616C/LTC2626C
LTC2606-1C/LTC2616-1C/LTC2626-1C ... 0°C to 70°C
LTC2606I/LTC2616I/LTC2626I
LTC2606-1I/LTC2616-1I/LTC2626-1I .. 40°C to 85°C

ORDER PART

NUMBER

DD PART MARKING

LTC2616CDD
LTC2616IDD

ORDER PART

NUMBER

DD PART MARKING

LTC2626CDD
LTC2626IDD

ELECTRICAL C

HARA TERISTICS

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25°C. REF = 4.096V (V

= 5V), REF = 2.048V (V

= 2.7V), V

OUT

unloaded,

unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

DC Performance

Resolution

Bits

Monotonicity

(Note 2)

Bits

DNL

Differential Nonlinearity

(Note 2)

±0.5

±1

LSB

INL

Integral Nonlinearity

(Note 2)

±1

±4

±16

±14

±64

LSB

Load Regulation

REF

= V

= 5V, Midscale

OUT

= 0mA to 15mA Sourcing

0.025 0.125

0.1

0.5

LSB/mA

OUT

= 0mA to 15mA Sinking

0.05 0.125

0.2

0.5

0.7

LSB/mA

REF

= V

= 2.7V, Midscale

OUT

= 0mA to 7.5mA Sourcing

0.05

0.25

0.2

0.9

LSB/mA

OUT

= 0mA to 7.5mA Sinking

0.1

0.25

0.4

1.5

LSB/mA

ZSE

Zero-Scale Error

Code = 0

Offset Error

(Note 5)

±1

±9

±1

±9

±1

±9

Temperature

±5

µV/°C

Coefficient

Gain Error

±0.1

±0.7

±0.1

±0.7

±0.1

±0.7

%FSR

Gain Temperature

±8.5

ppm/°C

Coefficient

LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1

LTC2606CDD-1
LTC2606IDD-1

LAJW

LBPQ

LBPR

LBPS

LBPT

LTC2616CDD-1
LTC2616IDD-1

LTC2626CDD-1
LTC2626IDD-1

LTC2606/LTC2616/LTC2626

26061626f

ELECTRICAL C

HARA TERISTICS

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25°C. REF = 4.096V (V

= 5V), REF = 2.048V (V

= 2.7V), V

OUT

unloaded,

unless otherwise noted. (Note 11)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PSR

Power Supply Rejection

= ±10%

OUT

DC Output Impedance

REF

= V

= 5V, Midscale; 15mA I

OUT

15mA

0.05

0.15

REF

= V

= 2.7V, Midscale; 7.5mA I

OUT

7.5mA

0.06

0.15

Short-Circuit Output Current

= 5.5V, V

REF

= 5.5V

Code: Zero Scale; Forcing Output to V

Code: Full Scale; Forcing Output to GND

= 2.7V, V

REF

= 2.7V

Code: Zero Scale; Forcing Output to V

7.5

Code: Full Scale; Forcing Output to GND

7.5

Reference Input

Input Voltage Range

Resistance

Normal Mode

124

160

Capacitance

REF

Reference Current, Power Down Mode

DAC Powered Down

0.001

µA

Power Supply

Positive Supply Voltage

For Specified Performance

2.7

5.5

Supply Current

= 5V (Note 3)

0.340

0.5

= 3V (Note 3)

0.27

0.4

DAC Powered Down (Note 3) V

= 5V

0.35

µA

DAC Powered Down (Note 3) V

= 3V

0.10

µA

Digital I/O (Note 11)

Low Level Input Voltage

0.5

0.3V

(SDA and SCL)

High Level Input Voltage

(Note 8)

0.7V

(SDA and SCL)

IL(LDAC)

Low Level Input Voltage (LDAC)

= 4.5V to 5.5V

0.8

= 2.7V to 5.5V

0.6

IH(LDAC)

High Level Input Voltage (LDAC)

= 2.7V to 5.5V

2.4

= 2.7V to 3.6V

2.0

IL(CA

)

Low Level Input Voltage on CA

See Test Circuit 1

0.15V

(

n = 0, 1, 2)

IH(CA

)

High Level Input Voltage on CA

See Test Circuit 1

0.85V

(

n = 0, 1, 2)

INH

Resistance from CA

n (n = 0, 1, 2)

See Test Circuit 2

to V

to Set CA

n = V

INL

Resistance from CA

n (n = 0, 1, 2)

See Test Circuit 2

to GND to Set CA

n = GND

INF

Resistance from CA

n (n = 0, 1, 2)

See Test Circuit 2

to V

or GND to Set CA

n = Float

Low Level Output Voltage

Sink Current = 3mA

0.4

Output Fall Time

= V

IH(MIN)

to V

= V

IL(MAX)

20 + 0.1C

250

= 10pF to 400pF (Note 9)

Pulse Width of Spikes Suppressed

by Input Filter

Input Leakage

0.1V

0.9V

µA

I/O Pin Capacitance

Capacitive Load for Each Bus Line

400

CAX

External Capacitive Load on Address

Pins CA

n (n = 0, 1, 2)

LTC2606/LTC2616/LTC2626

26061626f

TI I G CHARACTERISTICS

The

denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T

= 25°C. (See Figure 1) (Notes 10, 11)

ELECTRICAL C

HARA TERISTICS

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25°C. REF = 4.096V (V

= 5V), REF = 2.048V (V

= 2.7V), V

OUT

unloaded,

unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

AC Performance

Settling Time (Note 6)

±0.024% (±1LSB at 12 Bits)

µs

±0.006% (±1LSB at 14 Bits)

µs

±0.0015% (±1LSB at 16 Bits)

µs

Settling Time for 1LSB Step

±0.024% (±1LSB at 12 Bits)

2.7

µs

(Note 7)

±0.006% (±1LSB at 14 Bits)

4.8

µs

±0.0015% (±1LSB at 16 Bits)

5.2

µs

Voltage Output Slew Rate

0.75

V/µs

Capacitive Load Driving

1000

Glitch Impulse

At Midscale Transition

nV · s

Multiplying Bandwidth

180

kHz

Output Voltage Noise Density

At f = 1kHz

120

nV/Hz

At f = 10kHz

100

nV/Hz

Output Voltage Noise

0.1Hz to 10Hz

µV

P-P

Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.

Note 2: Linearity and monotonicity are defined from code k

to code

1, where N is the resolution and k

is given by k

= 0.016(2

REF

rounded to the nearest whole code. For V

REF

= 4.096V and N = 16, k

256 and linearity is defined from code 256 to code 65,535.

Note 3: Digital inputs at 0V or V

Note 4: Guaranteed by design and not production tested.

Note 5: Inferred from measurement at code 256 (LTC2606/LTC2606-1),
code 64 (LTC2616/LTC2616-1) or code 16 (LTC2626/LTC2626-1) and at
full scale.

Note 6: V

= 5V, V

REF

= 4.096V. DAC is stepped 1/4 scale to 3/4 scale

and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.

Note 7: V

= 5V, V

REF

= 4.096V. DAC is stepped ±1LSB between half

scale and half scale 1. Load is 2k in parallel with 200pF to GND.

Note 8: Maximum V

= V

CC(MAX)

+ 0.5V

Note 9: C

= capacitance of one bus line in pF.

Note 10: All values refer to V

IH(MIN)

and V

IL(MAX)

levels.

Note 11: These specifications apply to LTC2606/LTC2606-1,
LTC2616/LTC2616-1, LTC2626/LTC2626-1.

LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

= 2.7V to 5.5V

SCL

SCL Clock Frequency

400

kHz

HD(STA)

Hold Time (Repeated) Start Condition

0.6

µs

LOW

Low Period of the SCL Clock Pin

1.3

µs

HIGH

High Period of the SCL Clock Pin

0.6

µs

SU(STA)

Set-Up Time for a Repeated Start Condition

0.6

µs

HD(DAT)

Data Hold Time

0.9

µs

SU(DAT)

Data Set-Up Time

100

Rise Time of Both SDA and SCL Signals

(Note 9)

20 + 0.1C

300

Fall Time of Both SDA and SCL Signals

(Note 9)

20 + 0.1C

300

SU(STO)

Set-Up Time for Stop Condition

0.6

µs

BUF

Bus Free Time Between a Stop and Start Condition

1.3

µs

Falling Edge of 9th Clock of the 3rd Input Byte

400

to LDAC High or Low Transition

LDAC Low Pulse Width

LTC2606/LTC2616/LTC2626

26061626f

TYPICAL PERFOR A CE CHARACTERISTICS

LTC2606

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

INL vs Temperature

DNL vs Temperature

INL vs V

REF

DNL vs V

REF

CODE

16384

32768

49152

65535

INL (LSB)

2606 G01

= 5V

REF

= 4.096V

CODE

16384

32768

49152

65535

DNL (LSB)

2606 G02

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

= 5V

REF

= 4.096V

TEMPERATURE (°C)

INL (LSB)

2606 G03

= 5V

REF

= 4.096V

INL (POS)

INL (NEG)

TEMPERATURE (°C)

DNL (LSB)

2606 G04

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

= 5V

REF

= 4.096V

DNL (POS)

DNL (NEG)

REF

(V)

INL (LSB)

2606 G05

= 5.5V

INL (POS)

INL (NEG)

REF

(V)

DNL (LSB)

2606 G06

1.5

1.0

0.5

1.0

1.5

= 5.5V

DNL (POS)

DNL (NEG)

Settling to ±1LSB

Settling of Full-Scale Step

2µs/DIV

2606 G07

OUT

100µV/DIV

SCL

2V/DIV

= 5V, V

REF

= 4.096V

1/4-SCALE TO 3/4-SCALE STEP
R

= 2k, C

= 200pF

AVERAGE OF 2048 EVENTS

9.7µs

9TH CLOCK
OF 3RD DATA
BYTE

5µs/DIV

2606 G08

OUT

100µV/DIV

SCR

2V/DIV

SETTLING TO ±1LSB
V

= 5V, V

REF

= 4.096V

CODE 512 TO 65535 STEP
AVERAGE OF 2048 EVENTS

12.3µs

9TH CLOCK OF
3RD DATA BYTE

LTC2606/LTC2616/LTC2626

26061626f

TYPICAL PERFOR A CE CHARACTERISTICS

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

LTC2626

LTC2616

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Settling to ±1LSB

CODE

4096

8192

12288

16383

INL (LSB)

2606 G09

= 5V

REF

= 4.096V

CODE

4096

8192

12288

16383

DNL (LSB)

2606 G10

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

= 5V

REF

= 4.096V

2µs/DIV

2606 G11

OUT

100µV/DIV

SCL

2V/DIV

= 5V, V

REF

= 4.096V

1/4-SCALE TO 3/4-SCALE STEP
R

= 2k, C

= 200pF

AVERAGE OF 2048 EVENTS

8.9µs

9TH CLOCK
OF 3RD DATA
BYTE

CODE

1024

2048

3072

4095

INL (LSB)

2606 G12

2.0

1.5

1.0

0.5

1.0

1.5

2.0

= 5V

REF

= 4.096V

CODE

1024

2048

3072

4095

DNL (LSB)

2606 G13

= 5V

REF

= 4.096V

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

2µs/DIV

2606 G14

OUT

1mV/DIV

SCL

2V/DIV

= 5V, V

REF

= 4.096V

1/4-SCALE TO 3/4-SCALE STEP
R

= 2k, C

= 200pF

AVERAGE OF 2048 EVENTS

6.8µs

9TH CLOCK
OF 3RD DATA
BYTE

LTC2606/LTC2616/LTC2626

26061626f

TYPICAL PERFOR A CE CHARACTERISTICS

Gain Error vs Temperature

Offset Error vs V

Zero-Scale Error vs Temperature

Shutdown vs V

Gain Error vs V

LTC2606/LTC2616/LTC2626

TEMPERATURE (°C)

ZERO-SCALE ERROR (mV)

2606 G20

2.5

2.0

1.5

1.0

0.5

TEMPERATURE (°C)

GAIN ERROR (%FSR)

2606 G21

0.4

0.3

0.2

0.1

0.2

0.3

0.4

(V)

2.5

3.5

4.5

5.5

OFFSET ERROR (mV)

2606 G22

(V)

2.5

3.5

4.5

5.5

GAIN ERROR (%FSR)

2606 G23

0.4

0.3

0.2

0.1

0.2

0.3

0.4

(V)

2.5

3.5

4.5

5.5

(nA)

2606 G24

450

400

350

300

250

200

150

100

Current Limiting

Load Regulation

Offset Error vs Temperature

OUT

(mA)

40 30 20 10

OUT

(V)

2606 G17

0.10

0.08

0.06

0.04

0.02

0.04

0.06

0.08

0.10

REF

= V

= 5V

REF

= V

= 3V

REF

= V

= 5V

REF

= V

= 3V

CODE = MIDSCALE

OUT

(mA)

OUT

(mV)

2606 G18

1.0

0.8

0.6

0.4

0.2

0.4

0.6

0.8

1.0

REF

= V

= 5V

CODE = MIDSCALE

REF

= V

= 3V

TEMPERATURE (°C)

OFFSET ERROR (mV)

2606 G19

LTC2606/LTC2616/LTC2626

26061626f

TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current vs Logic Voltage

LTC2606/LTC2616/LTC2626

Midscale Glitch Impulse

Power-On Reset Glitch

Headroom at Rails
vs Output Current

OUT

10mV/DIV

SCL

2V/DIV

2.5µs/DIV

2606 G26

TRANSITION FROM

MS-1 TO MS

TRANSITION FROM

MS TO MS-1

9TH CLOCK
OF 3RD DATA
BYTE

OUT

(mA)

OUT

(V)

2606 G28

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

5V SOURCING

3V SOURCING

3V SINKING

5V SINKING

OUT

10mV/DIV

250µs/DIV

2606 G27

1V/DIV

4mV PEAK

Large-Signal Response

2.5µs/DIV

OUT

0.5V/DIV

2606 G25

REF

= V

= 5V

1/4-SCALE TO 3/4-SCALE

1V/DIV

500µs/DIV

2606 G29

OUT

REF

= V

Power-On Reset to Midscale

LOGIC VOLTAGE (V)

(

650

600

550

500

450

400

350

300

250

2606 G30

3.5

0.5

1.5

2.5

4.5

= 5V

SWEEP LDAC
0V TO V

LOGIC VOLTAGE (V)

(

0.8

1.0

1.2

2606 G31

0.6

0.4

0.7

0.9

1.1

0.5

0.3

0.2

0.5

1.5

3.5

4.5

2.5

HYSTERESIS

370mV

= 5V

SWEEP SCL AND
SDA 0V TO V

AND V

TO 0V

Supply Current vs Logic Voltage

LTC2606/LTC2616/LTC2626

26061626f

CTIO

CA2 (Pin 1): Chip Address Bit 2. Tie this pin to V

, GND

or leave it floating to select an I

C slave address for the part

(Table 1).

SDA (Pin 2): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance while data is shifted in. Open drain
N-channel output during acknowledgment. SDA requires
a pull-up resistor or current source to V

SCL (Pin 3): Serial Clock Input Pin. Data is shifted into the
SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current source
to V

CA0 (Pin 4): Chip Address Bit 0. Tie this pin to V

, GND

or leave it floating to select an I

C slave address for the part

(Table 1).

CA1 (Pin 5): Chip Address Bit 1. Tie this pin to V

, GND

or leave it floating to select an I

C slave address for the part

(Table 1).

REF (Pin 6): Reference Voltage Input. 0V V

REF

OUT

(Pin 7): DAC Analog Voltage Output. The output

range is 0V to V

REF

GND (Pin 8): Analog Ground.

(Pin 9): Supply Voltage Input. 2.7V V

5.5V.

LDAC (Pin 10): Asynchronous DAC Update. A falling edge
on this input after four bytes have been written into the part
immediately updates the DAC register with the contents of
the input register. A low on this input without a complete
32-bit (four bytes including the slave address) data write
transfer to the part does not update the DAC output.
Software power-down is disabled when LDAC is low.

Exposed Pad (Pin 11): Ground. Must be soldered to PCB
ground.

LTC2606/LTC2616/LTC2626

26061626f

power supply and can be obtained from the I

C specifica-

tions. For an I

C bus operating in the fast mode, an active

pull-up will be necessary if the bus capacitance is greater
than 200pF.

The LTC2606/LTC2616/LTC2626 are receive-only (slave)
devices. The master can write to the LTC2606/LTC2616/
LTC2626. The LTC2606/LTC2616/LTC2626 do not re-
spond to a read from the master.

The START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA from
high to low while SCL is high.

When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while SCL
is high. The bus is then free for communication with
another I

C device.

Acknowledge

The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge re-
lated clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
bus line during the Acknowledge clock pulse so that it
remains a stable LOW during the HIGH period of this clock
pulse. The LTC2606/LTC2616/LTC2626 respond to a
write by a master in this manner. The LTC2606/LTC2616/
LTC2626 do not acknowledge a read (retains SDA HIGH
during the period of the Acknowledge clock pulse).

Chip Address

The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set to
any one of three states: V

, GND or float. This results in

27 selectable addresses for the part. The slave address
assignments are shown in Table 1.

OPERATIO

Power-On Reset

The LTC2606/LTC2616/LTC2626 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2606-1/
LTC2616-1/LTC2626-1 set the voltage outputs to midscale
when power is first applied.

For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2606/
LTC2616/LTC2626 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.

Power Supply Sequencing

The voltage at REF (Pin 6) should be kept within the range
0.3V V

REF

+ 0.3V (see Absolute Maximum

Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V

(Pin 9) is in transition.

Transfer Function

The digital-to-analog transfer function is:

OUT IDEAL

REF

(

)

where k is the decimal equivalent of the binary DAC input
code, N is the resolution and V

REF

is the voltage at REF

(Pin 6).

Serial Digital Interface

The LTC2606/LTC2616/LTC2626 communicate with a host
using the standard 2-wire I

C interface. The Timing Dia-

grams (Figures 1 and 2) show the timing relationship of
the signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
resistors or current sources are required on these lines.
The value of these pull-up resistors is dependent on the

LTC2606/LTC2616/LTC2626

26061626f

OPERATIO

Table 1. Slave Address Map

CA2

CA1

CA0

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GND

FLOAT

GLOBAL ADDRESS

In addition to the address selected by the address pins, the
parts also respond to a global address. This address
allows a common write to all LTC2606, LTC2616 and
LTC2626 parts to be accomplished with one 3-byte write
transaction on the I

C bus. The global address is a 7-bit

on-chip hardwired address and is not selectable by CA0,
CA1 and CA2.

The addresses corresponding to the states of CA0, CA1
and CA2 and the global address are shown in Table 1. The
maximum capacitive load allowed on the address pins
(CA0, CA1 and CA2) is 10pF, as these pins are driven
during address detection to determine if they are floating.

Write Word Protocol

The master initiates communication with the LTC2606/
LTC2616/LTC2626 with a START condition and a 7-bit slave
address followed by the Write bit (W) = 0. The LTC2606/
LTC2616/LTC2626 acknowledges by pulling the SDA pin
low at the 9th clock if the 7-bit slave address matches the
address of the parts (set by CA0, CA1 and CA2) or the global
address. The master then transmits three bytes of data. The
LTC2606/LTC2616/LTC2626 acknowledges each byte of
data by pulling the SDA line low at the 9th clock of each data
byte transmission. After receiving three complete bytes of
data, the LTC2606/LTC2616/LTC2626 executes the com-
mand specified in the 24-bit input word.

If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2606/LTC2616/LTC2626 do
not acknowledge the extra bytes of data (SDA is high
during the 9th clock).

The format of the three data bytes is shown in Figure 3. The
first byte of the input word consists of the 4-bit command
and four don't care bits. The next two bytes consist of the
16-bit data word. The 16-bit data word consists of the
16-, 14- or 12-bit input code, MSB to LSB, followed by 0,
2 or 4 don't care bits (LTC2606, LTC2616 and LTC2626
respectively). A typical LTC2606 write transaction is shown
in Figure 4.

The command assignments (C3-C0) are shown in Table 2.
The first four commands in the table consist of write and
update operations. A write operation loads a 16-bit data
word from the 32-bit shift register into the input register.
In an update operation, the data word is copied from the
input register to the DAC register and converted to an ana-
log voltage at the DAC output. The update operation also
powers up the DAC if it had been in power-down mode. The
data path and registers are shown in the Block Diagram.

Power-Down Mode

For power-constrained applications, power-down mode
can be used to reduce the supply current whenever the DAC
output is not needed. When in power-down, the buffer
amplifier, bias circuit and reference input is disabled and
draws essentially zero current. The DAC output is put into

LTC2606/LTC2616/LTC2626

26061626f

OPERATIO

1ST DATA BYTE

Input Word (LTC2606)

Write Word Protocol for LTC2606/LTC2616/LTC1626

D13

D14

D15

SLAVE ADDRESS

1ST DATA BYTE

D12 D11 D10 D9

D7 D6

D1 D0

2ND DATA BYTE

3RD DATA BYTE

2606 F03

2ND DATA BYTE

INPUT WORD

3RD DATA BYTE

1ST DATA BYTE

Input Word (LTC2616)

D11

D12

D13

D10 D9

D5 D4

2ND DATA BYTE

3RD DATA BYTE

1ST DATA BYTE

Input Word (LTC2626)

D10

D11

D3 D2

2ND DATA BYTE

3RD DATA BYTE

a high impedance state, and the output pin is passively
pulled to ground through 90k resistors. Input- and DAC-
register contents are not disturbed during power-down.

The DAC channel can be put into power-down mode by
using command 0100

. The 16-bit data word is ignored.

The supply and reference currents are reduced to almost
zero when the DAC is powered down; the effective
resistance at REF becomes a high impedance input
(typically > 1G).

Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 2
or performing an asychronous update (LDAC) as de-
scribed in the next section. The DAC is powered up as its
voltage output is updated. When the DAC in powered-
down state is powered up and updated, normal settling is
delayed. The main bias generation circuit block has been

Figure 3

automatically shut down in addition to the DAC amplifier
and reference input and so the power up delay time is

12µs (for V

= 5V) or 30µs (for V

= 3V)

Asynchronous DAC Update Using LDAC

In addition to the update commands shown in Table 2, the
LDAC pin asynchronously updates the DAC register with
the contents of the input register. Asynchronous update is
disabled when the input word is being clocked into the part.

If a complete input word has been written to the part, a low
on the LDAC pin causes the DAC register to be updated
with the contents of the input register.

If the input word is being written to the part, a low going
pulse on the LDAC pin before the completion of three bytes
of data powers up the DAC but does not cause the output
to be updated. If LDAC remains low after a complete input
word has been written to the part, then LDAC is recog-
nized, the command specified in the 24-bit word just
transferred is executed and the DAC output is updated.

The DAC is powered up when LDAC is taken low, indepen-
dent of any activity on the I

C bus.

If LDAC is low at the falling edge of the 9th clock of the 3rd
byte of data, it inhibits any software power-down com-
mand that was specified in the input word.

Table 2

COMMAND*

Write to Input Register

Update (Power Up) DAC Register

Write to and Update (Power Up)

Power Down

No Operation

*Command codes not shown are reserved and should not be used.

LTC2606/LTC2616/LTC2626

26061626f

OPERATIO

Voltage Output

The rail-to-rail amplifier has guaranteed load regulation
when sourcing or sinking up to 15mA at 5V (7.5mA at 3V).

Load regulation is a measure of the amplifier's ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is ex-
pressed in LSB/mA.

DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifiers' DC output
impedance is 0.050 when driving a load well away from
the rails.

When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by the
25 typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
25 · 1mA = 25mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteris-
tics section.

The amplifier is stable driving capacitive loads of up to
1000pF.

Board Layout

The excellent load regulation performance is achieved in
part by keeping "signal" and "power" grounds separated
internally and by reducing shared internal resistance.

The GND pin functions both as the node to which the
reference and output voltages are referred and as a return
path for power currents in the device. Because of this,
careful thought should be given to the grounding scheme
and board layout in order to ensure rated performance.

The PC board should have separate areas for the analog and
digital sections of the circuit. This keeps digital signals away

from sensitive analog signals and facilitates the use of
separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each other.

Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device's ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continu-
ous and uninterrupted plane, except for necessary lead
pads and vias, with signal traces on another layer.

The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star ground
should be as low as possible. Resistance here will add
directly to the effective DC output impedance of the device
(typically 0.050). Note that the LTC2606/LTC2616/
LTC2626 are no more susceptible to these effects than other
parts of their type; on the contrary, they allow layout-based
performance improvements to shine rather than limiting
attainable performance with excessive internal resistance.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is
limited to voltages within the supply range.

Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in
Figure 5b. Similarly, limiting can occur near full scale
when the REF pin is tied to V

. If V

REF

= V

and the DAC

full-scale error (FSE) is positive, the output for the highest
codes limits at V

as shown in Figure 5c. No full-scale

limiting can occur if V

REF

is less than V

FSE.

Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.

LTC2606/LTC2616/LTC2626

26061626f

PACKAGE DESCRIPTIO

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

3.00 ±0.10

(4 SIDES)

NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.38 ± 0.10

BOTTOM VIEW--EXPOSED PAD

1.65 ± 0.10

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

2.38 ±0.10

(2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 5)

0.200 REF

0.00 0.05

(DD10) DFN 0403

0.25 ± 0.05

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)

2.15 ±0.05

0.50
BSC

0.675 ±0.05

3.50 ±0.05

PACKAGE
OUTLINE

0.25 ± 0.05

0.50 BSC

LTC2606/LTC2616/LTC2626

26061626f

PART NUMBER

DESCRIPTION

COMMENTS

LTC1458/LTC1458L

Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality

LTC1458: V

= 4.5V to 5.5V, V

OUT

= 0V to 4.096V

LTC1458L: V

= 2.7V to 5.5V, V

OUT

= 0V to 2.5V

LTC1654

Dual 14-Bit Rail-to-Rail V

OUT

DAC

Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA

LTC1655/LTC1655L

Single 16-Bit V

OUT

DACs with Serial Interface in SO-8

= 5V(3V), Low Power, Deglitched

LTC1657/LTC1657L

Parallel 5V/3V 16-Bit V

OUT

DACs

Low Power, Deglitched, Rail-to-Rail V

OUT

LTC1660/LTC1665

Octal 10/8-Bit V

OUT

DACs in 16-Pin Narrow SSOP

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

LTC1821

Parallel 16-Bit Voltage Output DAC

Precision 16-Bit Settling in 2µs for 10V Step

LTC2600/LTC2610

Octal 16-/14-/12-Bit V

OUT

DACs in 16-Lead SSOP

250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

LTC2620

Output, SPI Serial Interface

LTC2601/LTC2611

Single 16-/14-/12-Bit V

OUT

DACs in 10-Lead DFN

250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

LTC2621

Output, SPI Serial Interface

LTC2602/LTC2612

Dual 16-/14-/12-Bit V

OUT

DACs in 8-Lead MSOP

300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

LTC2622

Output, SPI Serial Interface

LTC2604/LTC2614

Quad 16-/14-/12-Bit V

OUT

DACs in 16-Lead SSOP

250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail

LTC2624

Output, SPI Serial Interface

LT/TP 1204 1K · PRINTED IN THE USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear.com

RELATED PARTS

TYPICAL APPLICATIO

Demo Circuit Schematic. Onboard 20-Bit ADC Measures Key Performance Parameters

LDAC
CA0
SDA
SCL
CA1
CA2

SCK

SDO

9
8
7
10

4
2
3
5
1

2606 TA01

100

7.5k

0.1µF

OUT

CA0

CA1
CA2

C BUS

LTC2606

GND

REF

1V TO 5V

DAC

OUTPUT

REF

GND

LTC2421

SET

0.1µF

SPI BUS

100pF

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC2606CDD