LTC3707

3707f

High Efficiency, 2-Phase

Synchronous Step-Down Switching Regulator

Figure 1. High Efficiency Dual 5V/3.3V Step-Down Converter

180

Phased Dual Controllers Reduce Required

Input Capacitance and Power Supply Induced Noise

OPTI-LOOP

Compensation Minimizes C

OUT

1.5% Output Voltage Accuracy over Temperature

Dual N-Channel MOSFET Synchronous Drive

Power Good Output Voltage Monitor

DC Programmed Fixed Frequency 150kHz to 300kHz

Wide V

Range: 4.5V to 28V Operation

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Soft-Start Current Ramping

Foldback Output Current Limiting

Latched Short-Circuit Shutdown with Defeat Option

Output Overvoltage Protection

Remote Output Voltage Sense

Low Shutdown I

: 20

5V and 3.3V Standby Regulators

Small 28-Lead Narrow SSOP Package

Selectable Constant Frequency, Burst Mode

Operation or PWM Operation

The LTC

3707 is a high performance dual step-down

switching regulator controller that drives N-channel syn-
chronous power MOSFET stages. A constant frequency
current mode architecture allows adjustment of the fre-
quency up to 300kHz. Power loss and noise due to the ESR
of the input capacitors are minimized by operating the two
controller output stages out of phase.

OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance and
ESR values. The precision 0.8V reference and power good
output indicator are compatible with future microproces-
sor generations, and a wide 3.5V to 30V input supply range
encompasses all battery chemistries.

A RUN/SS pin for each controller provides both soft-start
and optional timed, short-circuit shutdown. Current
foldback limits MOSFET dissipation during short-circuit
conditions when overcurrent latchoff is disabled. Output
overvoltage protection circuitry latches on the bottom
MOSFET until V

OUT

returns to normal. The FCB mode pin

can select among Burst Mode operation, constant fre-
quency mode and continuous inductor current mode or
regulate a secondary winding.

Notebook and Palmtop Computers, PDAs

Battery Chargers

Portable Instruments

Battery-Operated Digital Devices

DC Power Distribution Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.

DESCRIPTIO

FEATURES

APPLICATIO S

TYPICAL APPLICATIO

4.7

, 0.1

105k

1000pF

6.3

220pF

CERAMIC

50V
CERAMIC

OUT1

6V
SP

SENSE1

0.01

R1
20k
1%

15k

OUT1

5V
5A

, 0.1

63.4k

6.3

220pF

1000pF

OUT

SENSE2

0.01

20k

15k

OUT2

3.3V
5A

TG1

TG2

BOOST1

BOOST2

SW1

SW2

BG1

BG2

SGND

PGND

SENSE1

SENSE2

SENSE1

SENSE2

OSENSE1

OSENSE2

TH1

TH2

INTV

RUN/SS1

RUN/SS2

5.2V TO 28V

M1, M2, M3, M4: FDS6680A

3707 F01

SS1

0.1

SS2

0.1

LTC3707

LTC3707

3707f

ORDER PART

NUMBER

LTC3707EGN

(Note 1)

Input Supply Voltage (V

).........................30V to 0.3V

Top Side Driver Voltages
(BOOST1, BOOST2) ...................................36V to 0.3V
Switch Voltage (SW1, SW2) .........................30V to 5V
INTV

CC,

EXTV

, RUN/SS1, RUN/SS2, (BOOST1-SW1),

(BOOST2-SW2), PGOOD .............................7V to 0.3V
SENSE1

, SENSE2

, SENSE1

SENSE2

Voltages ........................ (1.1)INTV

to 0.3V

FREQSET, STBYMD, FCB Voltage ........ INTV

to 0.3V

TH1,

TH2

, V

OSENSE1

, V

OSENSE2

Voltages ... 2.7V to 0.3V

Peak Output Current <10

s (TG1, TG2, BG1, BG2) ... 3A

INTV

Peak Output Current ................................ 40mA

Operating Temperature Range

LTC3707EG (Note 2) .......................... 40

C to 85

Junction Temperature (Note 3) ............................. 125

Storage Temperature Range ................. 65

C to 150

Lead Temperature (Soldering, 10 sec).................. 300

JMAX

= 125

= 95

C/W

The

denotes the specifications which apply over the full operating

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loops

OSENSE1, 2

Regulated Feedback Voltage

(Note 4); I

TH1, 2

Voltage = 1.2V

0.788

0.800

0.812

VOSENSE1, 2

Feedback Current

(Note 4)

REFLNREG

Reference Voltage Line Regulation

= 3.6V to 30V (Note 4)

0.002

0.02

%/V

LOADREG

Output Voltage Load Regulation

(Note 4)
Measured in Servo Loop;

Voltage = 1.2V to 0.7V

0.1

0.5

Measured in Servo Loop;

Voltage = 1.2V to 2.0V

0.1

0.5

m1, 2

Transconductance Amplifier g

TH1, 2

= 1.2V; Sink/Source 5uA; (Note 4)

1.3

mmho

mGBW1, 2

Transconductance Amplifier GBW

TH1, 2

= 1.2V; (Note 4)

MHz

Input DC Supply Current

(Note 5)

Normal Mode

EXTV

Tied to V

OUT1

; V

OUT1

= 5V

350

Standby

RUN/SS1, 2

= 0V, V

STBYMD

> 2V

125

Shutdown

RUN/SS1, 2

= 0V, V

STBYMD

= Open

FCB

Forced Continuous Threshold

0.76

0.800

0.84

FCB

Forced Continuous Pin Current

FCB

= 0.85V

0.30

0.18

0.1

BINHIBIT

Burst Inhibit (Constant Frequency)

Measured at FCB pin

4.3

4.8

Threshold

UVLO

Undervoltage Lockout

Ramping Down

3.5

OVL

Feedback Overvoltage Lockout

Measured at V

OSENSE1, 2

0.84

0.86

0.88

SENSE

Sense Pins Total Source Current

(Each Channel); V

SENSE1

, 2

= V

SENSE1

, 2

= 0V

STBYMD

Master Shutdown Threshold

STBYMD

Ramping Down

0.4

0.6

temperature range, otherwise specifications are at T

= 25

C. V

= 15V, V

RUN/SS1, 2

= 5V unless otherwise noted.

TOP VIEW

GN PACKAGE

28-LEAD PLASTIC SSOP

RUN/SS1

SENSE1

OSENSE1

FREQSET

STBYMD

FCB

TH1

SGND

3.3V

OUT

TH2

OSENSE2

SENSE2

PGOOD

TG1

SW1

BOOST1

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

ELECTRICAL CHARACTERISTICS

Consult LTC Marketing for parts specified with wider operating temperature ranges.

LTC3707

3707f

The

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 15V, V

RUN/SS1, 2

= 5V unless otherwise noted.

ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

STBYMD

Keep-Alive Power On-Threshold

STBYMD

Ramping Up, RUN

SS1, 2

= 0V

1.5

MAX

Maximum Duty Factor

In Dropout

99.4

RUN/SS1, 2

Soft-Start Charge Current

RUN/SS1, 2

= 1.9V

0.5

1.2

RUN/SS1, 2

ON RUN/SS Pin ON Threshold

RUN/SS1,

RUN/SS2

Rising

1.0

1.5

2.0

RUN/SS1, 2

LT RUN/SS Pin Latchoff Arming Threshold V

RUN/SS1,

RUN/SS2

Rising from 3V

4.1

4.75

SCL1, 2

RUN/SS Discharge Current

Soft Short Condition V

OSENSE1, 2

= 0.5V;

0.5

RUN/SS1, 2

= 4.5V

SDLHO

Shutdown Latch Disable Current

OSENSE1, 2

= 0.5V

1.6

SENSE(MAX)

Maximum Current Sense Threshold

OSENSE1, 2

= 0.7V,V

SENSE1, 2

= 5V

TG Transition Time:

(Note 6)

TG1, 2 t

Rise Time

LOAD

= 3300pF

110

TG1, 2 t

Fall Time

LOAD

= 3300pF

110

BG Transition Time:

(Note 6)

BG1, 2 t

Rise Time

LOAD

= 3300pF

110

BG1, 2 t

Fall Time

LOAD

= 3300pF

100

TG/BG t

Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time

LOAD

= 3300pF Each Driver

BG/TG t

Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time

LOAD

= 3300pF Each Driver

ON(MIN)

Minimum On-Time

Tested with a Square Wave (Note 7)

180

INTV

Linear Regulator

INTVCC

Internal V

Voltage

6V < V

< 30V, V

EXTVCC

= 4V

4.8

5.0

5.2

LDO

INT

INTV

Load Regulation

= 0 to 20mA, V

EXTVCC

= 4V

0.2

2.0

LDO

EXT

EXTV

Voltage Drop

= 20mA, V

EXTVCC

= 5V

100

200

EXTVCC

EXTV

Switchover Voltage

= 20mA, EXTV

Ramping Positive

4.5

4.7

LDOHYS

EXTV

Hysteresis

0.2

Oscillator

OSC

Oscillator frequency

FREQSET

= Open (Note 8)

190

220

250

kHz

LOW

Lowest Frequency

FREQSET

= 0V

120

140

160

kHz

HIGH

Highest Frequency

FREQSET

= 2.4V

280

310

360

kHz

FREQSET

Input Current

FREQSET

= 0V

3.3V Linear Regulator

3.3OUT

3.3V Regulator Output Voltage

No Load

3.20

3.35

3.45

3.3IL

3.3V Regulator Load Regulation

3.3

= 0 to 10mA

0.5

3.3VL

3.3V Regulator Line Regulation

6V < V

< 30V

0.05

0.2

PGOOD Output

PGL

PGOOD Voltage Low

PGOOD

= 2mA

0.1

0.3

PGOOD

PGOOD Leakage Current

PGOOD

= 5V

PGOOD Trip Level, Either Controller

OSENSE

Respect to Set Output Voltage

OSENSE

Ramping Negative

7.5

9.5

OSENSE

Ramping Positive

7.5

9.5

LTC3707

3707f

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: The LTC3707E is guaranteed to meet performance specifications
from 0

C to 70

C. Specifications over the 40

C to 85

C operating

temperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: T

is calculated from the ambient temperature T

and power

dissipation P

according to the following formula:

LTC3707EGN = T

= T

+ (P

· 85

C/W)

Note 4: The LTC3707 is tested in a feedback loop that servos V

ITH1, 2

to a

specified voltage and measures the resultant V

OSENSE1, 2.

Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.

Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current

40% of I

MAX

(see minimum on-time

considerations in the Applications Information section).

Note 8: V

FREQSET

pin internally tied to a 1.19V reference through a large

resistance.

Efficiency vs Output Current
and Mode (Figure 13)

OUTPUT CURRENT (A)

0.001

EFFICIENCY (%)

100

0.01

0.1

3707 G01

FORCED
CONTINUOUS
MODE (PWM)

CONSTANT
FREQUENCY
(BURST DISABLE)

Burst Mode

OPERATION

= 15V

OUT

= 5V

OUTPUT CURRENT (A)

0.001

EFFICIENCY (%)

3707 G02

0.01

0.1

100

= 10V

= 15V

= 7V

= 20V

= 15V

OUT

= 5V

INPUT VOLTAGE (V)

EFFICIENCY (%)

3707 G03

100

OUT

= 5V

OUT

= 3A

Efficiency vs Output Current
(Figure 13)

Efficiency vs Input Voltage
(Figure 13)

INTV

and EXTV

Switch

Voltage vs Temperature

Supply Current vs Input Voltage
and Mode (Figure 13)

INPUT VOLTAGE (V)

SUPPLY CURRENT (

400

1000

3707 G04

200

800

600

BOTH
CONTROLLERS ON

STANDBY

SHUTDOWN

EXTV

Voltage Drop

CURRENT (mA)

EXTV

VOLTAGE DROP (mV)

200

150

100

3707 G05

TEMPERATURE (

INTV

AND EXTV

SWITCH VOLTAGE (V)

4.95

5.00

5.05

3707 G06

4.90

4.85

100

125

4.80

4.70

4.75

INTV

VOLTAGE

EXTV

SWITCHOVER THRESHOLD

ELECTRICAL CHARACTERISTICS

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3707

3707f

Internal 5V LDO Line Reg

Maximum Current Sense Threshold
vs Duty Factor

Maximum Current Sense Threshold
vs Percent of Nominal Output
Voltage (Foldback)

INPUT VOLTAGE (V)

4.8

4.9

5.1

3707 G07

4.7

4.6

4.5

4.4

5.0

INTV

VOLTAGE (V)

LOAD

= 1mA

DUTY FACTOR (%)

SENSE

(mV)

3707 G08

100

PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

SENSE

(mV)

100

3707 G09

Maximum Current Sense Threshold
vs V

RUN/SS

(Soft-Start)

RUN/SS

(V)

SENSE

(mV)

3707 G10

SENSE(CM)

= 1.6V

Maximum Current Sense Threshold
vs Sense Common Mode Voltage

COMMON MODE VOLTAGE (V)

SENSE

(mV)

3707 G11

Current Sense Threshold
vs I

Voltage

ITH

(V)

SENSE

(mV)

3707 G12

0.5

1.5

2.5

Load Regulation

LOAD CURRENT (A)

NORMALIZED V

OUT

(%)

0.2

0.1

3707 G13

0.3

0.4

0.0

FCB = 0V
V

= 15V

FIGURE 1

ITH

vs V

RUN/SS

RUN/SS

(V)

ITH

(V)

0.5

1.0

1.5

2.0

2.5

3707 G14

OSENSE

= 0.7V

SENSE Pins Total Source Current

SENSE

COMMON MODE VOLTAGE (V)

SENSE

(

3707 G15

100

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3707

3707f

TEMPERATURE (

SENSE

(mV)

3707 G17

100

125

OUTPUT CURRENT (A)

DROPOUT VOLTAGE (V)

0.5

1.0

1.5

2.0

3707 G18

2.5

3.0

3.5

4.0

SENSE

= 0.015

SENSE

= 0.010

OUT

= 5V

Maximum Current Sense
Threshold vs Temperature

Dropout Voltage vs Output Current
(Figure 13)

Soft-Start Up (Figure 13)

OUT

5V/DIV

RUN/SS

5V/DIV

OUT

2A/DIV

= 15V

5ms/DIV

3707 G19

OUT

= 5V

Load Step (Figure 13)

OUT

200mV/DIV

OUT

2A/DIV

= 15V

s/DIV

3707 G20

OUT

= 5V

LOAD STEP = 0A TO 3A
Burst Mode OPERATION

Load Step (Figure 13)

OUT

200mV/DIV

OUT

2A/DIV

= 15V

s/DIV

3707 G21

OUT

= 5V

LOAD STEP = 0A TO 3A
CONTINUOUS MODE

Input Source/Capacitor
Instantaneous Current (Figure 13)

2A/DIV

200mV/DIV

SW1

10V/DIV

= 15V

s/DIV

3707 G22

OUT

= 5V

OUT5

= I

OUT3.3

= 2A

Burst Mode Operation (Figure 13)

OUT

20mV/DIV

OUT

0.5A/DIV

= 15V

s/DIV

3707 G23

OUT

= 5V

FCB

= OPEN

OUT

= 20mA

Constant Frequency (Burst Inhibit)
Operation (Figure 13)

OUT

20mV/DIV

OUT

0.5A/DIV

= 15V

s/DIV

3707 G24

OUT

= 5V

FCB

= 5V

OUT

= 20mA

SW2

10V/DIV

RUN/SS Current vs Temperature

TEMPERATURE (

RUN/SS CURRENT (

0.2

0.6

0.8

1.0

100

1.8

3707 G25

0.4

125

1.2

1.4

1.6

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3707

3707f

Current Sense Pin Input Current
vs Temperature

EXTV

Switch Resistance

vs Temperature

TEMPERATURE (

CURRENT SENSE INPUT CURRENT (

3707 G26

100

125

OUT

= 5V

TEMPERATURE (

EXTV

SWITCH RESISTANCE (

)

3707 G27

100

125

Oscillator Frequency
vs Temperature

TEMPERATURE (

200

250

350

3707 G28

150

100

125

300

FREQUENCY (kHz)

FREQSET

= 5V

FREQSET

= OPEN

FREQSET

= 0V

Undervoltage Lockout
vs Temperature

TEMPERATURE (

UNDERVOLTAGE LOCKOUT (V)

3.40

3.45

3.50

3707 G29

3.35

3.30

100

125

3.25

3.20

Shutdown Latch Thresholds
vs Temperature

TEMPERATURE (

SHUTDOWN LATCH THRESHOLDS (V) 0.5

1.5

2.0

2.5

100

4.5

3707 G30

1.0

125

3.0

3.5

4.0

LATCH ARMING

LATCHOFF

THRESHOLD

TYPICAL PERFOR A CE CHARACTERISTICS

LTC3707

3707f

RUN/SS1, RUN/SS2 (Pins 1, 15): Combination of soft-
start, run control inputs and short-circuit detection timers.
A capacitor to ground at each of these pins sets the ramp
time to full output current. Forcing either of these pins
back below 1.0V causes the IC to shut down the circuitry
required for that particular controller. Latchoff overcurrent
protection is also invoked via this pin as described in the
Applications Information section.

SENSE1

, SENSE2

(Pins 2, 14): The (+) Input to the

Differential Current Comparators. The I

pin voltage and

controlled offsets between the SENSE

and SENSE

pins

in conjunction with R

SENSE

set the current trip threshold.

SENSE1

, SENSE2

(Pins 3, 13): The () Input to the

Differential Current Comparators.

OSENSE1

, V

OSENSE2

(Pins 4, 12): Receives the remotely-

sensed feedback voltage for each controller from an
external resistive divider across the output.

FREQSET (Pin 5): Frequency Control Input to the Oscilla-
tor. This pin can be left open, tied to ground, tied to INTV

or driven by an external voltage source. This pin can also
be used with an external phase detector to build a true
phase-locked loop.

STBYMD (Pin 6): Control pin that determines which cir-
cuitry remains active when the controllers are shut down
and/or provides a common control point to shut down
both controllers. See the Operation section for details.

FCB (Pin 7): Forced Continuous Control Input. This input
acts on both controllers and is normally used to regulate
a secondary winding. Pulling this pin below 0.8V will
force continuous synchronous operation on both con-
trollers. Do not leave this pin floating.

TH1,

TH2

(Pins 8, 11): Error Amplifier Output and Switch-

ing Regulator Compensation Point. Each associated chan-
nels' current comparator trip point increases with this
control voltage.

SGND (Pin 9): Small Signal Ground common to both
controllers, must be routed separately from high current
grounds to the common () terminals of the C

OUT

capacitors.

3.3V

OUT

(Pin 10): Output of a linear regulator capable of

supplying 10mA DC with peak currents as high as 50mA.

PGND (Pin 20): Driver Power Ground. Connects to the
sources of bottom (synchronous) N-channel MOSFETs, an-
odes of the Schottky rectifiers and the () terminal(s) of C

INTV

(Pin 21): Output of the Internal 5V Linear Low

Dropout Regulator and the EXTV

Switch. The driver and

control circuits are powered from this voltage source. Must
be decoupled to power ground with a minimum of 4.7

tantalum or other low ESR capacitor. The INTV

regulator

standby function is determined by the STBYMD pin.

EXTV

(Pin 22): External Power Input to an Internal

Switch Connected to INTV

. This switch closes and

supplies V

power, bypassing the internal

low dropout

regulator, whenever EXTV

is higher than 4.7V. See

EXTV

connection in Applications section. Do not exceed

7V on this pin.

BG1, BG2 (Pins 23, 19): High Current Gate Drives for
Bottom (Synchronous) N-Channel MOSFETs. Voltage
swing at these pins is from ground to INTV

(Pin 24): Main Supply Pin. A bypass capacitor should

be tied between this pin and the signal ground pin.

BOOST1, BOOST2 (Pins 25, 18): Bootstrapped Supplies
to the Top Side Floating Drivers. Capacitors are connected
between the boost and switch pins and Schottky diodes
are tied between the boost and INTV

pins. Voltage swing

at the boost pins is from INTV

to (V

+ INTV

SW1, SW2 (Pins 26, 17): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to V

TG1, TG2 (Pins 27, 16): High Current Gate Drives for Top
N-Channel MOSFETs. These are the outputs of floating
drivers with a voltage swing equal to INTV

0.5V

superimposed on the switch node voltage SW.

PGOOD (Pin 28): Open-Drain Logic Output. PGOOD is
pulled to ground when the voltage on either V

OSENSE

pin is

not within

7.5% of its set point.

PI FU CTIO S

LTC3707

3707f

(Refer to Functional Diagram)

Main Control Loop

The LTC3707 uses a constant frequency, current mode
step-down architecture with the two controller channels
operating 180 degrees out of phase. During normal opera-
tion, each top MOSFET is turned on when the clock for that
channel sets the RS latch, and turned off when the main
current comparator, I

, resets the RS latch. The peak

inductor current at which I

resets the RS latch is con-

trolled by the voltage on the I

pin, which is the output of

each error amplifier EA. The V

OSENSE

pin receives the

voltage feedback signal, which is compared to the internal
reference voltage by the EA. When the load current in-
creases, it causes a slight decrease in V

OSENSE

relative to

the 0.8V reference, which in turn causes the I

voltage to

increase until the average inductor current matches the
new load current. After the top MOSFET has turned off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current compara-
tor I

, or the beginning of the next cycle.

The top MOSFET drivers are biased from floating boot-
strap capacitor C

, which normally is recharged during

each off cycle through an external diode when the top
MOSFET turns off. As V

decreases to a voltage close to

OUT

, the loop may enter dropout and attempt to turn on

the top MOSFET continuously. The dropout detector de-
tects this and forces the top MOSFET off for about 500ns
every tenth cycle to allow C

to recharge.

The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.2

current source to charge soft-start capacitor C

. When

reaches 1.5V, the main control loop is enabled with the

voltage clamped at approximately 30% of its maximum

value. As C

continues to charge, the I

pin voltage is

gradually released allowing normal, full-current opera-
tion. When both RUN/SS1 and RUN/SS2 are low, all
LTC3707 controller functions are shut down, and the
STBYMD pin determines if the standby 5V and 3.3V
regulators are kept alive.

Low Current Operation

The FCB pin is a multifunction pin providing two func-
tions: 1) an analog input to provide regulation for a
secondary winding by temporarily forcing continuous
PWM operation on both controllers and 2) a logic input
to select between

two modes of low current operation.

When the FCB pin voltage is below 0.800V, the controller
forces continuous PWM current mode operation. In this
mode, the top and bottom MOSFETs are alternately
turned on to maintain the output voltage independent of
direction of inductor current. When the FCB pin is below
V

INTVCC

2V but greater than 0.80V, the controller en-

ters Burst Mode operation. Burst Mode operation sets a
minimum output current level before inhibiting the top
switch and turns off the synchronous MOSFET(s) when
the inductor current goes negative. This combination of
requirements will, at low currents, force the I

pin below

a voltage threshold that will temporarily inhibit turn-on of
both output MOSFETs until the output voltage drops.
There is 60mV of hysteresis in the burst comparator B
tied to the I

pin. This hysteresis produces output

signals to the MOSFETs that turn them on for several
cycles, followed by a variable "sleep" interval depending
upon the load current. The resultant output voltage ripple
is held to a very small value by having the hysteretic
comparator after the error amplifier gain block.

Constant Frequency Operation

When the FCB pin is tied to INTV

, Burst Mode operation

is disabled and the forced minimum output current re-
quirement is removed. This provides constant frequency,
discontinuous (preventing reverse inductor current) cur-
rent operation over the widest possible output current
range. This constant frequency operation is not as efficient
as Burst Mode operation, but does provide a lower noise,
constant frequency operating mode down to approxi-
mately 1% of designed maximum output current. Voltage
should not be applied to the FCB pin prior to the application
of voltage to the V

pin.

OPERATIO

LTC3707

3707f

Continuous Current (PWM) Operation

Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, current will be
forced back into the main power supply potentially boost-
ing the input supply to dangerous voltage levels--
BEWARE!

Frequency Setting

The FREQSET pin provides frequency adjustment of the
internal oscillator from approximately 140kHz to 310kHz.
This input is nominally biased through an internal resistor
to the 1.19V reference, setting the oscillator frequency to
approximately 220kHz. This pin can be driven from an
external AC or DC signal source to control the instanta-
neous frequency of the oscillator. Voltage should not be
applied to the FREQSET pin prior to the application of
voltage to the V

pin.

INTV

/EXTV

Power

Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTV

pin.

When the EXTV

pin is left open, an internal 5V low

dropout linear regulator supplies INTV

power. If EXTV

is taken above 4.7V, the 5V regulator is turned off and an
internal switch is turned on connecting EXTV

to INTV

This allows the INTV

power to be derived from a high

efficiency external source such as the output of the regu-
lator itself or a secondary winding, as described in the
Applications Information.

Standby Mode Pin

The STBYMD pin is a three-state input that controls
common circuitry within the IC as follows: When the
STBYMD pin is held at ground, both controller RUN/SS
pins are pulled to ground providing a single control pin to
shut down both controllers. When the pin is left open, the
internal RUN/SS currents are enabled to charge the
RUN/SS capacitor(s), allowing the turn-on of either con-
troller and activating necessary common internal biasing.
When the STBYMD pin is taken above 2V, both internal

linear regulators are turned on independent of the state on
the RUN/SS pins of the two switching regulator control-
lers, providing an output power source for "wake-up"
circuitry. Decouple the pin with a small capacitor (0.01

to ground if the pin is not connected to a DC potential.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned on
until the overvoltage condition is cleared.

Power Good (PGOOD) Pin

The PGOOD pin is connected to an open drain of an internal
MOSFET. The MOSFET turns on and pulls the pin low when
both the outputs are not within

7.5% of their nominal

output levels as determined by their resistive feedback
dividers. When both outputs meet the

7.5% require-

ment, the MOSFET is turned off within 10

s and the pin is

allowed to be pulled up by an external resistor to a source
of up to 7V.

Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff

The RUN/SS capacitors are used initially to limit the inrush
current of each switching regulator. After the controller
has been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SS capacitor is used in a short-circuit time-out
circuit. If the output voltage falls to less than 70% of its
nominal output voltage, the RUN/SS capacitor begins
discharging on the assumption that the output is in an
overcurrent and/or short-circuit condition. If the condition
lasts for a long enough period as determined by the size of
the RUN/SS capacitor, the controllers will be shut down
until the RUN/SS pin(s) voltage(s) are recycled. This built-
in latchoff can be overridden by providing a >5

A pull-up

at a compliance of 4.2V to the RUN/SS pin(s). This current
shortens the soft start period but also prevents net dis-
charge of the RUN/SS capacitor(s) during an overcurrent
and/or short-circuit condition. Foldback current limiting is
also activated when the output voltage falls below 70% of
its nominal level whether or not the short-circuit latchoff

(Refer to Functional Diagram)

OPERATIO

LTC3707

3707f

circuit is enabled. Even if a short is present and the short-
circuit latchoff is not enabled, a safe, low output current is
provided due to internal current foldback and actual power
dissipated is low due to the efficient nature of the current
mode switching regulator.

THEORY AND BENEFITS OF 2-PHASE OPERATION

The LTC1628 and the LTC3707 are the first dual high
efficiency DC/DC controllers to bring the considerable
benefits of 2-phase operation to portable applications.
Notebook computers, PDAs, handheld terminals and au-
tomotive electronics will all benefit from the lower input
filtering requirement, reduced electromagnetic interfer-
ence (EMI) and increased efficiency associated with
2-phase operation.

Why the need for 2-phase operation? Up until the LTC1628
was introduced, constant-frequency dual switching regu-
lators operated both channels in phase (i.e., single-phase
operation). This means that both switches turned on at the
same time, causing current pulses of up to twice the
amplitude of those for one regulator to be drawn from the
input capacitor and battery. These large amplitude current
pulses increased the total RMS current flowing from the
input capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.

With 2-phase operation, the two channels of the dual-
switching regulator are operated 180 degrees out of
phase. This effectively interleaves the current pulses drawn
by the switches, greatly reducing the overlap time where
they add together.

The result is a significant reduction in

total RMS input current, which in turn allows less expen-
sive input capacitors to be used, reduces shielding re-
quirements for EMI and improves real world operating
efficiency.

Figure 3 compares the input waveforms for a representa-
tive single-phase dual switching regulator to the LTC3707
2-phase dual switching regulator. An actual measurement
of the RMS input current under these conditions shows
that 2-phase operation dropped the input current from
2.53A

RMS

to 1.55A

RMS

. While this is an impressive reduc-

tion in itself, remember that the power losses are propor-
tional to I

RMS

, meaning that the actual power wasted is

reduced by a factor of 2.66. The reduced input ripple
voltage also means less power is lost in the input power
path, which could include batteries, switches, trace/con-
nector resistances and protection circuitry. Improvements
in both conducted and radiated EMI also directly accrue as
a result of the reduced RMS input current and voltage.

Of course, the improvement afforded by 2-phase opera-
tion is a function of the dual switching regulator's relative
duty cycles which, in turn, are dependent upon the input
voltage V

(Duty Cycle = V

OUT

). Figure 4 shows how

(b)

(a)

5V SWITCH

20V/DIV

3.3V SWITCH

20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

500mV/DIV

IN(MEAS)

= 1.55A

RMS

3707 F03b/TIFF

IN(MEAS)

= 2.53A

RMS

3707 F03a/TIFF

Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation
for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The
Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows Less Expensive
Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency

(Refer to Functional Diagram)

OPERATIO

LTC3707

3707f

Figure 4. RMS Input Current Comparison

Figure 1 on the first page is a basic LTC3707 application
circuit. External component selection is driven by the
load requirement, and begins with the selection of R

SENSE

and the inductor value. Next, the power MOSFETs and D1
are selected. Finally, C

and C

OUT

are selected. The

circuit shown in Figure 1 can be configured for operation
up to an input voltage of 28V (limited by the external
MOSFETs).

SENSE

Selection For Output Current

SENSE

is chosen based on the required output current.

The LTC3707 current comparator has a maximum thresh-
old of 75mV/R

SENSE

and an input common mode range of

SGND to 1.1(INTV

). The current comparator threshold

sets the peak of the inductor current, yielding a maximum
average output current I

MAX

equal to the peak value less

half the peak-to-peak ripple current,

Allowing a margin for variations in the LTC3707 and
external component values yields:

SENSE

MAX

When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to
the internal compensation required to meet stability crite-
rion for buck regulators operating at greater than 50%
duty factor. A curve is provided to estimate this reducton
in peak output current level depending upon the operating
duty factor.

Selection of Operating Frequency

The LTC3707 uses a constant frequency architecture with
the frequency determined by an internal oscillator capaci-
tor. This internal capacitor is charged by a fixed current
plus an additional current that is proportional to the
voltage applied to the FREQSET pin.

A graph for the voltage applied to the FREQSET pin vs
frequency is given in Figure 5. As the operating frequency

INPUT VOLTAGE (V)

INPUT RMS CURRENT (A)

3.0

2.5

2.0

1.5

1.0

0.5

3707 F04

SINGLE PHASE
DUAL CONTROLLER

2-PHASE

DUAL CONTROLLER

= 5V/3A

= 3.3V/3A

the RMS input current varies for single-phase and 2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.

It can readily be seen that the advantages of 2-phase
operation are not just limited to a narrow operating range,
but in fact extend over a wide region. A good rule of thumb
for most applications is that 2-phase operation will reduce
the input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.

A final question: If 2-phase operation offers such an
advantage over single-phase operation for dual switching
regulators, why hasn't it been done before? The answer is
that, while simple in concept, it is hard to implement.
Constant-frequency current mode switching regulators
require an oscillator derived "slope compensation" signal
to allow stable operation of each regulator at over 50%
duty cycle. This signal is relatively easy to derive in single-
phase dual switching regulators, but required the develop-
ment of a new and proprietary technique to allow 2-phase
operation. In addition, isolation between the two channels

(Refer to Functional Diagram)

OPERATIO

APPLICATIO S I FOR ATIO

becomes more critical with 2-phase operation because
switch transitions in one channel could potentially disrupt
the operation of the other channel.

The LTC1628 and the LTC3707 are proof that these
hurdles have been surmounted. The new device offers
unique advantages for the ever-expanding number of high
efficiency power supplies required in portable electronics.

LTC3707

3707f

is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 310kHz.

Inductor Value Calculation

The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.

The inductor value has a direct effect on ripple current. The
inductor ripple current

decreases with higher induc-

tance or frequency and increases with higher V

f L

OUT

( )( )

Accepting larger values of

allows the use of low

inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is

=0.3(I

MAX

). Remember, the

maximum

occurs at the maximum input voltage.

The inductor value also has secondary effects. The transi-
tion to Burst Mode operation begins when the average
inductor current required results in a peak current below

25% of the current limit determined by R

SENSE

. Lower

inductor values (higher

) will cause this to occur at

lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.

Inductor Core Selection

Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron
cores, forcing the use of more expensive ferrite,
molypermalloy, or Kool M

cores. Actual core loss is

independent of core size for a fixed inductor value, but it
is very dependent on inductance selected. As inductance
increases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.

Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates "hard," which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool M

. Toroids are very space efficient,

especially when you can use several layers of wire. Be-
cause they generally lack a bobbin, mounting is more
difficult. However, designs for surface mount are available
that do not increase the height significantly.

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for each
controller with the LTC3707: One N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTV

voltage. This voltage is typically 5V during start-up (see

Kool M

is a registered trademark of Magnetics, Inc.

Figure 5. FREQSET Pin Voltage vs Frequency

OPERATING FREQUENCY (kHz)

120

170

220

270

320

FREQSET PIN VOLTAGE (V)

3707 F05

2.5

2.0

1.5

1.0

0.5

APPLICATIO S I FOR ATIO

LTC3707

3707f

EXTV

Pin Connection). Consequently, logic-level

threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(V

< 5V); then, sub-logic level threshold MOSFETs

GS(TH)

< 3V) should be used. Pay close attention to the

DSS

specification for the MOSFETs as well; most of the

logic level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the "ON"
resistance R

DS(ON)

, reverse transfer capacitance C

RSS

input voltage and maximum output current. When the
LTC3707 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:

Main Switch Duty Cycle

OUT

Synchronous Switch Duty Cycle

OUT

The MOSFET power dissipations at maximum output
current are given by:

k V

MAIN

OUT

MAX

DS ON

MAX

RSS

( )

( ) ( )( )( )

(

)

SYNC

OUT

MAX

DS ON

( )

(

)

where

is the temperature dependency of R

DS(ON)

and k

is a constant inversely related to the gate drive current.

Both MOSFETs have I

R losses while the topside N-channel

equation includes an additional term for transition losses,
which are highest at high input voltages. For V

< 20V the

high current efficiency generally improves with larger
MOSFETs, while for V

> 20V the transition losses rapidly

increase to the point that the use of a higher R

DS(ON)

device

with lower C

RSS

actually provides higher efficiency. The

synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.

The term (1+

) is generally given for a MOSFET in the form

of a normalized R

DS(ON)

vs Temperature curve, but

= 0.005/

C can be used as an approximation for low

voltage MOSFETs. C

RSS

is usually specified in the MOS-

FET characteristics. The constant k = 1.7 can be used to
estimate the contributions of the two terms in the main
switch dissipation equation.

The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the dead-
time and requiring a reverse recovery period that could
cost as much as 3% in efficiency at high V

. A 1A to 3A

Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance.

and C

OUT

Selection

The selection of C

is simplified by the multiphase archi-

tecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
when only one controller is operating. The controller with
the highest (V

OUT

)(I

OUT

) product needs to be used in the

formula below to determine the maximum RMS current
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease
the input RMS ripple current from this maximum value
(see Figure 4). The out-of-phase technique typically re-
duces the input capacitor's RMS ripple current by a factor
of 30% to 70% when compared to a single phase power
supply solution.

The type of input capacitor, value and ESR rating have
efficiency effects that need to be considered in the selec-
tion process. The capacitance value chosen should be
sufficient to store adequate charge to keep high peak
battery currents down. 20

F to 40

F is usually sufficient

for a 25W output supply operating at 200kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery efficiency. All of the power (RMS
ripple current · ESR) not only heats up the capacitor but
wastes power from the battery.

APPLICATIO S I FOR ATIO

LTC3707

3707f

Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used as
input capacitors, but each has drawbacks: ceramic voltage
coefficients are very high and may have audible piezoelec-
tric effects; tantalums need to be surge-rated; OS-CONs
suffer from higher inductance, larger case size and limited
surface-mount applicability; electrolytics' higher ESR and
dryout possibility require several to be used. Multiphase
systems allow the lowest amount of capacitance overall.
As little as one 22

F or two to three 10

F ceramic capaci-

tors are an ideal choice in a 20W to 50W power supply due
to their extremely low ESR. Even though the capacitance
at 20V is substantially below their rating at zero-bias, very
low ESR loss makes ceramics an ideal candidate for
highest efficiency battery operated systems. Also con-
sider parallel ceramic and high quality electrolytic capaci-
tors as an effective means of achieving ESR and bulk
capacitance goals.

In continuous mode, the source current of the top N-chan-
nel MOSFET is a square wave of duty cycle V

OUT

. To

prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current of one channel must
be used. The maximum RMS capacitor current is given by:

quiredI

RMS

MAX

OUT

(

)

[

]

1 2

This formula has a maximum at V

= 2V

OUT

, where

RMS

= I

OUT

/2. This simple worst case condition is com-

monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer's
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.

The benefit of the LTC3707 multiphase can be calculated
by using the equation above for the higher power control-
ler and then calculating the loss that would have resulted
if both controller channels switch on at the same time. The
total RMS power lost is lower when both controllers are

operating due to the interleaving of current pulses through
the input capacitor's ESR. This is why the input capacitor's
requirement calculated above for the worst-case control-
ler is adequate for the dual controller design. Remember
that input protection fuse resistance, battery resistance
and PC board trace resistance losses are also reduced due
to the reduced peak currents in a multiphase system.

The

overall benefit of a multiphase design will only be fully
realized when the source impedance of the power supply/
battery is included in the efficiency testing. The drains of
the two top MOSFETS should be placed within 1cm of each
other and share a common C

(s). Separating the drains

and C

may produce undesirable voltage and current

resonances at V

The selection of C

OUT

is driven by the required effective

series resistance (ESR). Typically once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The output ripple (

OUT

) is determined by:

I ESR

OUT

Where f = operating frequency, C

OUT

= output capacitance,

and

= ripple current in the inductor. The output ripple

is highest at maximum input voltage since

increases

with input voltage. With

= 0.3I

OUT(MAX)

the output

ripple will typically be less than 50mV at max V

assum-

ing:

OUT

Recommended ESR < 2 R

SENSE

and C

OUT

> 1/(8fR

SENSE

)

The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran-
tees that the output capacitance does not significantly
discharge during the operating frequency period due to
ripple current. The choice of using smaller output capaci-
tance increases the ripple voltage due to the discharging
term but can be compensated for by using capacitors of
very low ESR to maintain the ripple voltage at or below
50mV. The I

pin OPTI-LOOP compensation compo-

nents can be optimized to provide stable, high perfor-
mance transient response regardless of the output capaci-
tors selected.

APPLICATIO S I FOR ATIO

LTC3707

3707f

Manufacturers such as Nichicon, United Chemicon and
Sanyo can be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.

In surface mount applications multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitors are available in surface mount packages. Spe-
cial polymer surface mount capacitors offer very low ESR
but have lower storage capacity per unit volume than other
capacitor types. These capacitors offer a very cost-effec-
tive output capacitor solution and are an ideal choice when
combined with a controller having high loop bandwidth.
Tantalum capacitors offer the highest capacitance density
and are often used as output capacitors for switching
regulators having controlled soft-start. Several excellent
surge-tested choices are the AVX TPS, AVX TPSV or the
KEMET T510 series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. Aluminum
electrolytic capacitors can be used in cost-driven applica-
tions providing that consideration is given to ripple current
ratings, temperature and long term reliability. A typical
application will require several to many aluminum electro-
lytic capacitors in parallel. A combination of the above
mentioned capacitors will often result in maximizing per-
formance and minimizing overall cost. Other capacitor
types include Nichicon PL series, NEC Neocap, Pansonic
SP and Sprague 595D series. Consult manufacturers for
other specific recommendations.

INTV

Regulator

An internal P-channel low dropout regulator produces 5V
at the INTV

pin from the V

supply pin. INTV

powers

the drivers and internal circuitry within the LTC3707. The
INTV

pin regulator can supply a peak current of 40mA

and must be bypassed to ground with a minimum of
4.7

F tantalum, 10

F special polymer, or low ESR type

electrolytic capacitor. A 1

F ceramic capacitor placed

directly adjacent to the INTV

and PGND IC pins is highly

recommended. Good bypassing is necessary to supply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between channels.

Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3707 to be
exceeded. The system supply current is normally domi-
nated by the gate charge current. Additional external
loading of the INTV

and 3.3V linear regulators also

needs to be taken into account for the power dissipation
calculations. The total INTV

current can be supplied by

either the 5V internal linear regulator or by the EXTV

input pin. When the voltage applied to the EXTV

pin is

less than 4.7V, all of the INTV

current is supplied by the

internal 5V linear regulator. Power dissipation for the IC in
this case is highest: (V

)(I

INTVCC

), and overall efficiency

is lowered. The gate charge current is dependent on
operating frequency as discussed in the Efficiency Consid-
erations section. The junction temperature can be esti-
mated by using the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC3707 V

current is limited to less than 24mA from a 24V supply
when not using the EXTV

pin as follows:

= 70

C + (24mA)(24V)(95

C/W) = 125

Use of the EXTV

input pin reduces the junction tempera-

ture to:

= 70

C + (24mA)(5V)(95

C/W) = 81

Dissipation should be calculated to also include any added
current drawn from the internal 3.3V linear regulator. To
prevent maximum junction temperature from being ex-
ceeded, the input supply current must be checked operat-
ing in continuous mode at maximum V

EXTV

Connection

The LTC3707 contains an internal P-channel MOSFET
switch connected between the EXTV

and INTV

pins.

When the voltage applied to EXTV

rises above

4.7V, the

internal regulator is turned off and the switch closes,
connecting the EXTV

pin to the INTV

pin thereby

supplying internal power. The switch remains closed as
long as the voltage applied to EXTV

remains above 4.5V.

This allows the MOSFET driver and control power to be

APPLICATIO S I FOR ATIO

LTC3707

3707f

derived from the output during normal operation (4.7V <
V

OUT

< 7V) and from the internal regulator when the output

is out of regulation (start-up, short-circuit). If more cur-
rent is required through the EXTV

switch than is speci-

fied, an external Schottky diode can be added between the
EXTV

and INTV

pins. Do not apply greater than 7V to

the EXTV

pin and ensure that EXTV

< V

Significant efficiency gains can be realized by powering
INTV

from the output, since the V

current resulting

from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 5V regulators this
supply means connecting the EXTV

pin directly to V

OUT

However, for 3.3V and other lower voltage regulators,
additional circuitry is required to derive INTV

power

from the output.

The following list summarizes the four possible connec-
tions for EXTV

CC:

1. EXTV

Left Open (or Grounded). This will cause INTV

to be powered from the internal 5V regulator resulting in
an efficiency penalty of up to 10% at high input voltages.

2. EXTV

Connected directly to V

OUT

. This is the normal

connection for a 5V regulator and provides the highest
efficiency.

3. EXTV

Connected to an External supply. If an external

supply is available in the 5V to 7V range, it may be used to
power EXTV

providing it is compatible with the MOSFET

gate drive requirements.

Figure 6a. Secondary Output Loop & EXTV

Connection

Figure 6b. Capacitive Charge Pump for EXTV

4. EXTV

Connected to an Output-Derived Boost Net-

work. For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTV

to an

output-derived voltage that has been boosted to greater
than 4.7V. This can be done with either the inductive boost
winding as shown in Figure 6a or the capacitive charge
pump shown in Figure 6b. The charge pump has the
advantage of simple magnetics.

Topside MOSFET Driver Supply (C

, D

)

External bootstrap capacitors C

connected to the BOOST

pins supply the gate drive voltages for the topside MOSFETs.
Capacitor C

in the functional diagram is charged though

external diode D

from INTV

when the SW pin is low.

When one of the topside MOSFETs is to be turned on, the
driver places the C

voltage across the gate-source of the

desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
V

and the BOOST pin follows. With the topside MOSFET

on, the boost voltage is above the input supply: V

BOOST

+ V

INTVCC

. The value of the boost capacitor C

needs

to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the exter-
nal Schottky diode must be greater than V

IN(MAX)

. When

adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and the
input current decreases, then the efficiency has improved.
If there is no change in input current, then there is no
change in efficiency.

EXTV

FCB

SGND

TG1

BG1

PGND

LTC3707

SENSE

OUT

SEC

OUT

3707 F06a

N-CH

1:N

OPTIONAL EXTV

CONNECTION
5V < V

SEC

< 7V

EXTV

TG1

BG1

PGND

LTC3707

OUT

VN2222LL

OUT

3707 F06b

N-CH

BAT85

0.22

SENSE

APPLICATIO S I FOR ATIO

LTC3707

3707f

Output Voltage

The LTC3707 output voltages are each set by an external
feedback resistive divider carefully placed across the
output capacitor. The resultant feedback signal is com-
pared with the internal precision 0.800V voltage reference
by the error amplifier. The output voltage is given by the
equation:

OUT

0 8

SENSE

/SENSE

Pins

The common mode input range of the current comparator
sense pins is from 0V to (1.1)INTV

. Continuous linear

operation is guaranteed throughout this range allowing
output voltage setting from 0.8V to 7.7V, depending upon
the voltage applied to EXTV

. A differential NPN input

stage is biased with internal resistors from an internal
2.4V source as shown in the Functional Diagram. This
requires that current either be sourced or sunk from the
SENSE pins depending on the output voltage. If the output
voltage is below 2.4V current will flow out of both SENSE
pins to the main output. The output can be easily preloaded
by the V

OUT

resistive divider to compensate for the current

comparator's negative input bias current. The maximum
current flowing out of each pair of SENSE pins is:

SENSE

+ I

SENSE

= (2.4V V

OUT

)/24k

Since V

OSENSE

is servoed to the 0.8V reference voltage, we

can choose R1 in Figure 2 to have a maximum value to
absorb this current.

MAX

OUT

0 8

2 4

(

)

for V

OUT

< 2.4V

Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32K. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb the
sense currents; however, R1 is still bounded by the
V

OSENSE

feedback current.

Soft-Start/Run Function

The RUN/SS1 and RUN/SS2 pins are multipurpose pins
that provide a soft-start function and a means to shut
down the LTC3707. Soft-start reduces the input power
source's surge currents by gradually increasing the
controller's current limit (proportional to V

ITH

). This pin

can also be used for power supply sequencing.

An internal 1.2

A current source charges up the C

capacitor

When the voltage on RUN/SS1 (RUN/SS2)

reaches 1.5V, the particular controller is permitted to start
operating. As the voltage on RUN/SS increases from 1.5V
to 3.0V, the internal current limit is increased from 25mV/
R

SENSE

to 75mV/R

SENSE

. The output current limit ramps

up slowly, taking an additional 1.25s/

F to reach full

current. The output current thus ramps up slowly, reduc-
ing the starting surge current required from the input
power supply. If RUN/SS has been pulled all the way to
ground there is a delay before starting of approximately:

F C

DELAY

(

)

1 5

1 2

1 25

F C

IRAMP

(

)

1 5

1 2

1 25

By pulling both RUN/SS pins below 1V and/or pulling the
STBYMD pin below 0.2V, the LTC3707 is put into low
current shutdown (I

= 20

A). The RUN/SS pins can be

driven directly from logic as shown in Figure 7. Diode D1
in Figure 7 reduces the start delay but allows C

to ramp

up slowly providing the soft-start function. Each RUN/SS
pin has an internal 6V zener clamp (See Functional
Diagram).

Figure 7. RUN/SS Pin Interfacing

APPLICATIO S I FOR ATIO

3.3V OR 5V

RUN/SS

INTV

RUN/SS

3707 F07

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

(a)

(b)

LTC3707

3707f

Fault Conditions: Overcurrent Latchoff

The RUN/SS pins also provide the ability to latch off the
controller(s) when an overcurrent condition is detected.
The RUN/SS capacitor, C

, is used initially to turn on and

limit the inrush current. After the controller has been
started and been given adequate time to charge up the
output capacitor and provide full load current, the RUN/SS
capacitor is used for a short-circuit timer. If the regulator's
output voltage falls to less than 70% of its nominal value
after C

reaches 4.2V, C

begins discharging on the

assumption that the output is in an overcurrent condition.
If the condition lasts for a long enough period as deter-
mined by the size of the C

and the specified discharge

current, the controller will be shut down until the RUN/SS
pin voltage is recycled. If the overload occurs during start-
up, the time can be approximated by:

LO1

(4.1 1.5 + 4.1 3.5)]/(1.2

= 2.7 · 10

)

If the overload occurs after start-up the voltage on C

will

begin discharging from the zener clamp voltage:

LO2

(6 3.5)]/(1.2

A) = 2.1 · 10

)

This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin as shown
in Figure 7. This resistance shortens the soft-start period
and prevents the discharge of the RUN/SS capacitor
during an over current condition. Tying this pull-up resis-
tor to V

as in Figure 7a, defeats overcurrent latchoff.

Diode-connecting this pull-up resistor to INTV

, as in

Figure 7b, eliminates any extra supply current during
controller shutdown while eliminating the INTV

from preventing controller start-up.

Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem
with noise pickup or poor layout causing the protection
circuit to latch off. Defeating this feature will easily allow
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. After the design is complete, a decision can be
made whether to enable the latchoff feature.

The value of the soft-start capacitor C

may need to be

scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:

> (C

OUT

)(V

OUT

) (10

) (R

SENSE

)

The minimum recommended soft-start capacitor of
C

= 0.1

F will be sufficient for most applications.

Fault Conditions: Current Limit and Current Foldback

The LTC3707 current comparator has a maximum sense
voltage of 75mV resulting in a maximum MOSFET current
of 75mV/R

SENSE

. The maximum value of current limit

generally occurs with the largest V

at the highest ambi-

ent temperature, conditions that cause the highest power
dissipation in the top MOSFET.

The LTC3707 includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch described above is overridden. If the
output falls below 70% of its nominal output level, then the
maximum sense voltage is progressively lowered from
75mV to 25mV. Under short-circuit conditions with very
low duty cycles, the LTC3707 will begin cycle skipping in
order to limit the short-circuit current. In this situation the
bottom MOSFET will be dissipating most of the power but
less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time t

ON(MIN)

the LTC3707 (less than 200ns), the input voltage and
inductor value:

L(SC)

= t

ON(MIN)

/L)

The resulting short-circuit current is:

SENSE

L SC

(

)

APPLICATIO S I FOR ATIO

LTC3707

3707f

Fault Conditions: Overvoltage Protection (Crowbar)

The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow, that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the
controller is operating.

A comparator monitors the output for overvoltage condi-
tions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage.
When this condition is sensed, the top MOSFET is turned
off and the bottom MOSFET is turned on until the overvolt-
age condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
therefore allow a switching regulator system having a poor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
as the OV condition persists; if V

OUT

returns to a safe level,

normal operation automatically resumes. A shorted top
MOSFET will result in a high current condition which will
open the system fuse. The switching regulator will regu-
late properly with a leaky top MOSFET by altering the duty
cycle to accommodate the leakage.

The Standby Mode (STBYMD) Pin Function

The Standby Mode (STBYMD) pin provides several choices
for start-up and standby operational modes. If the pin is
pulled to ground, the RUN/SS pins for both controllers are
internally pulled to ground, preventing start-up and thereby
providing a single control pin for turning off both control-
lers at once. If the pin is left open or decoupled with a
capacitor to ground, the RUN/SS pins are each internally
provided with a starting current enabling external control
for turning on each controller independently. If the pin is
provided with a current of >3

A at a voltage greater than

2V, both internal linear regulators (INTV

and 3.3V) will

be on even when both controllers are shut down. In this
mode, the onboard 3.3V and 5V linear regulators can

provide power to keep-alive functions such as a keyboard
controller. This pin can also be used as a latching "on" and/
or latching "off" power switch if so designed.

Frequency of Operation

The LTC3707 has an internal voltage controlled oscillator.
The frequency of this oscillator can be varied over a 2 to 1
range. The pin is internally self-biased at 1.19V, resulting
in a free-running frequency of approximately 220kHz. The
FREQSET pin can be grounded to lower this frequency to
approximately 140kHz or tied to the INTV

pin to yield

approximately 310kHz. The FREQSET pin may be driven
with a voltage from 0 to INTV

to fix or modulate the

oscillator frequency as shown in Figure 5.

Minimum On-Time Considerations

Minimum on-time t

ON(MIN)

is the smallest time duration

that the LTC3707 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that

ON MIN

OUT

(

)

( )

If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3707 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.

The minimum on-time for the LTC3707 is generally less
than 200ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
300ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.

APPLICATIO S I FOR ATIO

LTC3707

3707f

FCB Pin Operation

The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced
when the FCB pin drops below 0.8V. During continuous
mode, current flows continuously in the transformer pri-
mary. The secondary winding(s) draw current only when
the bottom, synchronous switch is on. When primary load
currents are low and/or the V

OUT

ratio is low, the

synchronous switch may not be on for a sufficient amount
of time to transfer power from the output capacitor to the
secondary load. Forced continuous operation will support
secondary windings providing there is sufficient synchro-
nous switch duty factor. Thus, the FCB input pin removes
the requirement that power must be drawn from the
inductor primary in order to extract power from the
auxiliary windings. With the loop in continuous mode, the
auxiliary outputs may nominally be loaded without regard
to the primary output load.

The secondary output voltage V

SEC

is normally set as

shown in Figure 6a by the turns ratio N of the transformer:

SEC

(N + 1) V

OUT

However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then V

SEC

will droop. An external resistive divider from

SEC

to the FCB pin sets a minimum voltage V

SEC(MIN)

SEC MIN

(

)

0 8

If V

SEC

drops below this level, the FCB voltage forces

temporary continuous switching operation until V

SEC

again above its minimum.

In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.18

internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.

The following table summarizes the possible states avail-
able on the FCB pin:

Table 1

FCB Pin

Condition

0V to 0.75V

Forced Continuous (Current Reversal
Allowed--Burst Inhibited)

0.85V < V

FCB

< V

INTVCC

Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed

Feedback Resistors

Regulating a Secondary Winding

= V

INTVCC

Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current

Voltage Positioning

Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifications. Voltage positioning can easily be added to
the LTC3707 by loading the I

pin with a resistive divider

having a Thevenin equivalent voltage source equal to the
midpoint operating voltage of the error amplifier, or 1.2V
(see Figure 8).

The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
maximum output voltage deviation can theoretically be
reduced to half or alternatively the amount of output
capacitance can be reduced for a particular application. A
complete explanation is included in Design Solutions 10.
(See www.linear-tech.com)

INTV

3707 F08

LTC3707

Figure 8. Active Voltage Positioning Applied to the LTC3707

APPLICATIO S I FOR ATIO

LTC3707

3707f

3. I

R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R

SENSE

but is "chopped" between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same R

DS(ON)

, then the resistance of one

MOSFET can simply be summed with the resistances of L,
R

SENSE

and ESR to obtain I

R losses. For example, if each

DS(ON)

= 30m

, R

= 50m

, R

SENSE

= 10m

and R

ESR

= 40m

(sum of both input and output capacitance

losses), then the total resistance is 130m

. This results in

losses ranging from 3% to 13% as the output current
increases from 1A to 5A for a 5V output, or a 4% to 20%
loss for a 3.3V output. Efficiency varies as the inverse
square of V

OUT

for the same external components and

output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!

4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:

Transition Loss = (1.7) V

O(MAX)

RSS

Other "hidden" losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these "system" level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that C

has

adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a
minimum of 20

F to 40

F of capacitance having a maxi-

mum of 20m

to 50m

of ESR. The LTC3707 2-phase

architecture typically halves this input capacitance re-
quirement over competing solutions. Other losses includ-
ing Schottky conduction losses during dead-time and
inductor core losses generally account for less than 2%
total additional loss.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage
of input power.

Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3707 circuits: 1) LTC3707 V

current (in-

cluding loading on the 3.3V internal regulator), 2) INTV

regulator current, 3) I

R losses, 4) Topside MOSFET

transition losses.

1. The V

current has two components: the first is the DC

supply current given in the Electrical Characteristics table,
which excludes MOSFET driver and control currents; the
second is the current drawn from the 3.3V linear regulator
output. V

current typically results in a small (<0.1%) loss.

2. INTV

current is the sum of the MOSFET driver and

control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTV

ground. The resulting dQ/dt is a current out of INTV

that

is typically much larger than the control circuit current. In
continuous mode, I

GATECHG

=f(Q

), where Q

and Q

are the gate charges of the topside and bottom side
MOSFETs.

Supplying INTV

power through the EXTV

switch input

from an output-derived source will scale the V

current

required for the driver and control circuits by a factor of
(Duty Cycle)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTV

current results in approxi-

mately 2.5mA of V

current. This reduces the mid-current

loss from 10% or more (if the driver was powered directly
from V

) to only a few percent.

APPLICATIO S I FOR ATIO

LTC3707

3707f

Checking Transient Response

The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V

OUT

shifts by an

amount equal to

LOAD

(ESR), where ESR is the effective

series resistance of C

OUT

LOAD

also begins to charge or

discharge C

OUT

generating the feedback error signal that

forces the regulator to adapt to the current change and
return V

OUT

to its steady-state value. During this recovery

time V

OUT

can be monitored for excessive overshoot or

ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values.

The availability of the I

pin not only allows

optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response. Assuming a pre-
dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I

external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.

The I

series R

-C

filter sets the dominant pole-zero

loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80% of

full-load current having a rise time of 1

s to 10

s will

produce output voltage and I

pin waveforms that will

give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This is
why it is better to look at the I

pin signal which is in the

feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing R

and the bandwidth of the loop will be

increased by decreasing C

. If R

is increased by the same

factor that C

is decreased, the zero frequency will be kept

the same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability of
the closed-loop system and will demonstrate the actual
overall supply performance.

A second, more severe transient is caused by switching in
loads with large (>1

F) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel
with C

OUT

, causing a rapid drop in V

OUT

. No regulator can

alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C

LOAD

to C

OUT

is greater than1:50, the switch rise time

should be controlled so that the load rise time is limited to
approximately 25 · C

LOAD

. Thus a 10

F capacitor would

require a 250

s rise time, limiting the charging current to

about 200mA.

APPLICATIO S I FOR ATIO

LTC3707

3707f

Automotive Considerations: Plugging into the
Cigarette Lighter

As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging into
the supply from hell. The main power line in an automobile
is the source of a number of nasty potential transients,
including load-dump, reverse-battery, and double-bat-
tery.

Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is

Figure 9. Automotive Application Protection

just what it says, while double-battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.

The network shown in Figure 9 is the most straight forward
approach to protect a DC/DC converter from the ravages
of an automotive power line. The series diode prevents
current from flowing during reverse-battery, while the
transient suppressor clamps the input voltage during
load-dump. Note that the transient suppressor should not
conduct during double-battery operation, but must still
clamp the input voltage below breakdown of the converter.
Although the LTC3707 has a maximum input voltage of
30V, most applications will be limited to 28V by the
MOSFET BVDSS.

3707 F09

LTC3707

TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A

50A I

RATING

12V

APPLICATIO S I FOR ATIO

LTC3707

3707f

Design Example

As a design example for one channel, assume V

12V(nominal), V

= 22V(max), V

OUT

= 1.8V, I

MAX

= 5A,

and f = 300kHz.

The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the FREQSET pin
to the INTV

pin for 300kHz operation. The minimum

inductance for 30% ripple current is:

f L

OUT

( )( )

A 4.7

H inductor will produce 23% ripple current and a

3.3

H will result in 33%. The peak inductor current will be

the maximum DC value plus one half the ripple current, or
5.84A, for the 3.3

H value. Increasing the ripple current

will also help ensure that the minimum on-time of 200ns
is not violated. The minimum on-time occurs at maximum
V

kHz

ON MIN

OUT

IN MAX

(

)

(

)

(

)

1 8

22 300

273

The R

SENSE

resistor value can be calculated by using the

maximum current sense voltage specification with some
accommodation for tolerances:

SENSE

5 84

0 01

Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pins specified input
current.

MAX

OUT

0 8

2 4

0 8

2 4

1 8

(

)

Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.

The power dissipation on the top side MOSFET can be
easily estimated. Choosing a Siliconix Si4412DY results
in; R

DS(ON)

= 0.042

, C

RSS

= 100pF. At maximum input

voltage with T(estimated) = 50

kHz

MAIN

( )

[

]

(

)

( ) ( )( )(

)

1 8

0 005 50

0 042

1 7 22

100

300

220

( .

)(

)

A short-circuit to ground will result in a folded back current
of:

0 01

200

3 3

3 2

(

)

with a typical value of R

DS(ON)

and

= (0.005/

C)(20) =

0.1. The resulting power dissipated in the bottom MOSFET
is:

SYNC

( ) ( )

(

)

1 8

3 2

1 1 0 042

434

which is less than under full-load conditions.

is chosen for an RMS current rating of at least 3A at

temperature assuming only this channel is on. C

OUT

chosen with an ESR of 0.02

for low output ripple. The

output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:

ORIPPLE

= R

ESR(

IL)

= 0.02

(1.67A) = 33mV

APPLICATIO S I FOR ATIO

LTC3707

3707f

PC Board Layout Checklist

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3707. These items are also illustrated graphically in
the layout diagram of Figure 10. The Figure 11 illustrates
the current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:

1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at C

? Do not attempt to split the input decoupling for the

two channels as it can cause a large resonant loop.

2. Are the signal and power grounds kept separate? The
combined LTC3707 signal ground pin and the ground
return of C

INTVCC

must return to the combined C

OUT

()

terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the C

capacitor should have short

leads and PC trace lengths. The output capacitor ()
terminals should be connected as close as possible to the
() terminals of the input capacitor by placing the capaci-
tors next to each other and away from the Schottky loop
described above.

3. Do the LTC3707 V

OSENSE

pins resistive dividers con-

nect to the (+) terminals of C

OUT

? The resistive divider

must be connected between the (+) terminal of C

OUT

and

Figure 10. LTC3707 Recommended Printed Circuit Layout Diagram

PGOOD

PULL-UP

(<7V)

INTVCC

VIN

INTV

3.3V

RUN/SS1

SENSE1

OSENSE1

FREQSET

STBYMD

FCB

TH1

SGND

3.3V

OUT

TH2

OSENSE2

SENSE2

PGOOD

TG1

SW1

BOOST1

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

LTC3707

OUT1

GND

OUT2

3707 F10

OUT2

SENSE

APPLICATIO S I FOR ATIO

LTC3707

3707f

Figure 11. Branch Current Waveforms

APPLICATIO S I FOR ATIO

signal ground and a small V

OSENSE

decoupling capacitor

should be as close as possible to the LTC3707 SGND pin.
The R2 and R4 connections should not be along the high
current input feeds from the input capacitor(s).

4. Are the SENSE

and SENSE

leads routed together

with minimum PC trace spacing? The filter capacitor
between SENSE

and SENSE

should be as close as

possible to the IC. Ensure accurate current sensing with
Kelvin connections at the SENSE resistor.

5. Is the INTV

decoupling capacitor connected close to

the IC, between

the INTV

and the power ground pins?

This capacitor carries the MOSFET drivers current peaks.
An additional 1

F ceramic capacitor placed immediately

next to the INTV

and PGND pins can help improve noise

performance substantially.

6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposites channel's voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the "output side"
of the LTC3707 and occupy minimum PC trace area.

SW1

SENSE1

OUT1

BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.

SW2

3707 F11

SENSE2

OUT2

LTC3707

3707f

APPLICATIO S I FOR ATIO

7. Use a modified "star ground" technique: a low imped-
ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV

decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.

PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the
operating voltage and current range expected in the appli-
cation. The frequency of operation should be maintained
over the input voltage range down to dropout and until the
output load drops below the low current operation thresh-
old--typically 10% to 20% of the maximum designed
current level in Burst Mode operation.

The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage
sensing inputs or inadequate loop compensation. Over-
compensation of the loop can be used to tame a poor PC
layout if regulator bandwidth optimization is not required.
Only after each controller is checked for their individual
performance should both controllers be turned on at the
same time. A particularly difficult region of operation is
when one controller channel is nearing its current com-
parator trip point when the other channel is turning on its
top MOSFET. This occurs around 50% duty cycle on either
channel due to the phasing of the internal clocks and may
cause minor duty cycle jitter.

Short-circuit testing can be performed to verify proper
overcurrent latchoff, or 5

A can be provided to the RUN/

SS pin(s) by resistors from V

to prevent the short-circuit

latchoff from occurring.

Reduce V

from its nominal level to verify operation of the

regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V

while

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher
output currents or only at higher input voltages. If prob-
lems coincide with high input voltages and low output
currents, look for capacitive coupling between the BOOST,
SW, TG, and possibly BG connections and the sensitive
voltage and current pins. The capacitor placed across the
current sensing pins needs to be placed immediately
adjacent to the pins of the IC. This capacitor helps to
minimize the effects of differential noise injection due to
high frequency capacitive coupling. If problems are en-
countered with high current output loading at lower input
voltages, look for inductive coupling between C

, Schottky

and the top MOSFET components to the sensitive current
and voltage sensing traces. In addition, investigate com-
mon ground path voltage pickup between these compo-
nents and the SGND pin of the IC.

An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still be
maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor--don't worry, the regulator
will still maintain control of the output voltage.

LTC3707

3707f

Figure 12. LTC3707 High Efficiency Low Noise 5V/3A, 3.3V/5A, 12/120mA Regulator

0.1

4.7

50V

D1
MBRM
140T3

MBRS1100T3

D2
MBRM
140T3

10V

CMDSH-3TR

0.1

0.01

0.015

INTV

3.3V

0.1

20k

105k, 1%

33pF

15k

33pF

15k

1000pF

0.1

20k

63.4k

RUN/SS1

SENSE1

OSENSE1

FREQSET

STBYMD

FCB

TH1

SGND

3.3V

OUT

TH2

OSENSE2

SENSE2

PGOOD

TG1

SW1

BOOST1

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

LTC3707

T1, 1:1.8

6.3

150

F, 6.3V

PANASONIC SP

25V

180

F, 4V

PANASONIC SP

GND

ON/OFF

OUT2

3.3V
5A; 6A PEAK

OUT3

12V
120mA

25V

OUT1

5V
3A; 4A PEAK

7V TO
28V

1628 F12

: 7V TO 28V

OUT

: 5V, 3A/3.3V, 6A/12V, 120mA

SWITCHING FREQUENCY = 300kHz
MI, M2, M3, M4: NDS8410A
L1: SUMIDA CEP123-6R3MC
T1: 10

H 1:1.8 -- DALE LPE6562-A262 GAPPED E-CORE OR BH ELECTRONICS #501-0657 GAPPED TOROID

LT1121

220k

100k

PGOOD

100k

PULL-UP

(<7V)

59k

180pF

0.01

TYPICAL APPLICATIO

LTC3707

3707f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTIO

0.386 0.393*

(9.804 9.982)

GN28 (SSOP) 1098

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

9 10 11 12

0.229 0.244

(5.817 6.198)

0.150 0.157**

(3.810 3.988)

19 18 17

13 14

1615

0.016 0.050

(0.406 1.270)

0.015

0.004

(0.38

0.10)

TYP

0.0075 0.0098

(0.191 0.249)

0.053 0.069

(1.351 1.748)

0.008 0.012

(0.203 0.305)

0.004 0.009

(0.102 0.249)

0.0250

(0.635)

BSC

0.033

(0.838)

REF

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

LTC3707

3707f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear.com

LINEAR TECHNOLOGY CORPORATION 2001

LT/TP 1101 1K · PRINTED IN USA

Figure 13. LTC3707 5V/4A, 3.3V/4A Regulator

RELATED PARTS

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DESCRIPTION

COMMENTS

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High Efficiency 5V to 3.3V Conversion at Up to 15A

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3.5V, Current Mode Ensures

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and PolyPhase are trademarks of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.

0.1

4.7

50V

M1A

M1B

M2A

M2B

10V

0.1

0.015

INTV

3.3V

0.1

20k

105k

33pF

15k

33pF

15k

220pF

1000pF

0.1

20k

63.4k

RUN/SS1

SENSE1

OSENSE1

FREQSET

STBYMD

FCB

TH1

SGND

3.3V

OUT

TH2

OSENSE2

SENSE2

PGOOD

TG1

SW1

BOOST1

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

LTC3707

F 6.3V

F, 4V

GND

OUT2

3.3V
3A; 4A PEAK

OUT1

5V
3A; 4A PEAK

5.2V TO
28V

3707 F13

: 5.2V TO 28V

OUT

: 5V, 4A/3.3V, 4A

SWITCHING FREQUENCY = 300kHz
MI, M2: FDS6982S

L1, L2: 8

H SUMIDA CEP1238R0MC

OUTPUT CAPACITORS: PANASONIC SP SERIES

27pF

0.1

CMDSH-3TR

0.01

PGOOD

PULL-UP

(<7V)

TYPICAL APPLICATIO

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC3707EGN

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC3707EGN