LTC3728L/LTC3728LX

3728lxfa

Figure 1. High Efficiency Dual 5V/3.3V Step-Down Converter

Dual, 180

Phased Controllers Reduce Required

Input Capacitance and Power Supply Induced Noise

OPTI-LOOP

Compensation Minimizes C

OUT

1% Output Voltage Accuracy (LTC3728LC)

Power Good Output Voltage Indicator

Phase-Lockable Fixed Frequency 250kHz to 550kHz

Dual N-Channel MOSFET Synchronous Drive

Wide V

Range: 4.5V to 28V Operation

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Soft-Start Current Ramping

Foldback Output Current Limiting

Latched Short-Circuit Shutdown with Defeat Option

Output Overvoltage Protection

Low Shutdown I

: 20

5V and 3.3V Standby Regulators

3 Selectable Operating Modes: Constant Frequency,
Burst Mode

Operation and PWM

5mm

5mm QFN and 28-Lead Narrow SSOP

Packages

The LTC

3728L/LTC3728LX are dual high performance

step-down switching regulator controllers that drive all
N-channel synchronous power MOSFET stages. A con-
stant frequency current mode architecture allows phase-
lockable frequency of up to 550kHz. Power loss and noise
due to the ESR of the input capacitors are minimized by
operating the two controller output stages out of phase.

OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance and
ESR values. The precision 0.8V reference and power good
output indicator are compatible with future microproces-
sor generations, and a wide 4.5V to 28V (30V maximum)
input supply range encompasses all battery chemistries.

A RUN/SS pin for each controller provides both soft-start
and optional timed, short-circuit shutdown. Current
foldback limits MOSFET dissipation during short-circuit
conditions when overcurrent latchoff is disabled. Output
overvoltage protection circuitry latches on the bottom
MOSFET until V

OUT

returns to normal. The FCB mode pin

can select among Burst Mode, constant frequency mode
and continuous inductor current mode or regulate a
secondary winding. The LTC3728L/LTC3728LX include a
power good output pin that indicates when both outputs
are within 7.5% of their designed set point.

Notebook and Palmtop Computers

Telecom Systems

Portable Instruments

Battery-Operated Digital Devices

DC Power Distribution Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.

4.7

, 0.1

105k

1000pF

3.2

220pF

CERAMIC

50V
CERAMIC

OUT1

6V
SP

SENSE1

0.01

R1
20k
1%

15k

OUT1

5V
5A

, 0.1

63.4k

3.2

220pF

1000pF

OUT

SENSE2

0.01

20k

15k

OUT2

3.3V
5A

TG1

TG2

BOOST1

BOOST2

SW1

SW2

BG1

BG2

SGND

PGND

SENSE1

SENSE2

SENSE1

SENSE2

OSENSE1

OSENSE2

TH1

TH2

PGOOD INTV

RUN/SS1

RUN/SS2

5.2V TO 28V

M1, M2: FDS6982S

3728 F01

SS1

0.1

SS2

0.1

LTC3728L/

LTC3728LX

PLLIN

500kHz

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

Dual, 550kHz, 2-Phase

Synchronous Regulators

LTC3728L/LTC3728LX

3728lxfa

Input Supply Voltage (V

) ........................ 30V to 0.3V

Top Side Driver Voltages
(BOOST1, BOOST2) .................................. 36V to 0.3V
Switch Voltage (SW1, SW2) ........................ 30V to 5V
INTV

CC,

EXTV

, RUN/SS1, RUN/SS2, (BOOST1-SW1),

(BOOST2-SW2), PGOOD ............................ 7V to 0.3V
SENSE1

, SENSE2

, SENSE1

SENSE2

Voltages ....................... (1.1)INTV

to 0.3V

PLLIN, PLLFLTR, FCB, Voltage ........... INTV

to 0.3V

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

TH1,

TH2

, V

OSENSE1

, V

OSENSE2

Voltages ... 2.7V to 0.3V

Peak Output Current <10

s (TG1, TG2, BG1, BG2) .. 3A

INTV

Peak Output Current ................................ 40mA

Operating Temperature Range (Note 7)

LTC3728LC/LTC3728LXC ....................... 0

C to 85

LTC3728LE ........................................ 40

C to 85

Junction Temperature (Note 2) ............................ 125

Storage Temperature Range ................ 65

C to 125

Reflow Peak Body Temperature (UH Package) .... 260

Lead Temperature (Soldering, 10 sec)

(GN Package) ................................................... 300

32 31 30 29 28 27 26 25

10 11 12 13

TOP VIEW

14 15 16

OSENSE1

PLLFLTR

PLLIN

FCB

TH1

SGND

3.3V

OUT

TH2

BOOST1

BG1

EXTV

INTV

PGND

BG2

BOOST2

SENSE1

RUN/SS1

PGOOD

TG1

SW1

OSENSE2

SENSE2

RUN/SS2

TG2

SW2

UH PACKAGE

32-LEAD (5mm

5mm) PLASTIC QFN

ORDER PART

NUMBER

LTC3728LCUH
LTC3728LEUH
LTC3728LXCUH

JMAX

= 125

= 34

C/W

EXPOSED PAD IS SGND (PIN 33),

MUST BE SOLDERED TO PCB

The

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 15V, V

RUN/SS1, 2

= 5V unless otherwise noted.

ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loops

OSENSE1, 2

Regulated Feedback Voltage

(Note 3); I

TH1, 2

Voltage = 1.2V (LTC3728LC)

0.792

0.800

0.808

(Note 3); I

TH1, 2

Voltage = 1.2V (LTC3728LE/LTC3728LX)

0.788

0.800

0.812

VOSENSE1, 2

Feedback Current

(Note 3)

REFLNREG

Reference Voltage Line Regulation V

= 3.6V to 30V (Note 3)

0.002

0.02

%/V

LOADREG

Output Voltage Load Regulation

(Note 3)
Measured in Servo Loop;

Voltage = 1.2V to 0.7V

0.1

0.5

Measured in Servo Loop;

Voltage = 1.2V to 2.0V

0.1

0.5

m1, 2

Transconductance Amplifier g

TH1, 2

= 1.2V; Sink/Source 5uA; (Note 3)

1.3

mmho

Consult LTC Marketing for parts specified with wider operating temperature ranges.

UH PART

MARKING

3728L
3728LE
3728LX

ORDER PART

NUMBER

LTC3728LCGN
LTC3728LEGN

TOP VIEW

GN PACKAGE

28-LEAD NARROW PLASTIC SSOP

RUN/SS1

SENSE1

SENSE

OSENSE1

PLLFLTR

PLLIN

FCB

TH1

SGND

3.3V

OUT

TH2

OSENSE2

SENSE2

PGOOD

TG1

SW1

BOOST1

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

JMAX

= 125

= 95

C/W

LTC3728L/LTC3728LX

3728lxfa

The

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 15V, V

RUN/SS1, 2

= 5V unless otherwise noted.

ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

mGBW1, 2

Transconductance Amplifier GBW

TH1, 2

= 1.2V; (Note 3)

MHz

Input DC Supply Current

(Note 4)

Normal Mode

= 15V; EXTV

Tied to V

OUT1

; V

OUT1

= 5V

450

Shutdown

RUN/SS1, 2

= 0V

FCB

Forced Continuous Threshold

0.76

0.800

0.84

FCB

Forced Continuous Pin Current

FCB

= 0.85V

0.50

0.18

0.1

BINHIBIT

Burst Inhibit (Constant Frequency)

Measured at FCB pin

4.3

4.8

Threshold

UVLO

Undervoltage Lockout

Ramping Down

3.5

OVL

Feedback Overvoltage Lockout

Measured at V

OSENSE1, 2

0.84

0.86

0.88

SENSE

Sense Pins Total Source Current

(Each Channel); V

SENSE1

, 2

= V

SENSE1

, 2

= 0V

MAX

Maximum Duty Factor

In Dropout

99.4

RUN/SS1, 2

Soft-Start Charge Current

RUN/SS1, 2

= 1.9V

0.5

1.2

RUN/SS1, 2

ON RUN/SS Pin ON Threshold

RUN/SS1,

RUN/SS2

Rising

1.0

1.5

2.0

RUN/SS1, 2

LT RUN/SS Pin Latchoff Arming Threshold V

RUN/SS1,

RUN/SS2

Rising from 3V

4.1

4.75

SCL1, 2

RUN/SS Discharge Current

Soft Short Condition V

OSENSE1, 2

= 0.5V;

0.5

RUN/SS1, 2

= 4.5V

SDLHO

Shutdown Latch Disable Current

OSENSE1, 2

= 0.5V

1.6

SENSE(MAX)

Maximum Current Sense Threshold

OSENSE1, 2

= 0.7V,V

SENSE1, 2

= 5V

OSENSE1, 2

= 0.7V,V

SENSE1, 2

= 5V

TG Transition Time:

(Note 5)

TG1, 2 t

Rise Time

LOAD

= 3300pF

100

TG1, 2 t

Fall Time

LOAD

= 3300pF

100

BG Transition Time:

(Note 5)

BG1, 2 t

Rise Time

LOAD

= 3300pF

100

BG1, 2 t

Fall Time

LOAD

= 3300pF

TG/BG t

Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time

LOAD

= 3300pF Each Driver

BG/TG t

Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time

LOAD

= 3300pF Each Driver

ON(MIN)

Minimum On-Time

Tested with a Square Wave (Note 6)

100

INTV

Linear Regulator

INTVCC

Internal V

Voltage

6V < V

< 30V, V

EXTVCC

= 4V

4.8

5.0

5.2

LDO

INT

INTV

Load Regulation

= 0 to 20mA, V

EXTVCC

= 4V

0.2

2.0

LDO

EXT

EXTV

Voltage Drop

= 20mA, V

EXTVCC

= 5V

100

200

EXTVCC

EXTV

Switchover Voltage

= 20mA, EXTV

Ramping Positive

4.5

4.7

LDOHYS

EXTV

Hysteresis

0.2

Oscillator and Phase-Locked Loop

NOM

Nominal Frequency

PLLFLTR

= 1.2V

360

400

440

kHz

LOW

Lowest Frequency

PLLFLTR

= 0V

230

260

290

kHz

HIGH

Highest Frequency

PLLFLTR

2.4V

480

550

590

kHz

PLLIN

PLLIN Input Resistance

PLLFLTR

Phase Detector Output Current

Sinking Capability

PLLIN

< f

OSC

Sourcing Capability

PLLIN

> f

OSC

LTC3728L/LTC3728LX

3728lxfa

Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.

Note 2: T

is calculated from the ambient temperature T

and power

dissipation P

according to the following formulas:

LTC3728LUH/LTC3728LXUH: T

= T

+ (P

· 34

C/W)

LTC3728LGN: T

= T

+ (P

· 95

C/W)

Note 3: The IC is tested in a feedback loop that servos V

ITH1, 2

to a

specified voltage and measures the resultant V

OSENSE1, 2.

Note 4: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 5: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.

Note 6: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current

40% of I

MAX

(see minimum on-time

considerations in the Applications Information section).

Note 7: The LTC3728LC/LTC3728LXC are guaranteed to meet
performance specifications from 0

C to 85

C. The LTC3728LE is

guaranteed to meet performance specifications over the 40

C to 85

operating temperature range as assured by design, characterization and
correlation with statistical process controls.

Efficiency vs Output Current
and Mode (Figure 13)

OUTPUT CURRENT (A)

0.001

EFFICIENCY (%)

100

0.01

0.1

3728L G01

FORCED
CONTINUOUS
MODE (PWM)

CONSTANT
FREQUENCY
(BURST DISABLE)

Burst Mode

OPERATION

= 15V

OUT

= 5V

f = 250kHz

OUTPUT CURRENT (A)

0.001

EFFICIENCY (%)

3728L G02

0.01

0.1

100

= 10V

= 15V

= 7V

= 20V

OUT

= 5V

f = 250kHz

INPUT VOLTAGE (V)

EFFICIENCY (%)

3728L G03

100

OUT

= 5V

OUT

= 3A

f = 250kHz

Efficiency vs Output Current
(Figure 13)

Efficiency vs Input Voltage
(Figure 13)

TYPICAL PERFOR A CE CHARACTERISTICS

The

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T

= 25

C. V

= 15V, V

RUN/SS1, 2

= 5V unless otherwise noted.

ELECTRICAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

3.3V Linear Regulator

3.3OUT

3.3V Regulator Output Voltage

No Load

3.2

3.35

3.45

3.3IL

3.3V Regulator Load Regulation

3.3

= 0 to 10mA

0.5

3.3VL

3.3V Regulator Line Regulation

6V < V

< 30V

0.05

0.2

PGOOD Output

PGL

PGOOD Voltage Low

PGOOD

= 2mA

0.1

0.3

PGOOD

PGOOD Leakage Current

PGOOD

= 5V

PGOOD Trip Level, Either Controller

OSENSE

with Respect to Set Output Voltage

OSENSE

Ramping Negative

7.5

9.5

OSENSE

Ramping Positive

7.5

9.5

LTC3728L/LTC3728LX

3728lxfa

Internal 5V LDO Line Regulation

Maximum Current Sense Threshold
vs Duty Factor

Maximum Current Sense Threshold
vs Percent of Nominal Output
Voltage (Foldback)

INPUT VOLTAGE (V)

4.8

4.9

5.1

3728L

G07

4.7

4.6

4.5

4.4

5.0

INTV

VOLTAGE (V)

LOAD

= 1mA

DUTY FACTOR (%)

SENSE

(mV)

3728L G08

100

PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

SENSE

(mV)

100

3728L

G09

Maximum Current Sense Threshold
vs V

RUN/SS

(Soft-Start)

RUN/SS

(V)

SENSE

(mV)

3728L G10

SENSE(CM)

= 1.6V

Maximum Current Sense Threshold
vs Sense Common Mode Voltage

COMMON MODE VOLTAGE (V)

SENSE

(mV)

3728L G11

Current Sense Threshold
vs I

Voltage

ITH

(V)

SENSE

(mV)

3728L G12

0.5

1.5

2.5

TYPICAL PERFOR A CE CHARACTERISTICS

INTV

and EXTV

Switch

Voltage vs Temperature

Supply Current vs Input Voltage
and Mode (Figure 13)

INPUT VOLTAGE (V)

SUPPLY CURRENT (

400

1000

3728L G04

200

800

600

SHUTDOWN

BOTH
CONTROLLERS ON

EXTV

Voltage Drop

CURRENT (mA)

EXTV

VOLTAGE DROP (mV)

150

200

3728L

G05

100

TEMPERATURE (

INTV

AND EXTV

SWITCH VOLTAGE (V)

4.95

5.00

5.05

3728L G06

4.90

4.85

100

125

4.80

4.70

4.75

INTV

VOLTAGE

EXTV

SWITCHOVER THRESHOLD

LTC3728L/LTC3728LX

3728lxfa

TEMPERATURE (

SENSE

(mV)

3728L G17

100

125

OUTPUT CURRENT (A)

DROPOUT VOLTAGE (V)

0.5

1.0

1.5

2.0

3728L G18

2.5

3.0

3.5

4.0

SENSE

= 0.015

SENSE

= 0.010

OUT

= 5V

Maximum Current Sense
Threshold vs Temperature

Dropout Voltage vs Output Current
(Figure 14)

Soft-Start Up (Figure 13)

OUT

5V/DIV

RUN/SS

5V/DIV

2A/DIV

= 15V

5ms/DIV

3728L G19

OUT

= 5V

Load Step (Figure 13)

OUT

200mV/DIV

2A/DIV

= 15V

s/DIV

3728L G20

OUT

= 5V

PLLFLTR

= 0V

LOAD STEP = 0A TO 3A
Burst Mode OPERATION

Load Step (Figure 13)

OUT

200mV/DIV

2A/DIV

= 15V

s/DIV

3728L G21

OUT

= 5V

PLLFLTR

= 0V

LOAD STEP = 0A TO 3A
CONTINUOUS MODE

RUN/SS Current vs Temperature

TEMPERATURE (

RUN/SS CURRENT (

0.2

0.6

0.8

1.0

100

1.8

3728L

G25

0.4

125

1.2

1.4

1.6

TYPICAL PERFOR A CE CHARACTERISTICS

Load Regulation

LOAD CURRENT (A)

NORMALIZED V

OUT

(%)

0.2

0.1

3728L G13

0.3

0.4

0.0

FCB = 0V
V

= 15V

FIGURE 13

ITH

vs V

RUN/SS

RUN/SS

(V)

ITH

(V)

0.5

1.0

1.5

2.0

2.5

3728L G14

OSENSE

= 0.7V

SENSE Pins Total Source Current

SENSE

COMMON MODE VOLTAGE (V)

SENSE

(

3728L G15

100

LTC3728L/LTC3728LX

3728lxfa

Current Sense Pin Input Current
vs Temperature

EXTV

Switch Resistance

vs Temperature

TEMPERATURE (

CURRENT SENSE INPUT CURRENT (

3728L G26

100

125

OUT

= 5V

TEMPERATURE (

EXTV

SWITCH RESISTANCE (

)

3728L G27

100

125

Oscillator Frequency
vs Temperature

TEMPERATURE (

400

500

700

3728L G28

300

200

100

125

100

600

FREQUENCY (kHz)

PLLFLTR

= 2.4V

PLLFLTR

= 1.2V

PLLFLTR

= 0V

Undervoltage Lockout
vs Temperature

TEMPERATURE (

UNDERVOLTAGE LOCKOUT (V)

3.40

3.45

3.50

3728L G29

3.35

3.30

100

125

3.25

3.20

Shutdown Latch Thresholds
vs Temperature

TEMPERATURE (

SHUTDOWN LATCH THRESHOLDS (V) 0.5

1.5

2.0

2.5

100

4.5

3728L

G30

1.0

125

3.0

3.5

4.0

LATCH ARMING

LATCHOFF

THRESHOLD

TYPICAL PERFOR A CE CHARACTERISTICS

Input Source/Capacitor
Instantaneous Current (Figure 13)

2A/DIV

200mV/DIV

SW1

10V/DIV

= 15V

s/DIV

3728L G22

OUT1

= 5V, V

OUT2

= 3.3V

PLLFLTR

= 0V

OUT5

= I

OUT3.3

= 2A

Burst Mode Operation (Figure 13)

OUT

20mV/DIV

0.5A/DIV

= 15V

s/DIV

3728L G23

OUT

= 5V

PLLFLTR

= 0V

FCB

= OPEN

OUT

= 20mA

Constant Frequency (Burst Inhibit)
Operation (Figure 13)

OUT

20mV/DIV

0.5A/DIV

= 15V

s/DIV

3728L G24

OUT

= 5V

PLLFLTR

= 0V

FCB

= 5V

OUT

= 20mA

SW2

10V/DIV

LTC3728L/LTC3728LX

3728lxfa

OSENSE1

, V

OSENSE2

: Error Amplifier Feedback Input. Re-

ceives the remotely-sensed feedback voltage for each
controller from an external resistive divider across the
output.

PLLFLTR: Filter Connection for Phase-Locked Loop. Al-
ternatively, this pin can be driven with an AC or DC voltage
source to vary the frequency of the internal oscillator.

PLLIN: External Synchronization Input to Phase Detector.
This pin is internally terminated to SGND with 50k

. The

phase-locked loop will force the rising top gate signal of
controller 1 to be synchronized with the rising edge of the
PLLIN signal.

FCB: Forced Continuous Control Input. This input acts on
both controllers and is normally used to regulate a
secondary winding. Pulling this pin below 0.8V will force
continuous synchronous operation.

TH1,

TH2

: Error Amplifier Output and Switching Regulator

Compensation Point. Each associated channels' current
comparator trip point increases with this control voltage.

SGND: Small Signal Ground. Common to both con-
trollers, this pin must be routed separately from high
current grounds to the common () terminals of the
C

OUT

capacitors.

3.3V

OUT

: Lnear Regulator Output. Capable of supplying

10mA DC with peak currents as high as 50mA.

NC: No Connect.

SENSE2

, SENSE1

: The () Input to the Differential

Current Comparators.

SENSE2

, SENSE1

: The (+) Input to the Differential

Current Comparators. The I

pin voltage and controlled

offsets between the SENSE

and SENSE

pins in conjunc-

tion with R

SENSE

set the current trip threshold.

RUN/SS2, RUN/SS1: Combination of soft-start, run con-
trol inputs and short-circuit detection timers. A capacitor
to ground at each of these pins sets the ramp time to full
output current. Forcing either of these pins back below
1.0V causes the IC to shut down the circuitry required for
that particular controller. Latchoff overcurrent protection

is also invoked via this pin as described in the Applications
Information section.

TG2, TG1: High Current Gate Drives for Top N-Channel
MOSFETs. These are the outputs of floating drivers with a
voltage swing equal to INTV

0.5V superimposed on

the switch node voltage SW.

SW2, SW1: Switch Node Connections to Inductors. Volt-
age swing at these pins is from a Schottky diode (external)
voltage drop below ground to V

BOOST2, BOOST1: Bootstrapped Supplies to the Top Side
Floating Drivers. Capacitors are connected between the
boost and switch pins and Schottky diodes are tied be-
tween the boost and INTV

pins. Voltage swing at the

boost pins is from INTV

to (V

+ INTV

BG2, BG1: High Current Gate Drives for Bottom (Synchro-
nous) N-Channel MOSFETs. Voltage swing at these pins is
from ground to INTV

PGND: Driver Power Ground. Connects to the sources of
bottom (synchronous) N-channel MOSFETs, anodes of the
Schottky rectifiers and the () terminal(s) of C

INTV

: Output of the Internal 5V Linear Low Dropout

Regulator and the EXTV

Switch. The driver and control

circuits are powered from this voltage source. Must be
decoupled to power ground with a minimum of 4.7

F tanta-

lum or other low ESR capacitor.

EXTV

: External Power Input to an Internal Switch Con-

nected to INTV

. This switch closes and supplies V

power, bypassing the internal

low dropout regulator, when-

ever EXTV

is higher than 4.7V. See EXTV

connection

in Applications section. Do not exceed 7V on this pin.

: Main Supply Pin. A bypass capacitor should be tied

between this pin and the signal ground pin.

PGOOD: Open-Drain Logic Output. PGOOD is pulled to
ground when the voltage on either V

OSENSE

pin is not

within

7.5% of its set point.

Exposed Pad (UH Package Only): Signal Ground. Must be
soldered to the PCB, providing a local ground for the
control components of the IC, and be tied to the PGND pin
under the IC.

PI FU CTIO S

LTC3728L/LTC3728LX

3728lxfa

Figure 2

FU CTIO AL DIAGRA

(Refer to Functional Diagram)

OPERATIO

Main Control Loop

The IC uses a constant frequency, current mode step-
down architecture with the two controller channels oper-
ating 180 degrees out of phase. During normal operation,
each top MOSFET is turned on when the clock for that
channel sets the RS latch, and turned off when the main
current comparator, I

, resets the RS latch. The peak

inductor current at which I

resets the RS latch is con-

trolled by the voltage on the I

pin, which is the output of

each error amplifier EA. The V

OSENSE

pin receives the

voltage feedback signal, which is compared to the internal
reference voltage by the EA. When the load current in-
creases, it causes a slight decrease in V

OSENSE

relative to

the 0.8V reference, which in turn causes the I

voltage to

SWITCH

LOGIC

0.8V

4.8V

4.5V

BINH

CLK2

CLK1

0.18

FCB

REF

INTERNAL

SUPPLY

3.3V

OUT

INTV

FCB

EXTV

INTV

SGND (UH PACKAGE PAD)

LDO
REG

SHDN

0.55V

TOP

BOOST

PGND

BOT

INTV

OUT

3728 FD/F02

SENSE

OSENSE

DROP

OUT

DET

RUN

SOFT

START

BOT

TOP ON

OSCILLATOR

PHASE DET

PLLFLTR

PLLIN

FCB

0.86V

0.80V

1.2

4(V

)

RST

SHDN

RUN/SS

4(V

)

0.86V

SLOPE

COMP

3mV

SENSE

INTV

30k

45k

2.4V

45k

30k

DUPLICATE FOR SECOND
CONTROLLER CHANNEL

50k

PGOOD

OSENSE1

OSENSE2

0.86V

0.74V

0.86V

0.74V

LTC3728L/LTC3728LX

3728lxfa

(Refer to Functional Diagram)

increase until the average inductor current matches the
new load current. After the top MOSFET has turned off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current compara-
tor I

, or the beginning of the next cycle.

The top MOSFET drivers are biased from floating boot-
strap capacitor C

, which normally is recharged during

each off cycle through an external diode when the top
MOSFET turns off. As V

decreases to a voltage close to

OUT

, the loop may enter dropout and attempt to turn on

the top MOSFET continuously. The dropout detector de-
tects this and forces the top MOSFET off for about 400ns
every tenth cycle to allow C

to recharge.

The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.2

current source to charge soft-start capacitor C

. When

reaches 1.5V, the main control loop is enabled with the

voltage clamped at approximately 30% of its maximum

value. As C

continues to charge, the I

pin voltage is

gradually released allowing normal, full-current opera-
tion. When both RUN/SS1 and RUN/SS2 are low, all
controller functions are shut down, including the 5V and
3.3V regulators.

Low Current Operation

The FCB pin is a multifunction pin providing two func-
tions: 1) to provide regulation for a secondary winding by
temporarily forcing continuous PWM operation on
both controllers; and 2) to select between

two modes of

low current operation. When the FCB pin voltage is below
0.8V, the controller forces continuous PWM current
mode operation. In this mode, the top and bottom
MOSFETs are alternately turned on to maintain the output
voltage independent of direction of inductor current.
When the FCB pin is below V

INTVCC

2V but greater than

0.8V, the controller enters Burst Mode operation. Burst
Mode operation sets a minimum output current level
before inhibiting the top switch and turns off the synchro-
nous MOSFET(s) when the inductor current goes nega-
tive. This combination of requirements will, at low cur-
rents, force the I

pin below a voltage threshold that will

OPERATIO

temporarily inhibit turn-on of both output MOSFETs until
the output voltage drops. There is 60mV of hysteresis in
the burst comparator B tied to the I

pin. This hysteresis

produces output signals to the MOSFETs that turn them
on for several cycles, followed by a variable "sleep"
interval depending upon the load current. The resultant
output voltage ripple is held to a very small value by
having the hysteretic comparator after the error amplifier
gain block.

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be
synchronized to an external source via the PLLIN pin. The
output of the phase detector at the PLLFLTR pin is also the
DC frequency control input of the oscillator that operates
over a 260kHz to 550kHz range corresponding to a DC
voltage input from 0V to 2.4V. When locked, the PLL aligns
the turn on of the top MOSFET to the rising edge of the
synchronizing signal. When PLLIN is left open, the PLLFLTR
pin goes low, forcing the oscillator to minimum frequency.

Constant Frequency Operation

When the FCB pin is tied to INTV

, Burst Mode operation

is disabled and the forced minimum output current
requirement is removed. This provides constant frequency,
discontinuous current (preventing reverse inductor cur-
rent) operation over the widest possible output current
range. This constant frequency operation is not as efficient
as Burst Mode operation, but does provide a lower noise,
constant frequency operating mode down to approxi-
mately 1% of the designed maximum output current.

Continuous Current (PWM) Operation

Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, current will be
forced back into the main power supply potentially boost-
ing the input supply to dangerous voltage levels--
BEWARE!

LTC3728L/LTC3728LX

3728lxfa

INTV

/EXTV

Power

Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTV

pin.

When the EXTV

pin is left open, an internal 5V low

dropout linear regulator supplies INTV

power. If EXTV

is taken above 4.7V, the 5V regulator is turned off and an
internal switch is turned on connecting EXTV

to INTV

This allows the INTV

power to be derived from a high

efficiency external source such as the output of the regu-
lator itself or a secondary winding, as described in the
Applications Information section.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned on
until the overvoltage condition is cleared.

Power Good (PGOOD) Pin

The PGOOD pin is connected to an open drain of an internal
MOSFET. The MOSFET turns on and pulls the pin low when
either output is not within

7.5% of the nominal output

level as determined by the resistive feedback divider.
When both outputs meet the

7.5% requirement, the

MOSFET is turned off within 10

s and the pin is allowed to

be pulled up by an external resistor to a source of up to 7V.

Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff

The RUN/SS capacitors are used initially to limit the inrush
current of each switching regulator. After the controller
has been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SS capacitor is used in a short-circuit time-out
circuit. If the output voltage falls to less than 70% of its
nominal output voltage, the RUN/SS capacitor begins
discharging on the assumption that the output is in an
overcurrent and/or short-circuit condition. If the condi-
tion lasts for a long enough period as determined by the
size of the RUN/SS capacitor, the controller will be shut
down until the RUN/SS pin(s) voltage(s) are recycled.

This built-in latchoff can be overridden by providing a
>5

A pull-up at a compliance of 5V to the RUN/SS pin(s).

This current shortens the soft start period but also pre-
vents net discharge of the RUN/SS capacitor(s) during an
overcurrent and/or short-circuit condition. Foldback cur-
rent limiting is also activated when the output voltage falls
below 70% of its nominal level whether or not the short-
circuit latchoff circuit is enabled. Even if a short is present
and the short-circuit latchoff is not enabled, a safe, low
output current is provided due to internal current foldback
and actual power wasted is low due to the efficient nature
of the current mode switching regulator.

THEORY AND BENEFITS OF 2-PHASE OPERATION

The LTC1628 and the LTC3728L family of dual high
efficiency DC/DC controllers brings the considerable ben-
efits of 2-phase operation to portable applications for the
first time. Notebook computers, PDAs, handheld termi-
nals and automotive electronics will all benefit from the
lower input filtering requirement, reduced electromag-
netic interference (EMI) and increased efficiency associ-
ated with 2-phase operation.

Why the need for 2-phase operation? Up until the 2-phase
family, constant-frequency dual switching regulators op-
erated both channels in phase (i.e., single-phase opera-
tion). This means that both switches turned on at the same
time, causing current pulses of up to twice the amplitude
of those for one regulator to be drawn from the input
capacitor and battery. These large amplitude current pulses
increased the total RMS current flowing from the input
capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.

With 2-phase operation, the two channels of the dual-
switching regulator are operated 180 degrees out of
phase. This effectively interleaves the current pulses
drawn by the switches, greatly reducing the overlap time
where they add together.

The result is a significant reduc-

tion in total RMS input current, which in turn allows less
expensive input capacitors to be used, reduces shielding
requirements for EMI and improves real world operating
efficiency.

(Refer to Functional Diagram)

OPERATIO

LTC3728L/LTC3728LX

3728lxfa

Figure 3 compares the input waveforms for a representa-
tive single-phase dual switching regulator to the LTC1628
2-phase dual switching regulator. An actual measurement
of the RMS input current under these conditions shows
that 2-phase operation dropped the input current from
2.53A

RMS

to 1.55A

RMS

. While this is an impressive reduc-

tion in itself, remember that the power losses are propor-
tional to I

RMS

, meaning that the actual power wasted is

reduced by a factor of 2.66. The reduced input ripple
voltage also means less power is lost in the input power
path, which could include batteries, switches, trace/con-
nector resistances and protection circuitry. Improvements
in both conducted and radiated EMI also directly accrue as
a result of the reduced RMS input current and voltage.

Of course, the improvement afforded by 2-phase opera-
tion is a function of the dual switching regulator's relative
duty cycles which, in turn, are dependent upon the input
voltage V

(Duty Cycle = V

OUT

). Figure 4 shows how

the RMS input current varies for single-phase and 2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.

It can readily be seen that the advantages of 2-phase
operation are not just limited to a narrow operating range,
but in fact extend over a wide region. A good rule of thumb
for most applications is that 2-phase operation will reduce
the input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.

A final question: If 2-phase operation offers such an
advantage over single-phase operation for dual switching

regulators, why hasn't it been done before? The answer is
that, while simple in concept, it is hard to implement.
Constant-frequency current mode switching regulators
require an oscillator derived "slope compensation" signal
to allow stable operation of each regulator at over 50%
duty cycle. This signal is relatively easy to derive in single-
phase dual switching regulators, but required the develop-
ment of a new and proprietary technique to allow 2-phase
operation. In addition, isolation between the two channels
becomes more critical with 2-phase operation because
switch transitions in one channel could potentially disrupt
the operation of the other channel.

These 2-phase parts are proof that these hurdles have
been surmounted. They offer unique advantages for the
ever-expanding number of high efficiency power supplies
required in portable electronics.

(b)

(a)

5V SWITCH

20V/DIV

3.3V SWITCH

20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

500mV/DIV

IN(MEAS)

= 1.55A

RMS

DC236 F03b

IN(MEAS)

= 2.53A

RMS

DC236 F03a

Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators
Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows
Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency

(Refer to Functional Diagram)

OPERATIO

Figure 4. RMS Input Current Comparison

INPUT VOLTAGE (V)

INPUT RMS CURRENT (A)

3.0

2.5

2.0

1.5

1.0

0.5

3728 F04

SINGLE PHASE
DUAL CONTROLLER

2-PHASE

DUAL CONTROLLER

= 5V/3A

= 3.3V/3A

LTC3728L/LTC3728LX

3728lxfa

Figure 1 on the first page is a basic LTC3728L/LTC3728LX
application circuit. External component selection is driven
by the load requirement, and begins with the selection of
R

SENSE

and the inductor value. Next, the power MOSFETs

and D1 are selected. Finally, C

and C

OUT

are selected.

The circuit shown in Figure 1 can be configured for
operation up to an input voltage of 28V (limited by the
external MOSFETs).

SENSE

Selection For Output Current

SENSE

is chosen based on the required output current.

The current comparator has a maximum threshold of
75mV/R

SENSE

and an input common mode range of SGND

to 1.1(INTV

). The current comparator threshold sets the

peak of the inductor current, yielding a maximum average
output current I

MAX

equal to the peak value less half the

peak-to-peak ripple current,

Allowing a margin for variations in the IC and external
component values yields:

SENSE

MAX

When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to
the internal compensation required to meet stability crite-
rion for buck regulators operating at greater than 50%
duty factor. A curve is provided to estimate this reduction
in peak output current level depending upon the operating
duty factor.

Operating Frequency

The IC uses a constant frequency phase-lockable architec-
ture with the frequency determined by an internal capaci-
tor. This capacitor is charged by a fixed current plus an
additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to Phase-Locked Loop
and Frequency Synchronization in the Applications Infor-
mation section for additional information.

A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure 5. As the operating frequency

is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 550kHz.

Inductor Value Calculation

The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.

The inductor value has a direct effect on ripple current. The
inductor ripple current

decreases with higher induc-

tance or frequency and increases with higher V

f L

OUT

( )( )

Accepting larger values of

allows the use of low

inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is

=0.3(I

MAX

). The maximum

occurs at the maximum input voltage.

APPLICATIO S I FOR ATIO

Figure 5. PLLFLTR Pin Voltage vs Frequency

OPERATING FREQUENCY (kHz)

200

300

400

500

600

PLLFLTR PIN VOLTAGE (V)

3728 F05

2.5

2.0

1.5

1.0

0.5

LTC3728L/LTC3728LX

3728lxfa

The inductor value also has secondary effects. The transi-
tion to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by R

SENSE

. Lower

inductor values (higher

) will cause this to occur at

lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.

Inductor Core Selection

Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron
cores, forcing the use of more expensive ferrite, molyper-
malloy, or Kool M

cores. Actual core loss is indepen-

dent of core size for a fixed inductor value, but it is very
dependent on inductance selected. As inductance in-
creases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.

Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates "hard," which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!

Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool M

. Toroids are very space efficient,

especially when you can use several layers of wire. Be-
cause they generally lack a bobbin, mounting is more
difficult. However, designs for surface mount are available
that do not increase the height significantly.

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for each
controller in the LTC3728L/LTC3728LX: One N-channel
MOSFET for the top (main) switch, and one N-channel
MOSFET for the bottom (synchronous) switch.

The peak-to-peak drive levels are set by the INTV

voltage. This voltage is typically 5V during start-up (see
EXTV

Pin Connection). Consequently, logic-level

threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(V

< 5V); then, sub-logic level threshold MOSFETs

GS(TH)

< 3V) should be used. Pay close attention to the

DSS

specification for the MOSFETs as well; most of the

logic level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the "ON"
resistance R

DS(ON)

, Miller capacitance C

MILLER

, input volt-

age and maximum output current. Miller capacitance,
C

MILLER

, can be approximated from the gate charge curve

usually provided on the MOSFET manufacturers' data
sheet. C

MILLER

is equal to the increase in gate charge along

the horizontal axis while the curve is approximately flat
divided by the specified change in V

. This result is then

multiplied by the ratio of the application applied V

to the

Gate charge curve specified V

. When the IC is operating

in continuous mode the duty cycles for the top and bottom
MOSFETs are given by:

Main Switch Duty Cycle

OUT

Synchronous Switch Duty Cycle

OUT

The MOSFET power dissipations at maximum output
current are given by:

MAIN

OUT

MAX

DS ON

MAX

MILLER

INTVCC

THMIN

( )

( )(

)

( )

(

)

SYNC

OUT

MAX

DS ON

( )

(

)

Kool M

is a registered trademark of Magnetics, Inc.

APPLICATIO S I FOR ATIO

LTC3728L/LTC3728LX

3728lxfa

where

is the temperature dependency of R

DS(ON)

and

(approximately 4

) is the effective driver resistance

at the MOSFET's Miller threshold voltage. V

THMIN

is the

typical MOSFET minimum threshold voltage.

Both MOSFETs have I

R losses while the topside N-channel

equation includes an additional term for transition losses,
which are highest at high input voltages. For V

< 20V the

high current efficiency generally improves with larger
MOSFETs, while for V

> 20V the transition losses rapidly

increase to the point that the use of a higher R

DS(ON)

device

with lower C

MILLER

actually provides higher efficiency. The

synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.

The term (1+

) is generally given for a MOSFET in the form

of a normalized R

DS(ON)

vs Temperature curve, but

= 0.005/

C can be used as an approximation for low

voltage MOSFETs.

The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the dead-
time and requiring a reverse recovery period that could
cost as much as 3% in efficiency at high V

. A 1A to 3A

Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance.

and C

OUT

Selection

The selection of C

is simplified by the multiphase archi-

tecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
when only one controller is operating. The controller with
the highest (V

OUT

)(I

OUT

) product needs to be used in the

formula below to determine the maximum RMS current
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease
the input RMS ripple current from this maximum value
(see Figure 4). The out-of-phase technique typically re-
duces the input capacitor's RMS ripple current by a factor

of 30% to 70% when compared to a single phase power
supply solution.

The type of input capacitor, value and ESR rating have
efficiency effects that need to be considered in the selec-
tion process. The capacitance value chosen should be
sufficient to store adequate charge to keep high peak
battery currents down. 20

F to 40

F is usually sufficient

for a 25W output supply operating at 200kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery efficiency. All of the power (RMS
ripple current · ESR) not only heats up the capacitor but
wastes power from the battery.

Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used as
input capacitors, but each has drawbacks: ceramic voltage
coefficients are very high and may have audible piezoelec-
tric effects; tantalums need to be surge-rated; OS-CONs
suffer from higher inductance, larger case size and limited
surface-mount applicability; electrolytics' higher ESR and
dryout possibility require several to be used. Multiphase
systems allow the lowest amount of capacitance overall.
As little as one 22

F or two to three 10

F ceramic capaci-

tors are an ideal choice in a 20W to 35W power supply due
to their extremely low ESR. Even though the capacitance
at 20V is substantially below their rating at zero-bias, very
low ESR loss makes ceramics an ideal candidate for
highest efficiency battery operated systems. Also con-
sider parallel ceramic and high quality electrolytic capaci-
tors as an effective means of achieving ESR and bulk
capacitance goals.

In continuous mode, the source current of the top N-chan-
nel MOSFET is a square wave of duty cycle V

OUT

. To

prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current of one channel must
be used. The maximum RMS capacitor current is given by:

quiredI

RMS

MAX

OUT

(

)

[

]

1 2

This formula has a maximum at V

= 2V

OUT

, where

RMS

= I

OUT

/2. This simple worst case condition is com-

monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer's

APPLICATIO S I FOR ATIO

LTC3728L/LTC3728LX

3728lxfa

ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.

The benefit of the LTC3728L/LTC3728LX multiphase clock-
ing can be calculated by using the equation above for the
higher power controller and then calculating the loss that
would have resulted if both controller channels switched
on at the same time. The total RMS power lost is lower
when both controllers are operating due to the interleaving
of current pulses through the input capacitor's ESR. This
is why the input capacitor's requirement calculated above
for the worst-case controller is adequate for the dual
controller design. Remember that input protection fuse
resistance, battery resistance and PC board trace resis-
tance losses are also reduced due to the reduced peak
currents in a multiphase system.

The overall benefit of a

multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing. The drains of the two top MOSFETS
should be placed within 1cm of each other and share a
common C

(s). Separating the drains and C

may pro-

duce undesirable voltage and current resonances at V

The selection of C

OUT

is driven by the required effective

series resistance (ESR). Typically once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The output ripple (

OUT

) is determined by:

I ESR

OUT

Where f = operating frequency, C

OUT

= output capacitance,

and

= ripple current in the inductor. The output ripple

is highest at maximum input voltage since

increases

with input voltage. With

= 0.3I

OUT(MAX)

the output

ripple will typically be less than 50mV at the maximum V

assuming:

OUT

Recommended ESR < 2 R

SENSE

and C

OUT

> 1/(8fR

SENSE

)

The first condition relates to the ripple current into the
ESR of the output capacitance while the second term
guarantees that the output capacitance does not signifi-
cantly discharge during the operating frequency period
due to ripple current. The choice of using smaller output
capacitance increases the ripple voltage due to the dis-
charging term but can be compensated for by using
capacitors of very low ESR to maintain the ripple voltage
at or below 50mV. The I

pin OPTI-LOOP compensation

components can be optimized to provide stable, high
performance transient response regardless of the output
capacitors selected.

Manufacturers such as Nichicon, United Chemi-Con and
Sanyo can be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.

In surface mount applications multiple capacitors may
need to be used in parallel to meet ESR, RMS current
handling and load step requirements. Aluminum electro-
lytic, dry tantalum and special polymer capacitors are
available in surface mount packages. Special polymer
surface mount capacitors offer very low ESR but have
lower storage capacity per unit volume than other capaci-
tor types. These capacitors offer a very cost-effective
output capacitor solution and are an ideal choice when
combined with a controller having high loop bandwidth.
Tantalum capacitors offer the highest capacitance density
and are often used as output capacitors for switching
regulators having controlled soft-start. Several excellent
surge-tested choices are the AVX TPS, AVX TPSV or the
KEMET T510 series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. Aluminum
electrolytic capacitors can be used in cost-driven applica-
tions providing that consideration is given to ripple cur-
rent ratings, temperature and long term reliability. A
typical application will require several to many aluminum
electrolytic capacitors in parallel. A combination of the
above mentioned capacitors will often result in maximiz-
ing performance and minimizing overall cost. Other ca-
pacitor types include Nichicon PL series, Panasonic SP,

APPLICATIO S I FOR ATIO

LTC3728L/LTC3728LX

3728lxfa

NEC Neocap, Cornell Dubilier ESRE and Sprague 595D
series. Consult manufacturers for other specific recom-
mendations.

INTV

Regulator

An internal P-channel low dropout regulator produces 5V
at the INTV

pin from the V

supply pin. INTV

powers

the drivers and internal circuitry within the IC. The INTV

pin regulator can supply a peak current of 50mA and must
be bypassed to ground with a minimum of 4.7

F tanta-

lum, 10

F special polymer, or low ESR type electrolytic

capacitor. A 1

F ceramic capacitor placed directly adja-

cent to the INTV

and PGND IC pins is highly recom-

mended. Good bypassing is necessary to supply the high
transient currents required by the MOSFET gate drivers
and to prevent interaction between channels.

Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the IC to be ex-
ceeded. The system supply current is normally dominated
by the gate charge current. Additional external loading of
the INTV

and 3.3V linear regulators also needs to be

taken into account for the power dissipation calculations.
The total INTV

current can be supplied by either the 5V

internal linear regulator or by the EXTV

input pin. When

the voltage applied to the EXTV

pin is less than 4.7V, all

of the INTV

current is supplied by the internal 5V linear

regulator. Power dissipation for the IC in this case is
highest: (V

)(I

INTVCC

), and overall efficiency is lowered.

The gate charge current is dependent on operating fre-
quency as discussed in the Efficiency Considerations
section. The junction temperature can be estimated by
using the equations given in Note 2 of the Electrical
Characteristics. For example, the IC V

current is ther-

mally limited to less than 67mA from a 24V supply when
not using the EXTV

pin as follows:

= 70

C + (67mA)(24V)(34

C/W) = 125

Use of the EXTV

input pin reduces the junction tempera-

ture to:

= 70

C + (67mA)(5V)(34

C/W) = 81

The absolute maximum rating for the INTV

Pin is 40mA.

Dissipation should be calculated to also include any added

current drawn from the internal 3.3V linear regulator. To
prevent maximum junction temperature from being
exceeded, the input supply current must be checked
operating in continuous mode at maximum V

EXTV

Connection

The IC contains an internal P-channel MOSFET switch
connected between the EXTV

and INTV

pins. When

the voltage applied to EXTV

rises above

4.7V, the inter-

nal regulator is turned off and the switch closes, connect-
ing the EXTV

pin to the INTV

pin thereby supplying

internal power. The switch remains closed as long as the
voltage applied to EXTV

remains above 4.5V. This

allows the MOSFET driver and control power to be derived
from the output during normal operation (4.7V < V

OUT

7V) and from the internal regulator when the output is out
of regulation (start-up, short-circuit). If more
current is required through the EXTV

switch than is

specified, an external Schottky diode can be added be-
tween the EXTV

and INTV

pins. Do not apply greater

than 7V to the EXTV

pin and ensure that EXTV

< V

Significant efficiency gains can be realized by powering
INTV

from the output, since the V

current resulting

from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 5V regulators this
supply means connecting the EXTV

pin directly to V

OUT

However, for 3.3V and other lower voltage regulators,
additional circuitry is required to derive INTV

power

from the output.

The following list summarizes the four possible connec-
tions for EXTV

CC:

1. EXTV

Left Open (or Grounded). This will cause INTV

to be powered from the internal 5V regulator resulting in
an efficiency penalty of up to 10% at high input voltages.

2. EXTV

Connected directly to V

OUT

. This is the normal

connection for a 5V regulator and provides the highest
efficiency.

3. EXTV

Connected to an External supply. If an external

supply is available in the 5V to 7V range, it may be used to
power EXTV

providing it is compatible with the MOSFET

gate drive requirements.

APPLICATIO S I FOR ATIO

LTC3728L/LTC3728LX

3728lxfa

4. EXTV

Connected to an Output-Derived Boost Net-

work. For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTV

to an

output-derived voltage that has been boosted to greater
than 4.7V. This can be done with either the inductive boost
winding as shown in Figure 6a or the capacitive charge
pump shown in Figure 6b. The charge pump has the
advantage of simple magnetics.

Topside MOSFET Driver Supply (C

, D

)

External bootstrap capacitors C

connected to the BOOST

pins supply the gate drive voltages for the topside MOSFETs.
Capacitor C

in the functional diagram is charged though

external diode D

from INTV

when the SW pin is low.

When one of the topside MOSFETs is to be turned on, the
driver places the C

voltage across the gate-source of the

desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
V

and the BOOST pin follows. With the topside MOSFET

on, the boost voltage is above the input supply: V

BOOST

+ V

INTVCC

. The value of the boost capacitor C

needs

to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the exter-
nal Schottky diode must be greater than V

IN(MAX)

. When

adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and the
input current decreases, then the efficiency has improved.
If there is no change in input current, then there is no
change in efficiency.

Figure 6a. Secondary Output Loop & EXTV

Connection

Figure 6b. Capacitive Charge Pump for EXTV

Output Voltage

The output voltages are each set by an external feedback
resistive divider carefully placed across the output capaci-
tor. The resultant feedback signal is compared with the
internal precision 0.800V voltage reference by the error
amplifier. The output voltage is given by the equation:

OUT

0 8

where R1 and R2 are defined in Figure 2.

SENSE

/SENSE

Pins

The common mode input range of the current comparator
sense pins is from 0V to (1.1)INTV

. Continuous linear

operation is guaranteed throughout this range allowing
output voltage setting from 0.8V to 7.7V, depending upon
the voltage applied to EXTV

. A differential NPN input

stage is biased with internal resistors from an internal
2.4V source as shown in the Functional Diagram. This
requires that current either be sourced or sunk from the
SENSE pins depending on the output voltage. If the output
voltage is below 2.4V current will flow out of both SENSE
pins to the main output. The output can be easily preloaded
by the V

OUT

resistive divider to compensate for the current

comparator's negative input bias current. The maximum
current flowing out of each pair of SENSE pins is:

SENSE

+ I

SENSE

= (2.4V V

OUT

)/24k

EXTV

FCB

SGND

TG1

BG1

PGND

LTC3728L/

LTC3728LX

SENSE

OUT

SEC

OUT

3728 F06a

N-CH

1:N

OPTIONAL EXTV

CONNECTION
5V < V

SEC

< 7V

BAT 85

EXTV

TG1

BG1

PGND

LTC3728L/

LTC3728LX

SENSE

OUT

VN2222LL

OUT

3728 F06b

N-CH

BAT85

0.22

APPLICATIO S I FOR ATIO

LTC3728L/LTC3728LX

3728lxfa

Since V

OSENSE

is servoed to the 0.8V reference voltage, we

can choose R1 in Figure 2 to have a maximum value to
absorb this current.

MAX

OUT

0 8

2 4

(

)

for V

OUT

< 2.4V

Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32k. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb the
sense currents; however, R1 is still bounded by the
V

OSENSE

feedback current.

Soft-Start/Run Function

The RUN/SS1 and RUN/SS2 pins are multipurpose pins
that provide a soft-start function and a means to shut
down the LTC3728L/LTC3728LX. Soft-start reduces the
input power source's surge currents by gradually increas-
ing the controller's current limit (proportional to V

ITH

This pin can also be used for power supply sequencing.

An internal 1.2

A current source charges up the C

capacitor

When the voltage on RUN/SS1 (RUN/SS2)

reaches 1.5V, the particular controller is permitted to start
operating. As the voltage on RUN/SS increases from 1.5V
to 3.0V, the internal current limit is increased from 25mV/
R

SENSE

to 75mV/R

SENSE

. The output current limit ramps

up slowly, taking an additional 1.25s/

F to reach full

current. The output current thus ramps up slowly, reduc-
ing the starting surge current required from the input
power supply. If RUN/SS has been pulled all the way to
ground there is a delay before starting of approximately:

F C

DELAY

(

)

1 5

1 2

1 25

F C

IRAMP

(

)

1 5

1 2

1 25

By pulling both RUN/SS pins below 1V, the IC is put into
low current shutdown (I

= 20

A). The RUN/SS pins can

be driven directly from logic as shown in Figure 7. Diode
D1 in Figure 7 reduces the start delay but allows C

ramp up slowly providing the soft-start function. Each
RUN/SS pin has an internal 6V zener clamp (See Func-
tional Diagram).

Fault Conditions: Overcurrent Latchoff

The RUN/SS pins also provide the ability to latch off the
controller(s) when an overcurrent condition is detected.
The RUN/SS capacitor, C

, is used initially to turn on and

limit the inrush current. After the controller has been
started and been given adequate time to charge up the
output capacitor and provide full load current, the RUN/SS
capacitor is used for a short-circuit timer. If the regulator's
output voltage falls to less than 70% of its nominal value
after C

reaches 4.1V, C

begins discharging on the

assumption that the output is in an overcurrent condition.
If the condition lasts for a long enough period as deter-
mined by the size of the C

and the specified discharge

current, the controller will be shut down until the RUN/SS
pin voltage is recycled. If the overload occurs during start-
up, the time can be approximated by:

LO1

(4.1 1.5 + 4.1 3.5)]/(1.2

= 2.7 · 10

)

If the overload occurs after start-up the voltage on C

will

begin discharging from the zener clamp voltage:

LO2

(6 3.5)]/(1.2

A) = 2.1 · 10

)

This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin as shown
in Figure 7. This resistance shortens the soft-start period
and prevents the discharge of the RUN/SS capacitor
during an over current condition. Tying this pull-up resis-
tor to V

, as in Figure 7a, defeats overcurrent latchoff.

Figure 7. RUN/SS Pin Interfacing

3.3V OR 5V

RUN/SS

INTV

RUN/SS

3728 F07

(a)

(b)

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

APPLICATIO S I FOR ATIO

LTC3728L/LTC3728LX

3728lxfa

Diode-connecting this pull-up resistor to INTV

, as in

Figure 7b, eliminates any extra supply current during
controller shutdown while eliminating the INTV

from preventing controller start-up.

Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem
with noise pickup or poor layout causing the protection
circuit to latch off. Defeating this feature will easily allow
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. After the design is complete, a decision can be
made whether to enable the latchoff feature.

The value of the soft-start capacitor C

may need to be

scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:

> (C

OUT

)(V

OUT

) (10

) (R

SENSE

)

The minimum recommended soft-start capacitor of
C

= 0.1

F will be sufficient for most applications.

Fault Conditions: Current Limit and Current Foldback

The current comparators have a maximum sense voltage
of 75mV resulting in a maximum MOSFET current of
75mV/R

SENSE

. The maximum value of current limit gener-

ally occurs with the largest V

at the highest ambient

temperature, conditions that cause the highest power
dissipation in the top MOSFET.

Each controller includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch described above is overridden. If the
output falls below 70% of its nominal output level, then the
maximum sense voltage is progressively lowered from
75mV to 25mV. Under short-circuit conditions with very
low duty cycles, the controller will begin cycle skipping in
order to limit the short-circuit current. In this situation the
bottom MOSFET will be dissipating most of the power but
less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time t

ON(MIN)

each controller (typically 100ns), the input voltage and
inductor value:

L(SC)

= t

ON(MIN)

/L)

The resulting short-circuit current is:

SENSE

L SC

(

)

Fault Conditions: Overvoltage Protection (Crowbar)

The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow, that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the
controller is operating.

A comparator monitors the output for overvoltage condi-
tions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage.
When this condition is sensed, the top MOSFET is turned
off and the bottom MOSFET is turned on until the overvolt-
age condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
therefore allow a switching regulator system having a poor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
as the OV condition persists; if V

OUT

returns to a safe level,

normal operation automatically resumes. A shorted top
MOSFET will result in a high current condition which will
open the system fuse. The switching regulator will regu-
late properly with a leaky top MOSFET by altering the duty
cycle to accommodate the leakage.

Phase-Locked Loop and Frequency Synchronization

The IC has a phase-locked loop comprised of an internal
voltage controlled oscillator and phase detector. This
allows the top MOSFET turn-on to be locked to the rising
edge of an external source. The frequency range of the
voltage controlled oscillator is

50% around the center

frequency f

. A voltage applied to the PLLFLTR pin of 1.2V

corresponds to a frequency of approximately 400kHz. The
nominal operating frequency range of the IC is 260kHz to
550kHz.

APPLICATIO S I FOR ATIO

LTC3728L/LTC3728LX

3728lxfa

The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range,

, is equal to the capture range,

0.5 f

(260kHz-550kHz)

The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 7.

If the external frequency (f

PLLIN

) is greater than the oscil-

lator frequency f

0SC

, current is sourced continuously,

pulling up the PLLFLTR pin. When the external frequency
is less than f

0SC

, current is sunk continuously, pulling

down the PLLFLTR pin. If the external and internal fre-
quencies are the same but exhibit a phase difference, the
current sources turn on for an amount of time correspond-
ing to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor C

holds the voltage. The IC's

PLLIN pin must be driven from a low impedance source
such as a logic gate located close to the pin. When using
multiple ICs for a phase-locked system, the PLLFLTR pin
of the master oscillator should be biased at a voltage that
will guarantee the slave oscillator(s) ability to lock onto the
master's frequency. A DC voltage of 0.7V to 1.7V applied
to the master oscillator's PLLFLTR pin is recommended in
order to meet this requirement. The resultant operating
frequency can range from 300kHz to 500kHz.

The loop filter components (C

, R

) smooth out the

current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C

and R

determine how fast the loop

acquires lock. Typically R

=10k

and C

is 0.01

F to

0.1

Minimum On-Time Considerations

Minimum on-time t

ON(MIN)

is the smallest time duration

that each controller is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that

V f

ON MIN

OUT

(

)

( )

If the duty cycle falls below what can be accommodated by
the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.

The minimum on-time for each controller is approximately
100ns. However, as the peak sense voltage decreases the
minimum on-time gradually increases up to about 150ns.
This is of particular concern in forced continuous applica-
tions with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with
correspondingly larger current and voltage ripple.

FCB Pin Operation

The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced on
both controllers when the FCB pin drops below 0.8V.
During continuous mode, current flows continuously in
the transformer primary. The secondary winding(s) draw
current only when the bottom, synchronous switch is on.
When primary load currents are low and/or the V

OUT

ratio is low, the synchronous switch may not be on for a
sufficient amount of time to transfer power from the
output capacitor to the secondary load. Forced continuous
operation will support secondary windings providing there
is sufficient synchronous switch duty factor. Thus, the
FCB input pin removes the requirement that power must
be drawn from the inductor primary in order to extract

APPLICATIO S I FOR ATIO

LTC3728L/LTC3728LX

3728lxfa

loop is reduced depending upon the maximum load step
specifications. Voltage positioning can easily be added to
either or both controllers by loading the I

pin with a

resistive divider having a Thevenin equivalent voltage
source equal to the midpoint operating voltage range of
the error amplifier, or 1.2V (see Figure 8).

The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
maximum output voltage deviation can theoretically be
reduced to half or alternatively the amount of output
capacitance can be reduced for a particular application. A
complete explanation is included in Design Solutions 10.
(See www.linear-tech.com)

power from the auxiliary windings. With the loop in
continuous mode, the auxiliary outputs may nominally be
loaded without regard to the primary output load.

The secondary output voltage V

SEC

is normally set as

shown in Figure 6a by the turns ratio N of the transformer:

SEC

(N + 1) V

OUT

However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then V

SEC

will droop. An external resistive divider from

SEC

to the FCB pin sets a minimum voltage V

SEC(MIN)

SEC MIN

(

)

0 8

where R5 and R6 are shown in Figure 2.

If V

SEC

drops below this level, the FCB voltage forces

temporary continuous switching operation until V

SEC

again above its minimum.

In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.18

internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.

The following table summarizes the possible states avail-
able on the FCB pin:

Table 1

FCB Pin

Condition

0V to 0.75V

Forced Continuous Both Controllers
(Current Reversal Allowed--
Burst Inhibited)

0.85V < V

FCB

< 4.3V

Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed

Feedback Resistors

Regulating a Secondary Winding

>4.8V

Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed

No Minimum Peak Current

Voltage Positioning

Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control

APPLICATIO S I FOR ATIO

INTV

3728 F08

LTC3728L/

LTC3728LX

Figure 8. Active Voltage Positioning
Applied to the LTC3728L/LTC3728LX

Efficiency Considerations

The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:

%Efficiency = 100% (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage
of input power.

Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3728L/LTC3728LX circuits: 1) IC V

current

(including loading on the 3.3V internal regulator), 2)
INTV

regulator current, 3) I

R losses, 4) Topside MOSFET

transition losses.

1. The V

current has two components: the first is the DC

supply current given in the Electrical Characteristics table,

LTC3728L/LTC3728LX

3728lxfa

4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:

Transition Loss = V

( )

(

)( )

V V

MAX

MILLER

Other "hidden" losses such as copper trace and internal
battery resistances can account for an additional 5% to 10%
efficiency degradation in portable systems. It is very impor-
tant to include these "system" level losses during the de-
sign phase. The internal battery and fuse resistance losses
can be minimized by making sure that C

has adequate

charge storage and very low ESR at the switching frequency.
A 25W supply will typically require a minimum of 20

F to

F of capacitance having a maximum of 20m

to 50m

of ESR. The LTC3728L 2-phase architecture typically halves
this input capacitance requirement over competing solu-
tions. Other losses including Schottky conduction losses
during dead-time and inductor core losses generally ac-
count for less than 2% total additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V

OUT

shifts by an

amount equal to

LOAD

(ESR), where ESR is the effective

series resistance of C

OUT

LOAD

also begins to charge or

discharge C

OUT

generating the feedback error signal that

forces the regulator to adapt to the current change and
return V

OUT

to its steady-state value. During this recovery

time V

OUT

can be monitored for excessive overshoot or

ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values.

The availability of the I

pin not only allows

optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point

which excludes MOSFET driver and control currents; the
second is the current drawn from the 3.3V linear regulator
output. V

current typically results in a small (<0.1%) loss.

2. INTV

current is the sum of the MOSFET driver and

control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTV

ground. The resulting dQ/dt is a current out of INTV

that

is typically much larger than the control circuit current. In
continuous mode, I

GATECHG

=f(Q

), where Q

and Q

are the gate charges of the topside and bottom side
MOSFETs.

Supplying INTV

power through the EXTV

switch input

from an output-derived source will scale the V

current

required for the driver and control circuits by a factor of
(Duty Cycle)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTV

current results in approxi-

mately 2.5mA of V

current. This reduces the mid-current

loss from 10% or more (if the driver was powered directly
from V

) to only a few percent.

3. I

R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R

SENSE

but is "chopped" between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same R

DS(ON)

, then the resistance of one

MOSFET can simply be summed with the resistances of L,
R

SENSE

and ESR to obtain I

R losses. For example, if each

DS(ON)

= 30m

, R

= 50m

, R

SENSE

= 10m

and R

ESR

= 40m

(sum of both input and output capacitance

losses), then the total resistance is 130m

. This results in

losses ranging from 3% to 13% as the output current
increases from 1A to 5A for a 5V output, or a 4% to 20%
loss for a 3.3V output. Efficiency varies as the inverse
square of V

OUT

for the same external components and

output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!

APPLICATIO S I FOR ATIO

LTC3728L/LTC3728LX

3728lxfa

truly reflects the closed loop response. Assuming a pre-
dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I

external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.

The I

series R

-C

filter sets the dominant pole-zero

loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80% of
full-load current having a rise time of 1

s to 10

s will

produce output voltage and I

pin waveforms that will

give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This is
why it is better to look at the I

pin signal which is in the

feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing R

and the bandwidth of the loop will be

increased by decreasing C

. If R

is increased by the same

factor that C

is decreased, the zero frequency will be kept

the same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability of
the closed-loop system and will demonstrate the actual
overall supply performance.

A second, more severe transient is caused by switching in
loads with large (>1

F) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel
with C

OUT

, causing a rapid drop in V

OUT

. No regulator can

alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C

LOAD

to C

OUT

is greater than1:50, the switch rise time

should be controlled so that the load rise time is limited to
approximately 25 · C

LOAD

. Thus a 10

F capacitor would

require a 250

s rise time, limiting the charging current to

about 200mA.

Automotive Considerations: Plugging into the
Cigarette Lighter

As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging into
the supply from hell. The main power line in an automobile
is the source of a number of nasty potential transients,
including load-dump, reverse-battery, and double-bat-
tery.

Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.

The network shown in Figure 9 is the most straightforward
approach to protect a DC/DC converter from the ravages
of an automotive power line. The series diode prevents
current from flowing during reverse-battery, while the
transient suppressor clamps the input voltage during
load-dump. Note that the transient suppressor should not
conduct during double-battery operation, but must still
clamp the input voltage below breakdown of the converter.
Although the LTC3728L/LTC3728LX have a maximum
input voltage of 30V, most applications will also be limited
to 30V by the MOSFET BVD

APPLICATIO S I FOR ATIO

Figure 9. Automotive Application Protection

3728 F09

LTC3728L/

LTC3728LX

TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A

50A I

RATING

12V

LTC3728L/LTC3728LX

3728lxfa

Design Example

As a design example for one channel, assume V

12V(nominal), V

= 22V(max), V

OUT

= 1.8V, I

MAX

= 5A,

and f = 300kHz.

The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLFLTR pin
to a resistive divider from the INTV

pin, generating 0.7V

for 300kHz operation. The minimum inductance for 30%
ripple current is:

f L

OUT

( )( )

A 4.7

H inductor will produce 23% ripple current and a

3.3

H will result in 33%. The peak inductor current will be

the maximum DC value plus one half the ripple current, or
5.84A, for the 3.3

H value. Increasing the ripple current

will also help ensure that the minimum on-time of 100ns
is not violated. The minimum on-time occurs at maximum
V

kHz

ON MIN

OUT

IN MAX

(

)

(

)

(

)

1 8

22 300

273

The R

SENSE

resistor value can be calculated by using the

maximum current sense voltage specification with some
accommodation for tolerances:

SENSE

5 84

0 01

Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pin's specified input
current.

V V

MAX

OUT

0 8

2 4

0 8

2 4

1 8

(

)

Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.

The power dissipation on the top side MOSFET can be
easily estimated. Choosing a Fairchild FDS6982S dual
MOSFET results in: R

DS(ON)

= 0.035

/0.022

, C

MILLER

215pF. At maximum input voltage with T(estimated) =
50

kHz

MAIN

( )

[

]

(

)

( )

( )( )

(

)

1 8

0 005 50

0 035

215

5 2 3

2 3

300

332

( .

)(

) ·

A short-circuit to ground will result in a folded back current
of:

0 01

120

3 3

2 1

(

)

with a typical value of R

DS(ON)

and

= (0.005/

C)(20) = 0.1.

The resulting power dissipated in the bottom MOSFET is:

SYNC

( ) (

)

(

)

1 8

2 1

1 125 0 022

100

which is less than under full-load conditions.

is chosen for an RMS current rating of at least 3A at

temperature assuming only this channel is on. C

OUT

chosen with an ESR of 0.02

for low output ripple. The

output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:

ORIPPLE

= R

ESR

(

) = 0.02

(1.67A) = 33mV

APPLICATIO S I FOR ATIO

LTC3728L/LTC3728LX

3728lxfa

PC Board Layout Checklist

When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. These items are also illustrated graphically in the
layout diagram of Figure 10. The Figure 11 illustrates the
current waveforms present in the various branches of the
2-phase synchronous regulators operating in the continu-
ous mode. Check the following in your layout:

1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at C

? Do not attempt to split the input decoupling for the

two channels as it can cause a large resonant loop.

2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
C

INTVCC

must return to the combined C

OUT

() terminals.

The path formed by the top N-channel MOSFET, Schottky
diode and the C

capacitor should have short leads and

PC trace lengths. The output capacitor () terminals
should be connected as close as possible to the ()
terminals of the input capacitor by placing the capacitors
next to each other and away from the Schottky loop
described above.

3. Do the LTC3728L/LTC3728LX V

OSENSE

pins' resistive

dividers connect to the (+) terminals of C

OUT

? The resistive

divider must be connected between the (+) terminal of

APPLICATIO S I FOR ATIO

Figure 10. LTC3728L/LTC3728LX Recommended Printed Circuit Layout Diagram

PGOOD

PULL-UP

(<7V)

INTVCC

CERAMIC

VIN

INTV

3.3V

RUN/SS1

SENSE1

OSENSE1

PLLFLTR

PLLIN

FCB

TH1

SGND

3.3V

OUT

TH2

OSENSE2

SENSE2

PGOOD

TG1

SW1

BOOST1

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

LTC3728L/LTC3728LX

OUT1

GND

OUT2

3728 F10

OUT2

SENSE

CERAMIC

LTC3728L/LTC3728LX

3728lxfa

OUT

and signal ground. The R2 and R4 connections

should not be along the high current input feeds from the
input capacitor(s).

4. Are the SENSE

and SENSE

leads routed together

with minimum PC trace spacing? The filter capacitor
between SENSE

and SENSE

should be as close as

possible to the IC. Ensure accurate current sensing with
Kelvin connections at the SENSE resistor.

5. Is the INTV

decoupling capacitor connected close to

the IC, between

the INTV

and the power ground pins?

This capacitor carries the MOSFET drivers current peaks.

An additional 1

F ceramic capacitor placed immediately

next to the INTV

and PGND pins can help improve noise

performance substantially.

6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposites channel's voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the "output side"
of the LTC3728L/LTC3728LX and occupy minimum PC
trace area.

APPLICATIO S I FOR ATIO

Figure 11. Branch Current Waveforms

SW1

SENSE1

OUT1

CERAMIC

BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.

SW2

3728 F11

SENSE2

OUT2

CERAMIC

LTC3728L/LTC3728LX

3728lxfa

APPLICATIO S I FOR ATIO

7. Use a modified "star ground" technique: a low imped-
ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV

decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.

PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the
operating voltage and current range expected in the appli-
cation. The frequency of operation should be maintained
over the input voltage range down to dropout and until the
output load drops below the low current operation thresh-
old--typically 10% to 20% of the maximum designed
current level in Burst Mode operation.

The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage
sensing inputs or inadequate loop compensation. Over-
compensation of the loop can be used to tame a poor PC
layout if regulator bandwidth optimization is not required.
Only after each controller is checked for its individual
performance should both controllers be turned on at the
same time. A particularly difficult region of operation is
when one controller channel is nearing its current com-
parator trip point when the other channel is turning on its
top MOSFET. This occurs around 50% duty cycle on either
channel due to the phasing of the internal clocks and may
cause minor duty cycle jitter.

Short-circuit testing can be performed to verify proper
overcurrent latchoff, or 5

A can be provided to the RUN/

SS pin(s) by resistors from V

to prevent the short-circuit

latchoff from occurring.

Reduce V

from its nominal level to verify operation of the

regulator in dropout. Check the operation of the under-
voltage lockout circuit by further lowering V

while moni-

toring the outputs to verify operation.

Investigate whether any problems exist only at higher
output currents or only at higher input voltages. If prob-
lems coincide with high input voltages and low output
currents, look for capacitive coupling between the BOOST,
SW, TG, and possibly BG connections and the sensitive
voltage and current pins. The capacitor placed across the
current sensing pins needs to be placed immediately
adjacent to the pins of the IC. This capacitor helps to
minimize the effects of differential noise injection due to
high frequency capacitive coupling. If problems are en-
countered with high current output loading at lower input
voltages, look for inductive coupling between C

, Schottky

and the top MOSFET components to the sensitive current
and voltage sensing traces. In addition, investigate com-
mon ground path voltage pickup between these compo-
nents and the SGND pin of the IC.

An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still be
maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor--don't worry, the regulator
will still maintain control of the output voltage.

LTC3728L/LTC3728LX

3728lxfa

Figure 12. LTC3728L/LTC3728LX High Efficiency Low Noise 5V/3A, 3.3V/5A, 12V/120mA Regulator

0.1

4.7

50V

MBRS1100T3

10V

CMDSH-3TR

0.1

0.01

0.015

3.3V

0.1

20k

105k, 1%

33pF

15k

33pF

15k

1000pF

0.1

20k

63.4k

RUN/SS1

SENSE1

OSENSE1

PLLFLTR

PLLIN

FCB

TH1

SGND

3.3V

OUT

TH2

OSENSE2

SENSE2

PGOOD

TG1

SW1

BOOST1

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

LTC3728L/LTC3728LX

T1, 1:1.8

6.3

150

F, 6.3V

PANASONIC SP

25V

180

F, 4V

PANASONIC SP

GND

ON/OFF

OUT2

3.3V
5A; 6A PEAK

OUT3

12V
120mA

25V

OUT1

5V
3A; 4A PEAK

7V TO
28V

3728 F12

: 7V TO 28V

OUT

: 5V, 3A/3.3V, 6A/12V, 150mA

SWITCHING FREQUENCY = 250kHz
MI, M2: FDS6982S OR VISHAY Si4810DY
L1: SUMIDA CEP123-6R3MC
T1: 10

H 1:1.8 -- DALE LPE6562-A262 GAPPED E-CORE OR BH ELECTRONICS #501-0657 GAPPED TOROID

LT1121

220k

100k

PGOOD

100k

PULL-UP

(<7V)

59k

180pF

TYPICAL APPLICATIO S

LTC3728L/LTC3728LX

3728lxfa

TYPICAL APPLICATIO S

Figure 13. LTC3728L/LTC3728LX 5V/4A, 3.3V/5A Regulator with External Frequency Synchronization

0.1

4.7

F, 10V

50V

PIN 4

0.1

0.008

F 50V

SYNC

3.3V

0.1

10k

105k

100pF

8.06k

100pF

4.75k

1000pF

1500pF

0.01

1000pF

0.1

20k

63.4k

20k

RUN/SS1

SENSE1

OSENSE1

PLLFLTR

PLLIN

FCB

TH1

SGND

3.3V

OUT

TH2

OSENSE2

SENSE2

PGOOD

TG1

SW1

BOOST1

BG1

EXTV

INTV

PGND

BG2

BOOST2

SW2

TG2

RUN/SS2

LTC3728L/LTC3728LX

4.3

150

F, 6.3V

180

F, 4V

GND

OUT2

3.3V/5A

OUT1

5V/4A

7V TO
28V

3728 F13

: 7V TO 28V

OUT

: 5V, 4A/3.3V, 5A

SWITCHING FREQUENCY = 250kHz TO 550kHz
M1, M2: FDS6982S OR VISHAY Si4810DY

L1, L2: SUMIDA CDEP105-4R3MC-88
OUTPUT CAPACITORS: PANASONIC SP SERIES

180pF

0.1

CMDSH-3TR

PGOOD

PULL-UP

(<7V)

F 50V

LTC3728L/LTC3728LX

3728lxfa

PACKAGE DESCRIPTIO

UH Package

32-Lead Plastic QFN (5mm

5mm)

(Reference LTC DWG # 05-08-1693)

(For purposes of clarity, drawings are not to scale)

5.00

0.10

(4 SIDES)

NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED

PIN 1
TOP MARK

0.40

0.10

BOTTOM VIEW--EXPOSED PAD

3.45

0.10

(4-SIDES)

0.75

0.05

R = 0.115

TYP

0.23

0.05

(UH) QFN 0102

0.50 BSC

0.200 REF

0.00 0.05

0.57

0.05

3.45

0.05

(4 SIDES)

4.20

0.05

5.35

0.05

0.23

0.05

PACKAGE

OUTLINE

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.386 .393*

(9.804 9.982)

GN28 (SSOP) 0502

9 10 11 12

.229 .244

(5.817 6.198)

.150 .157**
(3.810 3.988)

19 18 17

13 14

1615

.016 .050

(0.406 1.270)

.015

.004

(0.38

0.10)

TYP

.0075 .0098

(0.191 0.249)

.053 .069

(1.351 1.748)

.008 .012

(0.203 0.305)

.004 .009

(0.102 0.249)

.0250

(0.635)

BSC

.033

(0.838)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 .165

.0250 TYP

.0165

.0015

.045

.005

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:
1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

LTC3728L/LTC3728LX

3728lxfa

PART NUMBER

DESCRIPTION

COMMENTS

LTC1628/LTC1628-PG/

2-Phase, Dual Output Synchronous Step-Down

Reduces C

and C

OUT

, Power Good Output Signal, Synchronizable,

LTC1628-SYNC

DC/DC Controller

3.5V

36V, I

OUT

up to 20A, 0.8V

OUT

LTC1629/

20A to 200A PolyPhase

Synchronous Controllers

Expandable from 2-Phase to 12-Phase, Uses All

LTC1629-PG

Surface Mount Components, No Heat Sink, V

up to 36V

LTC1702A

No R

SENSE

2-Phase Dual Synchronous Step-Down

550kHz, No Sense Resistor

Controller

LTC1708-PG

2-Phase, Dual Synchronous Controller with Mobile VID

3.5V

36V, VID Sets V

OUT1

, PGOOD

LT1709/

High Efficiency, 2-Phase Synchronous Step-Down

1.3V

OUT

3.5V, Current Mode Ensures

LT1709-8

Switching Regulators with 5-Bit VID

Accurate Current Sharing, 3.5V

36V

LTC1735

High Efficiency Synchronous Step-Down

Output Fault Protection, 16-Pin SSOP

Switching Regulator

LTC1736

High Efficiency Synchronous Controller with 5-Bit Mobile Output Fault Protection, 24-Pin SSOP,
VID Control

3.5V

36V

LTC1778/LTC1778-1

No R

SENSE

Current Mode Synchronous Step-Down

Up to 97% Efficiency, 4V

36V, 0.8V

OUT

(0.9)(V

Controllers

OUT

up to 20A

LTC1929/

2-Phase Synchronous Controllers

Up to 42A, Uses All Surface Mount Components,

LTC1929-PG

No Heat Sinks, 3.5V

36V

LTC3708

Dual, 2-Phase, DC/DC Controller with Output Tracking

Current Mode, No R

SENSE

, Up/Down Tracking, Synchronizable

LTC3711

No R

SENSE

Current Mode Synchronous Step-Down

Up to 97% Efficiency, Ideal for Pentium

III Processors,

Controller with Digital 5-Bit Interface

0.925V

OUT

2V, 4V

36V, I

OUT

up to 20A

LTC3728

Dual, 550kHz, 2-Phase Synchronous Step-Down

Dual 180

Phased Controllers, V

3.5V to 35V, 99% Duty Cycle,

Controller

5x5QFN, SSOP-28

LTC3729

20A to 200A, 550kHz PolyPhase Synchronous Controller

Expandable from 2-Phase to 12-Phase, Uses all Surface Mount
Components, V

up to 36V

LTC3731

3- to 12-Phase Step-Down Synchronous Controller

60A to 240A Output Current, 0.6V

OUT

6V, 4.5V

32V

No R

SENSE

and PolyPhase are trademarks of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.

RELATED PARTS

TYPICAL APPLICATIO

Figure 14. Multioutput PolyPhase Application

PHASMD

CLKOUT

TG1

TG2

OPEN

180

LTC3729

BUCK: 2.5V/15A

PLLIN

TG1

TG2

270

LTC3728L/

LTC3728LX

BUCK: 1.5V/15A

2.5V

/30A

12V

*INPUT RIPPLE CURRENT CANCELLATION
INCREASES THE RIPPLE FREQUENCY AND
REDUCES THE RMS INPUT RIPPLE CURRENT
THUS, SAVING INPUT CAPACITORS

1.5V

/15A

1.8V

/15A

3728 F14

BUCK: 1.8V/15A

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear.com

LINEAR TECHNOLOGY CORPORATION 2002

LT/TP 0104 1K REV A · PRINTED IN USA

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC3728LCGN

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC3728LCGN