1
LTC3770
3770f
, LTC and LT are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. No R
SENSE
is a trademark of Linear
Technology Corporation. Protected by U.S. Patents including 5481178, 5487554, 6580258,
6304066, 6476589, 6774611.
Fast No R
SENSE
TM
Step-Down
Synchronous Controller with
Margining, Tracking and PLL
Wide V
IN
Range: 4V to 32V
0.67% 0.6V Reference Voltage
Output Voltage Tracking Capability
Programmable Margining
Sense Resistor Optional
True Current Mode Control
2% to 90% Duty Cycle at 200kHz
t
ON(MIN)
100ns
Phase Lock Loop Frequency Synchronization
Powerful Dual N-Channel MOSFET Driver
Adjustable Cycle-by-Cycle Current Limit
Adjustable Switching Frequency
Programmable Soft-Start
Current Foldback Protection (Disabled at Start-Up)
Output Overvoltage Protection
Micropower Shutdown: I
Q
< 30A
Power Good Output Voltage Monitor
Tracks the Reference Input Pin
Available in (5mm 5mm) QFN and 28-Lead
SSOP Packages
Distributed Power Systems
Server Power Supply
The LTC
3770 is a synchronous step-down switching
regulator controller with output voltage up/down tracking
capability and voltage margining. Its advanced functions
and high accuracy reference are ideal for powering
high performance server, ASIC and computer memory
systems.
The LTC3770 uses a constant on-time, valley current
mode control architecture to deliver very low duty factors
without requiring a sense resistor. The operating fre-
quency is selected by an external resistor and is compen-
sated for variations in input supply voltage. An internal
phase-lock loop allows the IC to be synchronized to an
external clock.
Fault protection is provided by an overvoltage comparator
and input undervoltage lockout. The regulator current limit
is user programmable. A wide supply range allows volt-
ages as high as 32V to be stepped down to as low as a 0.6V
output. Power supply sequencing is accomplished using
an external soft-start timing capacitor.
High Efficiency Step-Down Converter
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
CMDSH-3
B340A
95.3k
30.1k
10k
82k
1.8H
10F
10F
35V
x3
V
IN
5V TO 28V
V
OUT
2.5V
10A
180F
4V
x2
Si4874
Si4884
68k
0.1F
0.22F
10k
1000pF
V
OUT
10k
0.01F
+
I
ON
V
IN
TG
SW
BOOST
PLLIN
RUN
I
TH
SGND
INTV
CC
BG
PGND
SENSE
SENSE
+
V
FB
V
REFIN
LTC3770
DRV
CC
PGOOD
MPGM
V
REFOUT
V
ON
V
RNG
MARGIN
TRACK/SS
PLLFLTR
3770 TA01
LOAD CURRENT (A)
EFFICIENCY (%)
100
90
80
70
60
50
95
85
75
65
55
POWER LOSS (W)
10
0.1
1
0.01
0.01
1
10
3770 TA01b
0.1
V
IN
= 5V
V
OUT
= 2.5V
EFFICIENCY
POWER LOSS
Efficiency and Power Loss vs Load Current
2
LTC3770
3770f
32 31 30 29 28 27 26 25
9
10 11 12
TOP VIEW
UH PACKAGE
32-LEAD (5mm 5mm) PLASTIC QFN
13
33
14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1
V
RNG
V
FB
I
TH
SGND
MARGIN1
MARGIN0
I
ON
V
REFIN
SENSE
+
SENSE
PGND
BG
DRV
CC
INTV
CC
Z2
Z1
PGOOD
V
ON
RUN
FCB
Z0
BOOST
TG
SW
V
REFOUT
MPGM
TRACK/SS
PLLFLTR
PLLIN
V
IN
V
INSNS
ZV
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RUN
V
ON
PGOOD
V
RNG
V
FB
I
TH
SGND
MARGIN1
MARGIN0
I
ON
V
REFIN
V
REFOUT
MPGM
TRACK/SS
FCB
Z0
BOOST
TG
SW
PGND
BG
INTV
CC
Z2
Z1
ZV
IN
V
IN
PLLIN
PLLFLTR
Input Supply Voltage (V
IN
, V
INSNS
) ............32V to 0.3V
Boosted Topside Driver Supply Voltage
(BOOST) ................................................38V to 0.3V
SENSE
+
, SW Voltage ....................................32V to 5V
DRV
CC
, (BOOST SW) Voltages .................7V to 0.3V
V
ON
, V
RNG
, PGOOD Voltages .... INTV
CC
+ 0.3V to 0.3V
PLLFLTR, I
TH
, V
FB
, V
REFIN
Voltages .......... 2.7V to 0.3V
TRACK/SS, FCB, Z0, Z1, Z2, RUN, PLLIN, MARGIN0,
MARGIN1 Voltages ............... INTV
CC
+ 0.3V to 0.3V
ABSOLUTE AXI U RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
ORDER PART
NUMBER
LTC3770EG
G PART
MARKING
LTC3770EG
T
JMAX
= 125C,
JA
= 130C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
(Note 1)
INTV
CC
, ZV
IN
Voltages .................................7V to 0.3V
TG, BG, INTV
CC
Peak Currents ................................... 4A
TG, BG, INTV
CC
RMS Currents ............................. 50mA
Operating Ambient Temperature
Range (Note 4) ................................... 40C to 85C
Junction Temperature (Note 2) ............................. 125C
Storage Temperature Range ................. 65C to 125C
QFN Reflow Peak Body Temperature .................... 245C
Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART
NUMBER
LTC3770EUH
UH PART
MARKING
3770
T
JMAX
= 125C,
JA
= 34C/ W
EXPOSED PAD IS SGND (PIN 33)
MUST BE SOLDERED TO THE PCB
3
LTC3770
3770f
The
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T
A
= 25C. V
IN
= 15V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
I
Q
Input DC Supply Current
Normal Operation
1300
2200
A
Shutdown Supply Current
30
50
A
V
FB
Feedback Voltage Accuracy (Note 3)
V
REFIN
= V
REFOUT
; I
TH
= 1.2V (0C to 85C)
0.596
0.6
0.604
V
V
REFIN
= V
REFOUT
; I
TH
= 1.2V
0.594
0.6
0.606
V
V
FB(LINEREG)
Feedback Voltage Line Regulation
V
IN
= 4V to 30V, I
TH
= 1.2V (Note 3)
0.002
%/V
V
FB(LOADREG)
Feedback Voltage Load Regulation
I
TH
= 0.5V to 1.9V (Note 3)
0.05
0.3
%
V
RUN
Run Pin On Threshold
V
RUN
Rising
1
1.5
1.9
V
I
SS/TRACK
Soft-Start Charging Current
V
SS/TRACK
= 0V
1.1
1.4
1.7
A
I
FB
Feedback Pin Input Current
100
20
100
nA
g
m(EA)
Error Amplifier Transconductance
I
TH
= 1.2V (Note 3)
1
1.3
1.6
mS
V
FCB
Forced Continuous Threshold
0.57
0.6
0.63
V
I
FCB
Forced Continuous Pin Current
V
FCB
= 0V
1
2
A
t
ON
On-Time
I
ON
= 60A, V
ON
= 1.5V
210
250
290
ns
I
ON
= 60A, V
ON
= 0V
90
115
150
ns
t
ON(MIN)
Minimum On-Time
I
ON
= 180A, V
ON
= 0V
50
100
ns
t
OFF(MIN)
Minimum Off-Time
250
400
ns
V
SENSE(MAX)
Maximum Current Sense Threshold
V
RNG
= 1V, V
FB
= V
REFIN
30mV
113
133
153
mV
V
SENSE
V
SENSE
+
V
RNG
= 0V, V
FB
= V
REFIN
30mV
50
67
84
mV
V
RNG
= INTV
CC
, V
FB
= V
REFIN
30mV
228
268
308
mV
V
SENSE(MIN)
Minimum Current Sense Threshold
V
RNG
= 1V, V
FB
= V
REFIN
+ 30mV
60
mV
V
SENSE
V
SENSE
+
V
RNG
= 0V, V
FB
= V
REFIN
+ 30mV
30
mV
V
RNG
= INTV
CC
, V
FB
= V
REFIN
+ 30mV
120
mV
V
FB(OV)
Output Overvoltage Fault Threshold Offset
7
10
13
%
V
IN(UVLO
+
)
Undervoltage Lockout
V
IN
Falling
3.2
3.9
V
V
IN(UVLO
)
Undervoltage Lockout
V
IN
Rising
3.3
4
V
V
MGN(TH)
MARGIN0, MARGIN1 Input Thresholds
1.4
V
V
MPGM
MPGM Pin Voltage
1.18
V
TG R
UP
TG Driver Pull-Up On Resistance
TG High
1.9
2.5
TG R
DOWN
TG Driver Pull-Down On Resistance
TG Low
1.2
2.5
BG R
UP
BG Driver Pull-Up On Resistance
BG High
1.9
3
BG R
DOWN
BG Driver Pull-Down On Resistance
BG Low
0.7
1.5
TG t
r
TG Rise Time
C
LOAD
= 3300pF
20
ns
TG t
f
TG Fall Time
C
LOAD
= 3300pF
20
ns
BG t
r
BG Rise Time
C
LOAD
= 3300pF
20
ns
BG t
f
BG Fall Time
C
LOAD
= 3300pF
20
ns
4
LTC3770
3770f
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
as follows:
LTC3770EG: T
J
= T
A
+ (P
D
130C/W)
LTC3770EUH: T
J
= T
A
+ (P
D
34C/W)
Note 3: The 3770 is tested in a feedback loop that adjusts V
FB
to achieve a
specified error amplifier output voltage (I
TH
). For these tests, V
REFOUT
=
V
REFIN
.
Note 4: The LTC3770E is guaranteed to meet performance specifications
from 0C to 70C. Specifications over the 40C to 85C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
The
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T
A
= 25C. V
IN
= 15V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Internal V
CC
Regulator
V
INTVCC
Internal V
CC
Voltage
6V < V
IN
< 30V
4.7
5
5.3
V
V
LDO(LOADREG)
Internal V
CC
Load Regulation
I
CC
= 0mA to 20mA
0.1
2
%
Phased-Locked Loop
R
PLLIN
PLLIN Input Resistance
50
k
I
PLLFLTR
Phase Detector Output Current
Sink Capability
f
PLLIN
< f
0
15
A
Source Capability
f
PLLIN
> f
0
15
A
PGOOD Output
V
FBH
PGOOD Upper Threshold
V
FB
Rising
7
10
13
%
V
FBL
PGOOD Lower Threshold
V
FB
Falling
7
10
13
%
V
FB(HYS)
PGOOD Hysteresis
V
FB
Returning
1.5
3
%
V
PGL
PGOOD Low Voltage
I
PGOOD
= 5mA
0.15
0.4
V
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
On-Time vs I
ON
Current
On-Time vs V
ON
Voltage
Current Sense Threshold
vs I
TH
Voltage
I
TH
VOLTAGE (V)
0
200
CURRENT SENSE THRESHOLD (mV)
100
0
100
200
300
0.5
1.0
1.5
2.0
3770 G01
2.5
3.0
V
RNG
=
1V
0.7V
0.5V
1.4V
2V
I
ON
CURRENT (A)
1
10
ON-TIME (ns)
100
1k
10k
10
100
3770
G02
V
VON
= 0V
V
ON
VOLTAGE (V)
0
ON-TIME (ns)
400
600
3770
G03
200
0
1
2
5
4
3
1200
1000
800
I
ION
= 60A
5
LTC3770
3770f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Maximum Current Sense
Threshold vs Temperature
Maximum Current Sense
Threshold vs V
RNG
Voltage
V
RNG
VOLTAGE (V)
0.5
0
MAXIMUM CURRENT SENSE THRESHOLD (mV)
50
100
150
200
300
0.75
1.0
1.25
1.5
3770 G05
1.75
2.0
250
TEMPERATURE (C)
50
25
100
MAXIMUM CURRENT SENSE THRESHOLD (mV)
120
150
0
50
75
3770 G06
110
140
130
25
100
125
V
RNG
= 1V
TEMPERATURE (C)
50
ON-TIME (ns)
200
250
300
25
75
3770
G04
150
100
25
0
50
100
125
50
0
I
ION
= 30A
V
VON
= 0V
On-Time vs Temperature
INPUT VOLTAGE (V)
0
INPUT CURRENT (mA)
1.5
2.0
2.5
15
25
3770
G08
1.0
0.5
5
10
20
30
35
0
Input Current vs Input Voltage
Error Amplifier g
m
vs Temperature
TEMPERATURE (C)
50
25
0.6
g
m
(mS)
1.0
1.6
0
50
75
3770 G07
0.8
1.4
1.2
25
100
125
Shutdown Current vs Input Voltage
INPUT VOLTAGE (V)
0
SHUTDOWN CURRENT (
A)
15
25
3770
G09
5
10
20
30
35
30
40
60
50
20
10
0
FCB Pin Current vs Temperature
Undervoltage Lockout Threshold
vs Temperature
TEMPERATURE (C)
50
FCB PIN CURRENT (
A)
0.50
0.25
0
25
75
3770
G11
0.75
1.00
25
0
50
100
125
1.25
1.50
TEMPERATURE (C)
50
2.0
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
2.5
3.0
3.5
4.0
25
0
25
50
3770 G12
75
100
125
INTV
CC
LOAD CURRENT (mA)
0
INTV
CC
(%)
0.2
0.1
0
40
3770 G10
0.3
0.4
10
20
30
50
INTV
CC
Load Regulation
6
LTC3770
3770f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Transient Response
Track Down
Track Up
I
TH
Voltage vs Load Current
Efficiency vs Load Current
Frequency vs Input Voltage
V
OUT
2V/DIV
TRACK/SS
AND V
FB
500mV/DIV
250ms/DIV
3770 G13
TRACK/SS
FIGURE 12 CIRCUIT
V
FB
V
OUT
V
OUT
2V/DIV
TRACK/SS
AND V
FB
500mV/DIV
250ms/DIV
3770 G14
TRACK/SS
V
FB
V
OUT
FIGURE 12 CIRCUIT
V
OUT
100mV/DIV
I
L
5A/DIV
STEP
0A TO 10A
20s/DIV
3770 G15
FIGURE 12 CIRCUIT
LOAD CURRENT (A)
EFFICIENCY (%)
100
90
95
85
80
75
50
55
60
65
70
0.01
1
10
3770 G16
0.1
DISCONTINUOUS
MODE
CONTINUOUS
MODE
FIGURE 12 CIRCUIT
INPUT VOLTAGE (V)
FREQUENCY (kHz)
480
460
440
420
400
300
320
340
360
380
0
20
30
25
3770 G18
10
15
5
FCB = 0V
FIGURE 12 CIRCUIT
I
OUT
= 10A
I
OUT
= 0A
LOAD CURRENT (A)
I
TH
VOLTAGE (V)
2.5
1.5
2.0
1.0
0.5
0
0
8
12
10
3770 G17
4
6
2
DISCONTINUOUS
MODE
FIGURE 12 CIRCUIT
CONTINUOUS
MODE
Frequency vs Load Current
Efficiency vs Input Voltage
INPUT VOLTAGE (V)
EFFICIENCY (%)
100
95
90
85
80
70
75
0
20
30
25
3770 G19
10
15
5
FCB = 5V
FIGURE 12 CIRCUIT
I
LOAD
= 10A
I
LOAD
= 1A
LOAD CURRENT (A)
0
8
12
10
4
6
2
FREQUENCY (kHz)
500
450
400
350
300
250
0
50
100
150
200
3770 G20
DISCONTINUOUS
MODE
CONTINUOUS
MODE
FIGURE 12 CIRCUIT
7
LTC3770
3770f
V
FB
(V)
0
0
MAXIMUM CURRENT SENSE THRESHOLD (mV)
160
0.1
0.2
0.3
0.4
3770 G21
0.5
0.6
80
60
40
140
120
20
100
V
RNG
= 1V
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
U
U
U
PI FU CTIO S
V
RNG
(Pin 1/Pin 4): Sense Voltage Range Input. The
voltage at this pin is ten times the nominal sense voltage
at maximum output current and can be set from 0.5V to 2V
by a resistive divider from INTV
CC
. The nominal sense
voltage defaults to 50mV when this pin is tied to ground,
200mV when tied to INTV
CC
. Do not set this voltage
between 0.5V to ground or 2V to INTV
CC
.
V
FB
(Pin 2/Pin 5): Error Amplifier Feedback Input. This pin
connects the error amplifier input to an external resistive
divider from V
OUT
.
I
TH
(Pin 3/Pin 6): Current Control Threshold and Error
Amplifier Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
ranges from 0V to 2.4V with 0.75V corresponding to zero
sense voltage (zero current). There is an integrated ca-
pacitor of 20pF connected to this pin.
SGND (Pin 4/Pin 7): Signal Ground. All small-signal
components and compensation components should con-
nect to this ground, which in turn connects to PGND at one
point.
MARGIN1 (Pin 5/Pin 8): The MSB Logic Input for the
Margining Function. Together with the MARGIN0 pin
determines whether the IC is in margin high, margin low,
or no margin state. This pin has a 50k internal pull-down
resistor.
MARGIN0 (Pin 6/Pin 9): The LSB Logic Input for the
Margining Function. Together with the MARGIN1 pin
determines whether the IC is in margin high, margin low,
or no margin state. This pin has a 50k internal pull-down
resistor.
I
ON
(Pin 7/Pin 10): On-Time Current Input. Tie a resistor
from this pin to ground to set the one-shot timer current
and thereby set the switching frequency.
V
REFIN
(Pin 8/Pin 11): Error Amplifier Reference Input.
The voltage at this pin must be greater than 0.5V and less
than 1V.
V
REFOUT
(Pin 9/Pin 12): Buffered Internal 0.6V Reference
Output. The maximum current sinking limit is 50A at
this pin. Do not put a filter capacitor larger than 100pF on
this pin.
MPGM (Pin 10/Pin 13): Programmable Margining Input.
A resistor from this pin to ground sets the margining
current. This current, together with the resistor between
the V
REFOUT
and V
REFIN
pins, determines the margining
voltage offset.
TRACK/SS (Pin 11/Pin 14): Output Voltage Tracking and
Soft Start Input. When the IC is configured to be the master
of two outputs, a capacitor to ground at this pin sets the
ramp rate for the output voltage. When the IC is configured
(UH Package/G Package)
Ion Current vs V
IN
Current Limit Foldback
INPUT VOLTAGE (V)
0
ION CURRENT (
A)
15
25
3770
G22
5
10
20
30
35
80
60
40
140
120
20
100
0
R
ON
= 82k
8
LTC3770
3770f
U
U
U
PI FU CTIO S
(UH Package/G Package)
to be the slave of two outputs, the V
FB
voltage of the master
IC is reproduced by a resistor divider and applied to this
pin. An internal 1.4A soft start current is charging this pin
during the soft-start phase.
PLLFLTR (Pin 12/Pin 15): The Phase-Locked Loop's
Lowpass Filter is Tied to This Pin. The voltage at this pin
defaults to 1.18V when the IC is not synchronized with an
external clock at the PLLIN pin.
PLLIN (Pin 13/Pin 16): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with a 50k resistor.
V
IN
(Pin 14/Pin 17): Main Input Supply. Decouple this pin
to PGND with a capacitor (0.1F to 1F).
V
INSNS
(Pin 15) UH Package: V
IN
Voltage Sense Input.
Normally this pin is tied to V
IN
. However, in certain
applications when the IC is powered from a separate
supply, V
INSNS
is tied to the upper MOSFET supply to sense
the V
IN
voltage. The pin is co-bonded with V
IN
in the SSOP
package.
ZV
IN
(Pin 16/Pin 18): Post-Package Zener-Trim Voltage
Input. Under normal conditions this pin should always be
connected to INTV
CC
.
Z1 (Pin 17/Pin 19): Post-Package Zener-Trim Control.
This pin is a multifunctional pin used in production for
post-package trimming and tracking. Ground this pin
under normal soft-start operation. Connecting this pin to
INTV
CC
will turn off the soft-start current during tracking.
Z2 (Pin 18/Pin 20): Post-Package Zener-Trim Control.
This pin is used in production for Post-Package trimming.
Ground this pin or tie to INTV
CC
under normal operation.
INTV
CC
(Pin 19/Pin 21): Internal 5V Regulator Output. The
control circuits are powered from this voltage. Decouple
this pin to PGND with a minimum of 10F low ESR
tantalum or ceramic capacitor.
DRV
CC
(Pin 20) UH Package Gate: Driver Voltage Input.
Normally connected to the INTV
CC
regulated output. Do
not exceed 7V at this pin. This pin is co-bonded to INTV
CC
internally in the SSOP package.
BG (Pin 21/Pin 22): Bottom Gate Driver Output. This pin
drives the gate of the bottom N-channel MOSFET between
ground and INTV
CC
.
PGND (Pin 22/Pin 23): Power Ground. Connect this pin
closely to the source of the bottom N-channel MOSFET,
the () terminal of C
VCC
and the () terminal of C
IN
.
SENSE
(Pin 23) UH Package: Current Sense Comparator
Input. The () input to the current comparator is used to
accurately Kelvin sense the bottom side of the sense
resistor or MOSFET. This pin is co-bonded with PGND
internally in the SSOP package.
SENSE
+
(Pin 24) UH Package: Current Sense Comparator
Input. The (+) input to the current comparator is normally
connected to the SW node unless using a sense resistor.
This pin is co-bonded with SW internally in the SSOP
package.
SW (Pin 25/Pin 24): Switch Node. The () terminal of the
boot-strap capacitor CB connects here. This pin swings
from a diode voltage drop below ground up to V
IN
.
TG (Pin 26/Pin 25): Top Gate Drive Output. This pin drives
the top N-channel MOSFET with a voltage swing equal to
INTV
CC
, superimposed on the switch node voltage SW.
BOOST (Pin 27/Pin 26): Boosted Floating Driver Supply.
The (+) terminal of the boot-strap capacitor CB connects
here. This pin swings from a diode voltage drop below
INTV
CC
up to V
IN
+ INTV
CC
.
Z0 (Pin 28/Pin 27): Dead Time Control Input. Applying a
DC voltage will vary the dead time between TG-Low and
BG-High transition. Do not force a voltage higher than 5V
on this pin.
FCB (Pin 29/Pin 28): Forced Continuous Input. Connect
this pin to SGND to force continuous synchronization
operation at low load, to INTV
CC
to enable discontinuous
mode operation at low load or to a resistive divider from a
secondary output when using a secondary winding.
RUN (Pin 30/Pin 1): Run Control Input. A voltage above
1.5V turns on the IC. Forcing this pin below 1.5V shuts
down the device.
9
LTC3770
3770f
80% V
REFIN
2.0V
0.5V
V
RNG
1
+
+
+
+
+
7
31
I
ON
29 FCB
14 V
IN
1A
R
ON
V
VON
I
ION
t
ON
=
(10pF)
R
S
Q
20k
I
CMP
I
REV
Q6
3.3A
RUN
SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
BG
ON
FCNT
F
0.6V
OV
1
240k
Q1
Q2
1.5V
I
TH
R
C
C
C1
EA
SS
Q4
3
8
9
11
SGND
R2
R1
RUN
PGND
22
PGOOD
32
DRV
CC
20
INTV
CC
INTV
CC
19
SW
25
TG
C
B
V
IN
C
IN
BOOST
27
+
+
OV
UV
C
VCC
V
OUT
M2
M1
L1
C
OUT
D
B
I
THB
V
OUT
0.6V
4.8V
V
ON
R
SENSE
(OPTIONAL)*
SENSE
+
SENSE
23
24
SENSE
+
SENSE
BG
M2
*CONNECTION W/O
SENSE RESISTOR
SW
PGND
(0.5~2)
V
REFIN
R3
+
FOLDBACK
+
0.25V
+
+
V
REFOUT
0.6V
REF
V
IN
10K
90K
10K
+
5
MARGIN1
10
MPGM
1.18V
R4
TRACK/SS
12K
FOLDBACK
DISABLED
AT START-UP*
RUN
30
MARGIN0
6
V
FB
4
2
PLLIN
PLLFLTR
PLL-SYNC
13
12
+
V
INSNS
15
17
18
28
Z0
Z1
Z2
16
Z
VIN
+
+
5V
REG
1.4A
C
SS
21
26
R
R
R
INTV
CC
FU CTIO AL DIAGRA
U
U
W
(UH Package)
V
ON
(Pin 31/Pin 2): On-Time Voltage Input. Connecting
this pin to the output voltage makes the on-time propor-
tional to V
OUT
. The comparator input defaults to 0.6V when
the pin is grounded and defaults to 4.8V when the pin is
tied to INTV
CC
.
PGOOD (Pin 32/Pin 3): Power Good Output. Open drain
logic output that is pulled to ground when the output
voltage is not within 10% of the regulation point, after the
internal 25s power bad mask timer expires.
Exposed Pad (Pin 33) UH Package: Signal Ground. Must
be soldered to the PCB ground for electrical contact and
optimum thermal performance.
U
U
U
PI FU CTIO S
(UH Package/G Package)
10
LTC3770
3770f
OPERATIO
U
Main Control Loop
The LTC3770 is a current mode controller for DC/DC
step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by a
one-shot timer OST. When the top MOSFET is turned off,
the bottom MOSFET is turned on until the current com-
parator I
CMP
trips, restarting the one-shot timer and initi-
ating the next cycle. Inductor current is determined by
sensing the voltage between the SENSE
(PGND on G
Package) and SENSE
+
(SW on G Package) pins using a
sense resistor or the bottom MOSFET on-resistance . The
voltage on the I
TH
pin sets the comparator threshold
corresponding to inductor valley current. The error ampli-
fier EA adjusts this voltage by comparing the feedback
signal V
FB
from a reference voltage set by the V
REFIN
pin.
If the load current increases, it causes a drop in the
feedback voltage relative to the reference. The I
TH
voltage
then rises until the average inductor current again matches
the load current.
At low load currents, the inductor current can drop to zero
and become negative. This is detected by current reversal
comparator I
REV
which then shuts off M2, resulting in
discontinuous operation. Both switches will remain off
with the output capacitor supplying the load current until
the I
TH
voltage rises above the zero current level (0.75V)
to initiate another cycle. Discontinuous mode operation is
disabled by comparator F when the FCB pin is brought
below 0.6V, forcing continuous synchronous operation.
The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an on-
time that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in V
IN
. The nominal frequency can be adjusted with an
external resistor R
ON
.
For applications with stringent constant frequency re-
quirements, the LTC3770 can be synchronized with an
external clock. By programming the nominal frequency of
the LTC3770 the same as the external clock frequency, the
LTC3770 behaves as a constant frequency part against the
load and supply variations.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a 10% window around the regulation point after the
internal 25s power bad mask timer expires. Furthermore,
in an overvoltage condition, M1 is turned off and M2 is
turned on immediately and held on until the overvoltage
condition clears.
Foldback current limiting is provided if the output is
shorted to ground. As V
FB
drops, the buffered current
threshold voltage I
THB
is pulled down and clamped to
0.9V. This reduces the inductor valley current level to one
tenth of its maximum value as V
FB
approaches 0V. Foldback
current limiting is disabled at start-up.
Pulling the RUN pin low forces the controller into its
shutdown state, turning off both M1 and M2. Forcing a
voltage above 1.5V will turn on the device.
INTV
CC
Power
Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTV
CC
pin. The top MOSFET driver is powered from a
floating bootstrap capacitor C
B
. This capacitor is re-
charged from INTV
CC
through an external Schottky diode
D
B
when the top MOSFET is turned off. If the input voltage
is low and INTV
CC
drops below 3.2V, undervoltage
lockout circuitry prevents the power switches from
turning on.
11
LTC3770
3770f
The basic LTC3770 application circuit is shown in
Figure 12. External component selection is primarily de-
termined by the maximum load current and begins with
the selection of the sense resistance and power MOSFET
switches. The LTC3770 uses either a sense resistor or the
on-resistance of the synchronous power MOSFET for
determining the inductor current. The desired amount of
ripple current and operating frequency largely deter-
mines the inductor value. Finally, C
IN
is selected for its
ability to handle the large RMS current into the converter
and C
OUT
is chosen with low enough ESR to meet the
output voltage ripple and transient specification.
Maximum Sense Voltage and V
RNG
Pin
Inductor current is determined by measuring the voltage
across a sense resistance that appears between the SENSE
(PGND on G Package) and SENSE
+
(SW on G Package)
pins. The maximum sense voltage is set by the voltage
applied to the V
RNG
pin and is equal to approximately
(0.133)V
RNG
. The current mode control loop will not allow
the inductor current valleys to exceed (0.133)V
RNG
/R
SENSE
.
In practice, one should allow some margin for variations
in the LTC3770 and external component values and a good
guide for selecting the sense resistance is:
R
V
I
SENSE
RNG
OUT MAX
=
10
(
)
An external resistive divider from INTV
CC
can be used to
set the voltage of the V
RNG
pin between 0.5V and 2V
resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the V
RNG
pin can be tied to SGND or INTV
CC
in which case the nominal sense voltage defaults to 50mV
or 200mV, respectively. The maximum allowed sense
voltage is about 1.33 times this nominal value.
Connecting the SENSE
+
and SENSE
Pins
The LTC3770 comes in UH and G packages. The UH
package IC can be used with or without a sense resistor.
When using a sense resistor, place it between the source
of the bottom MOSFET, M2, and PGND. Connect the
SENSE
+
and SENSE
pins to the top and bottom of the
sense resistor. Using a sense resistor provides a well
defined current limit, but adds cost and reduces efficiency.
Alternatively, one can eliminate the sense resistor and use
the bottom MOSFET as the current sense element by
simply connecting the SENSE
+
pin to the SW pin and
SENSE
pin to PGND. This improves efficiency, but one
must carefully choose the MOSFET on-resistance as dis-
cussed below.
Power MOSFET Selection
The LTC3770 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V
(BR)DSS
,
threshold voltage V
(GS)TH
, on-resistance R
DS(ON)
, reverse
transfer capacitance C
RSS
and maximum current I
DS(MAX)
.
The gate drive voltage is set by the 5V INTV
CC
supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3770 applications. If the input voltage is
expected to drop below 5V, then sub-logic level threshold
MOSFETs should be considered.
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on-
resistance. MOSFET on-resistance is typically specified
with a maximum value R
DS(ON)(MAX)
at 25C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
R
R
DS ON MAX
SENSE
T
(
)(
)
=
The
T
term is a normalization factor (unity at 25C)
accounting for the significant variation in on-resistance
Figure 1. R
DS(ON)
vs Temperature
JUNCTION TEMPERATURE (C)
50
T
NORMALIZED ON-RESISTANCE
1.0
1.5
150
3770 F01
0.5
0
0
50
100
2.0
APPLICATIO S I FOR ATIO
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LTC3770
3770f
with temperature, typically about 0.4%/C as shown in
Figure 1. For a maximum junction temperature of 100C,
using a value
T
= 1.3 is reasonable.
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and
the load current. When the LTC3770 is operating in
continuous mode, the duty cycles for the MOSFETs are:
D
V
V
D
V
V
V
TOP
OUT
IN
BOT
IN
OUT
IN
=
=
The resulting power dissipation in the MOSFETs at maxi-
mum output current are:
P
TOP
= D
TOP
I
OUT(MAX)
2
T(TOP)
R
DS(ON)(MAX)
+ k V
IN
2
I
OUT(MAX)
C
RSS
f
P
BOT
= D
BOT
I
OUT(MAX)
2
T(BOT)
R
DS(ON)(MAX)
Both MOSFETs have I
2
R losses and the top MOSFET
includes an additional term for transition losses, which are
largest at high input voltages. The constant k = 1.7A
1
can
be used to estimate the amount of transition loss. The
bottom MOSFET losses are greatest when the bottom duty
cycle is near 100%, during a short-circuit or at high input
voltage.
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
The operating frequency of LTC3770 applications is deter-
mined implicitly by the one-shot timer that controls the
on-time t
ON
of the top MOSFET switch. The on-time is set
by the current out of the I
ON
pin and the voltage at the V
ON
pin according to:
t
V
I
pF
ON
VON
ION
=
(
)
10
Tying a resistor R
ON
to SGND from the I
ON
pin yields an on-
time inversely proportional to 1/3 V
IN
. The current out of
the I
ON
pin is:
I
V
R
ION
IN
ON
=
3
For a step-down converter, this results in approximately
constant frequency operation as the input supply varies:
f
V
V
R
pF
H
OUT
VON
ON
Z
=
(
)
[
]
3
10
To hold frequency constant during output voltage changes,
tie the V
ON
pin to V
OUT
. The V
ON
pin has internal clamps
that limit its input to the one-shot timer. If the pin is tied
below 0.6V, the input to the one-shot is clamped at 0.6V.
Similarly, if the pin is tied above 4.8V, the input is clamped
at 4.8V. In high V
OUT
applications, tie V
ON
to INTV
CC
.
Figures 2a and 2b show how R
ON
relates to switching
frequency for several common output voltages.
R
ON
(k)
100
100
SWITCHING FREQUENCY (kHz)
1000
1000
3770 F02a
V
OUT
= 3.3V
V
OUT
= 1.5V
V
OUT
= 2.5V
R
ON
(k)
10
100
SWITCHING FREQUENCY (kHz)
1000
100
1000
3770 F02b
V
OUT
= 3.3V
V
OUT
= 12V
V
OUT
= 5V
Figure 2a. Switching Frequency vs R
ON
(V
ON
= 0V)
Figure 2b. Switching Frequency vs R
ON
(V
ON
= INTV
CC
)
APPLICATIO S I FOR ATIO
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LTC3770
3770f
When there is no R
ON
resistor connected to the I
ON
pin, the
on-time t
ON
is theoretically infinite, which in turn could
damage the converter. To prevent this, the LTC3770 will
detect this fault condition and provide a minimum I
ON
current of 5A to 10A.
Changes in the load current magnitude will cause fre-
quency shift. Parasitic resistance in the MOSFET switches
and inductor reduce the effective voltage across the induc-
tance, resulting in increased duty cycle as the load current
increases. By lengthening the on-time slightly as current
increases, constant frequency operation can be main-
tained. This is accomplished with a resistive divider from
the I
TH
pin to the V
ON
pin and V
OUT
. The values required will
depend on the parasitic resistances in the specific applica-
tion. A good starting point is to feed about 25% of the
voltage change at the I
TH
pin to the V
ON
pin as shown in
Figure 3a. Place capacitance on the V
ON
pin to filter out the
I
TH
variations at the switching frequency. The resistor load
on I
TH
reduces the DC gain of the error amp and degrades
load regulation, which can be avoided by using the PNP
emitter follower of Figure 3b.
Minimum Off-Time and Dropout Operation
The minimum off-time t
OFF(MIN)
is the smallest amount of
time that the LTC3770 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 250ns. The
minimum off-time limit imposes a maximum duty cycle of
t
ON
/(t
ON
+ t
OFF(MIN)
). If the maximum duty cycle is reached,
due to a dropping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:
V
V
t
t
t
IN MIN
OUT
ON
OFF MIN
ON
(
)
(
)
=
+
A plot of maximum duty cycle vs frequency is shown in
Figure 4.
C
VON
0.01F
R
VON2
100k
R
VON1
30k
C
C
V
OUT
R
C
(3a)
(3b)
V
ON
I
TH
LTC3770
C
VON
0.01F
R
VON2
10k
Q1
2N5087
R
VON1
3k
10k
C
C
3770 F03
V
OUT
INTV
CC
R
C
V
ON
I
TH
LTC3770
Figure 3. Correcting Frequency Shift with Load Current Changes
2.0
1.5
1.0
0.5
0
0
0.25
0.50
0.75
3770 F04
1.0
DROPOUT
REGION
DUTY CYCLE (V
OUT
/V
IN
)
SWITCHING FREQUENCY (MHz)
Figure 4. Maximum Switching Frequency vs Duty Cycle
Inductor Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:
=
-
I
V
f L
V
V
L
OUT
OUT
IN
1
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
A reasonable starting point is to choose a ripple current
that is about 40% of I
OUT(MAX)
. The largest ripple current
occurs at the highest V
IN
. To guarantee that ripple current
does not exceed a specified maximum, the inductance
APPLICATIO S I FOR ATIO
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14
LTC3770
3770f
should be chosen according to:
L
V
f I
V
V
OUT
L MAX
OUT
IN MAX
=
-
(
)
(
)
1
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron
cores, forcing the use of more expensive ferrite, molyper-
malloy or Kool M
cores. A variety of inductors designed
for high current, low voltage applications are available
from manufacturers such as Sumida, Panasonic, Coil-
tronics, Coilcraft and Toko.
Schottky Diode D1 Selection
The Schottky diode D1 shown in Figure 12 conducts
during the dead time between the conduction of the power
MOSFET switches. It is intended to prevent the body diode
of the bottom MOSFET from turning on and storing charge
during the dead time, which can cause a modest (about
1%) efficiency loss. The diode can be rated for about one
half to one fifth of the full load current since it is on for only
a fraction of the duty cycle. In order for the diode to be
effective, the inductance between it and the bottom MOS-
FET must be as small as possible, mandating that these
components be placed adjacently. The diode can be omit-
ted if the efficiency loss is tolerable.
C
IN
and C
OUT
Selection
The input capacitance C
IN
is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.
I
I
V
V
V
V
RMS
OUT MAX
OUT
IN
IN
OUT
(
)
1
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT(MAX)
/ 2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief. Note that ripple
current ratings from capacitor manufacturers are often
based on only 2000 hours of life which makes it advisable
to derate the capacitor.
The selection of C
OUT
is primarily determined by the ESR
required to minimize voltage ripple and load step
transients. The output ripple V
OUT
is approximately
bounded by:
+
V
I ESR
fC
OUT
L
OUT
1
8
Since I
L
increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to signifi-
cant ringing. When used as input capacitors, care must be
taken to ensure that ringing from inrush currents and
switching does not pose an overvoltage hazard to the
power switches and controller. To dampen input voltage
transients, add a small 5F to 50F aluminum electrolytic
capacitor with an ESR in the range of 0.5 to 2. High
performance through-hole capacitors may also be used,
but an additional ceramic capacitor in parallel is recom-
mended to reduce the effect of their lead inductance.
Top MOSFET Driver Supply (C
B
, D
B
)
An external bootstrap capacitor C
B
connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode D
B
from INTV
CC
when the switch node is low. When the top MOSFET turns
Kool M is a registered trademark of Magnetics, Inc.
APPLICATIO S I FOR ATIO
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LTC3770
3770f
on, the switch node rises to V
IN
and the BOOST pin rises
to approximately V
IN
+ INTV
CC
. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications 0.1F to 0.47F, X5R or
X7R dielectric capacitor is adequate.
Discontinuous Mode Operation and FCB Pin
The FCB pin determines whether the bottom MOSFET
remains on when current reverses in the inductor. Tying
this pin above its 0.6V threshold enables discontinuous
operation where the bottom MOSFET turns off when
inductor current reverses. The load current at which
current reverses and discontinuous operation begins de-
pends on the amplitude of the inductor ripple current and
will vary with changes in V
IN
. Tying the FCB pin below the
0.6V threshold forces continuous synchronous operation,
allowing current to reverse at light loads and maintaining
high frequency operation. To prevent forcing current back
into the main power supply, potentially boosting the input
supply to a dangerous voltage level, forced continuous
mode of operation is disabled when the TRACK/SS voltage
is 20% below the reference voltage during soft-start or
tracking up. Forced continuous mode of operation is also
disabled when the TRACK/SS voltage is below 0.1V during
tracking down operation. During these two periods, the
PGOOD signal is forced low.
In addition to providing a logic input to force continuous
operation, the FCB pin provides a mean to maintain a
flyback winding output when the primary is operating in
discontinuous mode. The secondary output V
OUT2
is nor-
mally set as shown in Figure 5 by the turns ratio N of the
transformer. However, if the controller goes into discon-
tinuous mode and halts switching due to a light primary
load current, then V
OUT2
will droop. An external resistor
divider from V
OUT2
to the FCB pin sets a minimum voltage
V
OUT2(MIN)
below which continuous operation is forced
until V
OUT2
has risen above its minimum.
V
V
R
R
OUT MIN
2
0 6
1
4
3
(
)
.
=
+
Fault Conditions: Current Limit and Foldback
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage. In
the LTC3770, the maximum sense voltage is controlled by
the voltage on the V
RNG
pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
I
V
R
I
LIMIT
SNS MAX
DS ON
T
L
=
+
(
)
(
)
1
2
The current limit value should be checked to ensure that
I
LIMIT(MIN)
> I
OUT(MAX)
. The minimum value of current limit
generally occurs with the largest V
IN
at the highest ambi-
ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of I
LIMIT
which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the R
DS(ON)
of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET on-
resistance. Data sheets typically specify nominal and
maximum values for R
DS(ON)
, but not a minimum. A
reasonable assumption is that the minimum R
DS(ON)
lies
the same percentage below the typical value as the maxi-
mum lies above it. Consult the MOSFET manufacturer for
further guidelines.
To further limit current in the event of a short circuit to
ground, the LTC3770 includes foldback current limiting. If
the output falls by more than 60%, then the maximum
sense voltage is progressively lowered to about one tenth
of its full value.
Figure 5. Secondary Output Loop
V
IN
LTC3770
SGND
FCB
TG
SW
R3
R4
3770 F05
T1
1:N
BG
PGND
+
C
OUT2
1F
V
OUT1
V
OUT2
V
IN
+
C
IN
1N4148
+
C
OUT
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LTC3770
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INTV
CC
Regulator
An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3770. The INTV
CC
pin can supply up to
50mA RMS and must be bypassed to ground with a
minimum of 10F low ESR tantalum capacitor or other low
ESR capacitor. Good bypassing is necessary to supply the
high transient currents required by the MOSFET gate
drivers. Applications using large MOSFETs with a high
input voltage and high frequency of operation may cause
the LTC3770 to exceed its maximum junction temperature
rating or RMS current rating. Most of the supply current
drives the MOSFET gates. In continuous mode operation,
this current is I
GATECHG
= f(Q
g(TOP)
+ Q
g(BOT)
). The junction
temperature can be estimated from the equations given in
Note 2 of the Electrical Characteristics. For example, the
LTC3770EG is limited to less than 14mA from a 30V
supply:
T
J
= 70C + (14mA)(30V)(130C/W) = 125C
For applications where more current is needed than INTV
CC
could supply, INTV
CC
could be driven by an external
supply with a voltage higher than 5.3V. However, the
INTV
CC
pin should not exceed its absolute maximum
voltage of 7V.
External Gate Drive Buffers
The LTC3770 drivers are adequate for driving up to about
50nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
frequencies requiring greater RMS currents will benefit
from using external gate drive buffers such as the LTC1693.
Alternately, the external buffer circuit shown in Figure 6
can be used.
Figure 6. Optional External Gate Driver
Q1
FMMT619
GATE
OF M1
TG
BOOST
SW
Q2
FMMT720
Q3
FMMT619
GATE
OF M2
BG
3770 F06
INTV
CC
PGND
Q4
FMMT720
10
10
Soft-Start and Tracking
The LTC3770 has the ability to either soft start by itself with
a capacitor or track the output of another supply. When the
device is configured to soft start by itself, a capacitor
should be connected to the TRACK/SS pin. The LTC3770
is put in a low quiescent current shutdown state (IQ <
30A) if the RUN pin voltage is below 1.5V. The TRACK/SS
pin is actively pulled to ground in this shutdown state.
Once the RUN pin voltage is above 1.5V, the LTC3770 is
powered up. A soft-start current of 1.4A then starts to
charge the soft-start capacitor C
SS
. Pin Z1 must be
grounded for soft-start operation. Note that soft-start is
achieved not by limiting the maximum output current of
the controller but by controlling the ramp rate of the output
voltage. Current foldback is disabled during this soft-start
phase. During the soft-start phase, the LTC3770 is ramp-
ing the reference voltage until it is 20% below the voltage
set by the V
REFIN
pin. The force continuous mode is also
disabled and PGOOD signal is forced low during this
phase. The total soft-start time can be calculated as:
t
SOFTSTART
= 0.8 V
REFIN
C
SS
/1.4A
When the device is configured to track another supply, the
feedback voltage of the other supply is duplicated by a
resistor divider and applied to the TRACK/SS pin. Pin Z1
should be tied to INTV
CC
to turn off the soft-start current
in this mode. Therefore, the voltage ramp rate on this pin
is determined by the ramp rate of the other supply output
voltage.
Output Voltage Tracking
The LTC3770 allows the user to program how its output
ramps up and down by means of the TRACK/SS pin.
Through this pin, the output can be set up to either
coincidentally or ratiometrically track with another supply's
output, as shown in Figure 7. In the following discussions,
V
OUT1
refers to the master LTC3770's output and V
OUT2
refers to the slave LTC3770's output.
To implement the coincident tracking in Figure 7a, connect
an additional resistive divider to V
OUT1
and connect its
midpoint to the TRACK/SS pin of the slave IC. The ratio of
this divider should be selected the same as that of the slave
IC's feedback divider shown in Figure 8. In this tracking
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Figure 7. Two Different Modes of Output Voltage Tracking
TIME
(7a) Coincident Tracking
V
OUT1
V
OUT2
OUTPUT VOLTAGE
TIME
3770 F07
(7b) Ratiometric Tracking
V
OUT1
V
OUT2
OUTPUT VOLTAGE
Figure 8. Setup for Coincident and Ratiometric Tracking
R3
R1
R4
R2
R3
V
OUT2
R4
(8a) Coincident Tracking Setup
TO
V
FB1
PIN
TO
TRACK/SS2
PIN
TO
V
FB2
PIN
V
OUT1
R1
R2
R3
V
OUT2
R4
3770 F08
(8b) Ratiometric Tracking Setup
TO
V
FB1
PIN
TO
TRACK/SS2
PIN
TO
V
FB2
PIN
V
OUT1
+
I
I
D1
TRACK/SS2
0.6V
V
FB2
D2
D3
3770 F09
EA2
Figure 9. Equivalent Input Circuit of Error Amplifier
mode, V
OUT1
must be set higher than V
OUT2
. To implement
the ratiometric tracking, the ratio of the divider should be
exactly the same as the master IC's feedback divider. Note
that the pin Z1 of the slave IC should be tied to INTV
CC
so
that the internal soft-start current is disabled in both
tracking modes or it will introduce a small error on the
tracking voltage depending on the absolute values of the
tracking resistive divider.
By selecting different resistors, the LTC3770 can achieve
different modes of tracking including the two in Figure 7.
So which mode should be programmed? While either
mode in Figure 7 satisfies most practical applications,
there do exist some tradeoffs. The ratiometric mode saves
a pair of resistors, but the coincident mode offers better
output regulation. This can be better understood with the
help of Figure 9. At the input stage of the slave IC's error
amplifier, two common anode diodes are used to clamp
the equivalent reference voltage and an additional diode is
used to match the shifted common mode voltage. The top
two current sources are of the same amplitude. In the
coincident mode, the TRACK/SS voltage is substantially
higher than 0.6V at steady state and effectively turns off
D1. D2 and D3 will therefore conduct the same current and
offer tight matching between V
FB2
and the internal preci-
sion 0.6V reference. In the ratiometric mode, however,
TRACK/SS equals 0.6V at steady state. D1 will divert part
of the bias current to make V
FB2
slightly lower than 0.6V.
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a finite amount
of output voltage deviation. Furthermore, when the master
IC's output experiences dynamic excursion (under load
transient, for example), the slave IC output will be affected
as well.
For better output regulation, use the coincident
tracking mode instead of ratiometric.
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LTC3770
3770f
Margining
Margining is a way to program the reference voltage to the
error amplifier to a voltage different from the default 0.6V.
Margining is useful for customers who want to stress their
systems by varying supply voltages during testing. The
reference voltage to the error amplifier is set according to
the following equation when the margining function is
enabled:
V
REFIN
= 0.6V (1.18V/R4) R3
Referring to the functional diagram, 0.6V is the buffered
system reference at the V
REFOUT
pin. R3 and R4 are
resistors used for programming the amount of margining.
V
REFIN
should be a voltage between 0.5V and 1V.
There are two logic control pins, MARGIN1 and MARGIN0,
to determine whether the margining function is enabled,
Margin up(+) or Margin down(). Table 1 summarizes the
configurations:
Table 1: Margining Function
MARGIN1
MARGIN0
Mode
LOW
LOW
No Margining
LOW
HIGH
Margin Up
HIGH
LOW
Margin Down
HIGH
HIGH
No Margining
The buffered reference at V
REFOUT
has the ability to source
a large amount of current. However, it can only sink a
maximum of 50A of current. To increase the sinking
capability of this reference, connect a resistor to ground at
this pin. One may also be tempted to connect a large
capacitor to this pin to filter out the noise. However, it is
recommended that no larger than 100pF of capacitance
should be connected to this pin.
Phase-Locked Loop and Frequency Synchronization
The LTC3770 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is 30% around the
center frequency f
O
. The center frequency is the operating
frequency discussed in the previous section. The LTC3770
incorporates a pulse detection circuit that will detect a
clock on the PLLIN pin. In turn, it will turn on the phase-
locked loop function. The pulse width of the clock has to
be greater than 400ns and the amplitude of the clock
should be greater than 2V.
During the start-up phase, phase-locked loop function is
disabled. When LTC3770 is not in synchronization mode,
PLLFLTR pin voltage is set to around 1.18V. Frequency
synchronization is accomplished by changing the internal
on-time current according to the voltage on the PLLFLTR
pin.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal pulses. This type of phase detector
will not lock up on input frequencies close to the harmon-
ics of the VCO center frequency. The PLL hold-in range,
f
H
, is equal to the capture range, f
C:
f
H
= f
C
= 0.3 f
O
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 10.
If the external frequency (f
PLLIN
) is greater than the oscil-
lator frequency f
O
, current is sourced continuously, pull-
ing up the PLLFLTR pin. When the external frequency is
less than f
O
, current is sunk continuously, pulling down
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLLFLTR
pin is adjusted until the phase and frequency of the
external and internal oscillators are identical. At this stable
DIGITAL
PHASE/
FREQUENCY
DETECTOR
PLLIN
PLLFLTR
2.4V
C
LP
3770 F10
R
LP
VCO
Figure 10. Phase-Locked Loop Block Diagram
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LTC3770
3770f
operating point the phase comparator output is open and
the filter capacitor C
LP
holds the voltage. The LTC3770
PLLIN pin must be driven from a low impedance source
such as a logic gate located close to the pin.
The loop filter components (C
LP
, R
LP
) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
=10k and C
LP
is 0.01F to
0.1F.
Dead Time Control
To further optimize the efficiency, the LTC3770 gives
users some control over the dead time of the Top gate low
and Bottom gate high transition. By applying a DC voltage
on the Z0 pin, the TG low BG high dead time can be
programmed. Because the dead time is a strong function
of the load current and the type of MOSFET used, users
need to be careful to optimize the dead time for their
particular applications. Figure 11 shows the relation be-
tween the TG Low BG High Dead time by varying the Z0
voltages. For an application using LTC3770 with load
current of 5A and IR7811W MOSFETs, the dead time could
be optimized. To make sure that there is no shoot-through
under all conditions, a dead time of 70ns is selected. This
corresponds to a DC voltage about 2.6V on Z0 pin. This
voltage can easily be generated with a resistor divider off
INTV
CC
.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3770 circuits:
1. DC I
2
R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same R
DS(ON)
, then the
resistance of one MOSFET can simply be summed with the
resistances of L and the board traces to obtain the DC I
2
R
loss. For example, if R
DS(ON)
= 0.01 and R
L
= 0.005, the
loss will range from 15mW to 1.5W as the output current
varies from 1A to 10A.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET
capacitance, among other factors. The loss is significant
at input voltages above 20V and can be estimated from:
Transition Loss (1.7A
1
) V
IN
2
I
OUT
C
RSS
f
3. INTV
CC
current. This is the sum of the MOSFET driver
and control currents.
4. C
IN
loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I
2
R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including C
OUT
ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the
input current is the best indicator of changes in efficiency.
Z0 VOLTAGE (V)
0
TDEAD TIME (ns)
60
100
120
140
5
3770 F11
20
80
160
40
20
0
1
2
4
3
180
I
OUT
= 5A
IRT811W FETs
Figure 11. TG Low BG High Dead Time vs Z0 Voltage
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LTC3770
3770f
If you make a change and the input current decreases, then
the efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to I
LOAD
(ESR), where ESR is the effective series
resistance of C
OUT
. I
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used by
the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I
TH
pin external components shown in Figure 12
will provide adequate compensation for most applica-
tions. For a detailed explanation of switching control loop
theory see Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: V
IN
= 5V to 28V (15V nominal), V
OUT
= 2.5V
5%, I
OUT(MAX)
= 10A, f = 450kHz. First, calculate the
timing resistor with V
ON
= V
OUT
:
R
V
V
kHz
pF
k
ON
=
(
)(
)(
)
=
2 5
3 2 5
450
10
74
.
.
and choose the inductor for about 40% ripple current at
the maximum V
IN
:
L
V
kHz
A
V
V
H
=
(
)( )(
)
-
=
2 5
450
0 4 10
1
2 5
28
1 3
.
.
.
.
Selecting a standard value of 1.8H results in a maximum
ripple current of:
=
(
)
(
)
=
I
V
kHz
H
V
V
A
L
2 5
450
1 8
1
2 5
28
2 8
.
.
.
.
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (R
DS(ON)
= 0.0083 (NOM) 0.010 (MAX),
JA
= 40C/W) yields a nominal sense voltage of:
V
SNS(NOM)
= (10A)(1.3)(0.0083) = 108mV
Tying V
RNG
to 1.1V will set the current sense voltage range
for a nominal value of 110mV with current limit occurring
at 146mV. To check if the current limit is acceptable,
assume a junction temperature of about 80C above a
70C ambient with
150C
= 1.5:
I
mV
A
A
LIMIT
( )
(
)
+
(
)
=
146
1 5 0 010
1
2
2 8
11
.
.
.
and double check the assumed T
J
in the MOSFET:
P
V
V
V
A
W
BOT
=
(
) ( )
(
)
=
28
2 5
28
11
1 5 0 010
1 65
2
.
.
.
.
T
J
= 70C + (1.65W)(40C/W) = 136C
Because the top MOSFET is on for such a short time, an
Si4884 R
DS(ON)(MAX)
= 0.0165, C
RSS
= 100pF,
JA
=
40C/W will be sufficient. Checking its power dissipation
at current limit with
100C
= 1.4:
P
V
V
A
V
A
pF
kHz
W
W
W
TOP
=
(
) ( )
(
)
+
( )(
) (
)(
)(
)
=
+
=
2 5
28
11
1 4 0 0165
1 7 28
11
100
250
0 25
0 37
0 62
2
2
.
.
.
.
.
.
.
T
J
= 70C + (0.62W)(40C/W) = 95C
The junction temperature will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking on the board will be necessary in
this circuit.
C
IN
is chosen for an RMS current rating of about 3A at
85C. The output capacitors are chosen for a low ESR of
0.013 to minimize output voltage changes due to induc-
tor ripple current and load steps. The ripple voltage will be
only:
V
OUT(RIPPLE)
= I
L(MAX)
(ESR)
= (2.8A) (0.013) = 36mV
However, a 0A to 10A load step will cause an output
change of up to:
V
OUT(STEP)
= I
LOAD
(ESR) = (10A) (0.013) = 130mV
An optional 22F ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 12.
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LTC3770
3770f
To set a 25% margining, select the resistors R3, R4 such
that
V
REFIN
= 0.6 25% 0.6
or
1 18
3
4
25
0 6
.
% .
R
R
=
R4 8R3
Choose R3 to be 10k, R4 to be 82k for this application.
PC Board Layout Checklist
When laying out a PC board follow one of two suggested
approaches. The simple PC board layout requires a dedi-
cated ground plane layer. Also, for higher currents, it is
recommended to use a multilayer board to help with heat
sinking power components.
The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
Place C
IN
, C
OUT
, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components on
the bottom side of the board.
Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3770.
Use several bigger vias for power components.
Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
Use planes for V
IN
and V
OUT
to maintain good voltage
filtering and to keep power losses low.
Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power component. You can connect the copper areas to
any DC net (V
IN
, V
OUT
, GND or to any other DC rail in
your system).
Figure 12. Design Example: 2.5V/10A at 450kHz
3770 F12
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RUN
V
ON
PGOOD
V
RNG
V
FB
I
TH
SGND
MARGIN1
MARGIN0
I
ON
V
REFIN
V
REFOUT
MPGM
TRACK/SS
RUN
FCB
Z0
BOOST
TG
SW
PGND
BG
INTV
CC
Z1
Z2
Z
VIN
V
IN
PLLIN
PLLFLTR
INTV
CC
5V
LTC3770EG
L1: SUMIDA CEP125-1R8MC-H
C
OUT
: CORNELL DUBILIER ESRE181E04B
C
IN
: UNITED CHEMICON THCR60E1H106ZT
R6
11k
R5
39k
R
C
20k
R3
10k
R2
95.3k
R
ON
75k
R4
82k
R
PG
100k
CC1
500pF
CC2
100pF
C
SS
0.1F
CV
CC
10F
CV
IN
0.1F
DB
CMDSH-3
D1
B340A
+
C
OUT3
23F
x5R
x2
C
OUT1-2
180F
4V
x2
V
OUT
2.5V
10A
V
IN
5V TO 28V
+
C
IN
10F
50V
x3
CB
0.22F
M1
Si4884
L1
1.8H
M2
Si4874
+
R1
30.1k
R8
51k
R7
47k
APPLICATIO S I FOR ATIO
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LTC3770
3770f
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PACKAGE DESCRIPTIO
G Package
28-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
G28 SSOP 0204
0.09 0.25
(.0035 .010)
0 8
0.55 0.95
(.022 .037)
5.00 5.60**
(.197 .221)
7.40 8.20
(.291 .323)
1
2 3
4
5
6 7 8
9 10 11 12
14
13
9.90 10.50*
(.390 .413)
25
26
22 21 20 19 18 17 16 15
23
24
27
28
2.0
(.079)
MAX
0.05
(.002)
MIN
0.65
(.0256)
BSC
0.22 0.38
(.009 .015)
TYP
MILLIMETERS
(INCHES)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
*
**
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
0.42 0.03
0.65 BSC
5.3 5.7
7.8 8.2
RECOMMENDED SOLDER PAD LAYOUT
1.25 0.12
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller.
Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
source of M2.
Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
Connect the input capacitor(s) C
IN
close to the power
MOSFETs. This capacitor carries the MOSFET AC
current.
Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
Connect the INTV
CC
decoupling capacitor C
VCC
closely
to the INTV
CC
and PGND pins.
Connect the top driver boost capacitor C
B
closely to the
BOOST and SW pins.
Connect the V
IN
pin decoupling capacitor C
F
closely to
the V
IN
and PGND pins.
APPLICATIO S I FOR ATIO
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3770f
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PACKAGE DESCRIPTIO
UH Package
32-Lead Plastic QFN (5mm 5mm)
(Reference LTC DWG # 05-08-1693)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
TYPICAL APPLICATIO
1.8V/5A at 450kHz with Tracking
INTV
CC
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
PLLFLTR PLLIN V
IN
V
INSNS
ZV
IN
LTC3770EUH
3770 TA02a
PGOOD V
ON
RUN FCB
FCB
V
REFOUT
MPGM TRACK/SS
Z0 BOOST TG
SW
SENSE+
SENSE
PGND
BG
DRV
CC
INTV
CC
Z2
Z1
V
RNG
V
FB
I
TH
SGND
R1
30.1k
R2
60.4k
CC1
1000pF
MARGIN1
V
REFIN
I
ON
MARGIN0
L1: BI TECH 1.8H HM65-H1R8-TB
M1, M2: PHILIPS PH3230
C
IN
: TDK C4532X5R1H685M
C
OUT
: PANASONIC EEFUE0G181R
MARGIN1
RUN
TRACK/SS
PGOOD
MARGIN0
R
ON
75k
R5
10k
R
C
10k
R6
200k
R
RUN
51k
R
PG
100k
CC2
100pF
C
F
220pF
V
CC
5V
M1
PH3230
CV
CC
10F
DB
CMDSH-3
D1
B340A
C
IN
6.8F
50V
x3
V
OUT
1.8V
5A
V
IN
4V TO 28V
CB
0.22F
M2
PH3230
+
L1
1.8H
C
OUT3
22F
X5R
x2
C
OUT
180F
4V
x2
+
R8
51k
R7
47k
1000pF
5.00 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 0.10
0.23 TYP
(4 SIDES)
31
1
2
32
BOTTOM VIEW--EXPOSED PAD
3.45 0.10
(4-SIDES)
0.75 0.05
R = 0.115
TYP
0.25 0.05
(UH) QFN 0603
0.50 BSC
0.200 REF
0.00 0.05
0.70 0.05
3.45 0.05
(4 SIDES)
4.10 0.05
5.50 0.05
0.25 0.05
PACKAGE
OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
24
LTC3770
3770f
PART NUMBER
DESCRIPTION
COMMENTS
LTC1622
550kHz Step-Down Controller
8-Pin MSOP; Synchronizable; Soft-Start; Current Mode
LTC1625/LTC1775
No R
SENSE
Current Mode Synchronous Step-Down Controller
97% Efficiency; No Sense Resistor; 16-Pin SSOP
LTC1628/LTC3728
Dual, 2-Phase Synchronous Step-Down Controller
Power Good Output; Minimum Input/Output Capacitors;
3.5V V
IN
36V
LTC1735
High Efficiency, Synchronous Step-Down Controller
Burst Mode
Operation; 16-Pin Narrow SSOP;
3.5V V
IN
36V
LTC1736
High Efficiency, Synchronous Step-Down Controller with 5-Bit VID
Mobile VID; 0.925V V
OUT
2V; 3.5V V
IN
36V
LTC1772
SOT-23 Step-Down Controller
Current Mode; 550kHz; Very Small Solution Size
LTC1773
Synchronous Step-Down Controller
Up to 95% Efficiency, 550kHz, 2.65V V
IN
8.5V,
0.8V V
OUT
V
IN
, Synchronizable to 750kHz
LTC1778
Wide Range, No R
SENSE
Synchronous Step-Down Controller
GN16-Pin, 0.8V
FB
Reference
LTC1876
2-Phase, Dual Synchronous Step-Down Controller with
3.5V V
IN
36V, Power Good Output, 300kHz Operation
Step-Up Regulator
LTC3708
Dual, 2-Phase, No R
SENSE
Synchronous Step-Down Controller with
Fast Transient Response Reduces C
OUT
; 4V V
IN
36V,
Output Tracking
0.6V V
OUT
6V; 2-Phase Operation Reduces C
IN
LTC3713
Low V
IN
High Current Synchronous Step-Down Controller
1.5V V
IN
36V, 0.8V V
OUT
(0.9)V
IN
, I
OUT
Up to 20A
LTC3731
3-Phase Synchronous Step-Down Controller
600kHz; Up to 60A Output
LTC3778
Low V
OUT
, No R
SENSE
Synchronous Step-Down Controller
0.6V V
OUT
(0.9)V
IN
, 4V V
IN
36V, I
OUT
Up to 20A
Burst Mode is a registered trademark of Linear Technology Corporation.
LINEAR TECHNOLOGY CORPORATION 2004
LT/TP 1104 1K PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
RELATED PARTS
U
TYPICAL APPLICATIO
Typical Application 2.5V/10A Synchronized at 450kHz
R8
51k
R7
47k
INTV
CC
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
PLLFLTR PLLIN
PLLIN
V
IN
V
INSNS
ZV
IN
LTC3770EUH
3770 TA02b
PGOOD V
ON
RUN FCB
FCB
V
REFOUT
MPGM TRACK/SS
Z0 BOOST TG
SW
SENSE+
SENSE
PGND
BG
DRV
CC
INTV
CC
Z2
Z1
V
RNG
V
FB
I
TH
SGND
R1
30.1k
R2
95.3k
CC1
1000pF
MARGIN1
V
REFIN
I
ON
MARGIN0
MARGIN1
RUN
PGOOD
MARGIN0
R
ON
75k
R5
10k
R
C
10k
R6
82k
R
PL
10k
RV
IN
10
R
RUN
51k
R4
39k
R3
11k
R
PG
100k
CC2
100pF
C
F
220pF
CV
IN
0.01F
0.1F
C
SS
0.1F
M1
PH3230
CV
CC
10F
DB
CMDSH-3
D1
B340A
C
IN
10F
50V
x3
V
OUT
2.5V
10A
V
IN
5V TO 28V
CB
0.22F
M2
PH3230
L1
1.8H
C
OUT3
22F
X5R
x2
C
OUT
180F
4V
x2
+
C
P
1000pF
C
PL
0.01
F
L1: BI TECH 1.8H HM65-H1R8-TB
M1, M2: PHILIPS PH3230
C
IN
: TDK C4532X5R1H685M
C
OUT
: PANASONIC EEFUE0G181R
1000pF
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