LTC3806

3806f

Synchronous

Flyback DC/DC Controller

High Efficiency at Full Load

Better Cross Regulation Than Nonsynchronous
Converters (Multiple Outputs)

Soft-Start Minimizes Inrush Current

Current Mode Control Provides Excellent
Transient Response

High Maximum Duty Cycle: 89% Typical

2% Programmable Undervoltage Lockout Threshold

1% Internal Voltage Reference

Micropower Start-Up

Constant Frequency Operation (Never Audible)

3mm

4mm 12-Pin DFN Package

48V Telecom Supplies

12V/42V Automotive

24V Industrial

VoIP Phone

Power Over Ethernet

The LTC

3806 is a current mode synchronous flyback

controller that drives N-channel power MOSFETs and
requires very few external components. It is intended for
medium power applications where multiple outputs are
required. Synchronous rectification provides higher effi-
ciency and improved output cross regulation than
nonsynchronous converters.

The IC contains all the necessary control circuitry includ-
ing a 250kHz oscillator, precision undervoltage lockout
circuit with hysteresis, gate drivers for primary and syn-
chronous switches, current mode control circuitry and
soft-start circuitry.

Programmable soft-start reduces inrush currents. This
makes it easier to design compliant Power Over Ethernet
supplies.

Low start-up current reduces power dissipation in the
start-up resistor and reduces the size of the external start-
up capacitor.

The LTC3806 is available in a 12-pin, exposed pad DFN
package.

, LTC and LT are registered trademarks of Linear Technology Corporation.

SENSE

GND

RUN

INTV

LTC3806

C3
4.7

C4
0.47

C5
470

C6
470

3806 F01

OUT1

3.3V
3A

OUT2

2.5V
3A

C2
1nF

C7
4.7

C1
100

R4
3.4k

R5
0.056

12.4k

21k

R3
26.7k

R8
100

604k

51k

36V TO 72V

Figure 1. Multiple Output Flyback Converter for Telecom

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

LTC3806

3806f

SENSE

GND

RUN

INTV

TOP VIEW

DE12 PACKAGE

12-LEAD (4mm

3mm) PLASTIC DFN

ORDER PART

NUMBER

(Note 1)

Voltage ............................................................. 25V

INTV

Voltage ......................................................... 8V

INTV

Output Current ........................................ 50mA

G1, G2 Voltages ....................... 0.3V to V

INTVCC

+ 0.3V

, FB, SS Voltages ................................. 0.3V to 2.7V

RUN Voltage ............................................... 0.3V to 7V
SENSE Pin Voltage ..................................... 0.3V to 8V
Operating Ambient Temperature Range
(Note 2) .................................................. 40

C to 85

Junction Temperature (Note 3) ............................ 125

Storage Temperature Range ................. 65

C to 125

LTC3806EDE

JMAX

= 125

= 34

C/W

EXPOSED PAD (PIN 13) IS GND

MUST BE SOLDERED TO PCB

ABSOLUTE

AXI

RATINGS

PACKAGE/ORDER I

FOR

ATIO

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are T

= 25

C. V

= 10V, V

RUN

= 1.5V, unless otherwise specified.

ELECTRICAL CHARACTERISTICS

Consult LTC Marketing for parts specified with wider operating temperature ranges.

DE PART MARKING

3806

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

IN(MIN)

Minimum Input Voltage

(Note 4)

Input Voltage Supply Current

(Note 5)

Quiescent

1000

Shutdown Mode

RUN

= 0V

Start-Up Mode

RUN

> 1.255V, V

< 7V

140

RUN

Rising RUN Input Threshold Voltage

= 20V

1.205

1.230

1.255

1.181

1.279

RUN

Falling RUN Input Threshold Voltage

= 20V

1.116

1.139

1.162

1.093

1.185

RUN(HYST)

RUN Pin Input Threshold Hysteresis

= 20V

137

RUN

RUN Input Current

Feedback Voltage

ITH

= 0.75V (Note 6)

1.218

1.230

1.242

1.212

1.248

Feedback Pin Input Current

ITH

= 0.75V (Note 6)

100

Line Regulation

10V

20V

0.01

%/V

ITH

Load Regulation

= 0.55V to 0.95V (Note 6)

0.1

Error Amplifier Transconductance

Pin Load =

A (Note 6)

650

Mho

SENSE(MAX)

Maximum Current Sense Input Threshold

110

150

190

SENSE(ON)

SENSE Pin Current (G1 High)

SENSE

= 0V

SENSE(OFF)

SENSE Pin Current (G1 Low)

SENSE

= 1V

0.1

SS Pin Source Current

= 1.5V

Oscillator

OSC

Oscillator Frequency

210

250

290

kHz

DC(MAX)

Maximum Duty Cycle

LTC3806

3806f

The

denotes specifications which apply over the full operating

temperature range, otherwise specifications are T

= 25

C. V

= 10V, V

RUN

= 1.5V, unless otherwise specified.

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.

Note 2: The LTC3806E is guaranteed to meet performance specifications
from 0

C to 70

C. Specifications over the 40

C to 85

C operating

temperature range are assured by design, characterization and correlation
with statistical process controls.

Note 3: T

is calculated from the ambient temperature T

and power

dissipation P

according to the following formula:

= T

+ (P

· 34

C/W)

Note 4: The minimum operating voltage is allowed once operation begins.
To begin operation, V

must be above the rising undervoltage lockout

threshold with V

RUN

above the rising RUN input threshold.

Note 5: The dynamic input supply current is higher due to power MOSFET
gate charging (Q

· f

OSC

). See Applications Information.

Note 6: The LTC3806 is tested in a feedback loop which servos V

to the

reference voltage with the I

pin forced to a voltage between 0V and 1.4V

(the no load to full load operating voltage range for the I

pin is 0.3V to

1.23V).

TYPICAL PERFOR A CE CHARACTERISTICS

FB Voltage vs Temperature

FB Voltage Line Regulation

FB Pin Current vs Temperature

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Regulator

INTVCC

INTV

Regulator Output Voltage

= 10V

6.9

7.8

INTV

Regulator Line Regulation

10V

20V

100

LDO(LOAD)

INTV

Load Regulation

INTVCC

20mA

UVL

Rising V

Threshold Voltage

UVL

Falling V

Threshold Voltage

7.5

8.5

Gate Drivers

Gate Driver 1 Output Rise Time

= 3300pF

100

Gate Driver 1 Output Fall Time

= 3300pF

100

Gate Driver 2 Output Rise Time

= 4700pF

100

Gate Driver 2 Output Fall Time

= 4700pF

100

DEAD

Gate Driver Dead Time

= 3300pF, C

= 4700pF

100

TEMPERATURE (

FB VOLTAGE (V)

1.2400

1.2350

1.2300

1.2250

1.2200

1.2150

3806 G01

(V)

FB VOLTAGE (V)

3806 G02

14 15

1.2310

1.2305

1.2300

1.2295

1.2290

= 25

TEMPERATURE (

FB PIN CURRENT (nA)

3806 G03

LTC3806

3806f

TYPICAL PERFOR A CE CHARACTERISTICS

Shutdown Mode I

vs V

Shutdown Mode I

vs Temperature

Soft-Start Current vs Temperature

G1 Rise and Fall Time vs C

G2 Rise and Fall Time vs C

RUN Thresholds vs Temperature

Frequency vs Temperature

(V)

SHUTDOWN MODE, I

(

3806 G04

= 25

TEMPERATURE (

SHUTDOWN MODE, I

(

3806 G05

TEMPERATURE (

5.0

SOFT-START CURRENT (

5.5

6.0

6.5

7.0

3806 G06

(pF)

TIME (ns)

150

200

250

16000

3806 G07

100

4000

8000

12000

20000

= 25

(pF)

TIME (ns)

100

120

16000

3806 G08

4000

8000

12000

20000

= 25

Maximum Sense Threshold
vs Temperature

TEMPERATURE (

1.10

RUN THRESHOLDS (V)

1.12

1.14

1.16

1.18

1.20

1.22

TRIP

3806 G10

RELEASE

TEMPERATURE (

FREQUENCY (kHz)

250

255

3806 G11

245

240

260

TEMPERATURE (

MAX SENSE THRESHOLD (mV)

151

153

155

3806 G12

149

147

150

152

154

148

146

145

LTC3806

3806f

TYPICAL PERFOR A CE CHARACTERISTICS

SENSE Pin Current
vs Temperature

INTV

Load Regulation

INTV

Line Regulation

INTV

Dropout Voltage

vs Current, Temperature

TEMPERATURE (

SENSE PIN CURRENT (

31.0

31.5

3806 G13

30.5

30.0

32.0

INTV

LOAD (mA)

6.990

INTV

VOLTAGE (V)

6.995

7.000

7.005

7.010

7.015

7.020

3806 G14

= 25

(V)

6.990

INTV

VOLTAGE (V)

6.995

7.000

7.005

7.010

7.015

7.020

3806 G15

INTV

LOAD (mA)

1.9

DROPOUT VOLTAGE (V)

2.0

2.2

2.3

2.4

2.8

3806 G16

2.1

2.5

2.6

2.7

= 40

= 25

= 55

= 85

= 0

% OF MAXIMUM OUTPUT POWER

EFFICIENCY (%)

3806 G17

100

FIGURE 8 CIRCUIT

Efficiency vs Output Power

LTC3806

3806f

PI FU CTIO S

RUN (Pin 1): The RUN pin provides the user with an
accurate means for sensing the input voltage and pro-
gramming the start-up threshold for the converter. The
falling RUN pin threshold is nominally 1.14V and the
comparator has 91mV of hysteresis for noise immunity.
When the RUN pin is below this input threshold, the gate
drive outputs G1 and G2 are held low. The absolute
maximum rating for the voltage on this pin is 7V.

(Pin 2): Error Amplifier Compensation Pin. The current

comparator input threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 1.4V.

FB (Pin 3): Receives the feedback voltage from the exter-
nal resistor divider across the main output. Nominal
voltage for this pin in regulation is 1.230V.

NC (Pins 4, 11): Do Not Connect.

(Pin 5): Main Supply Pin. Must be closely decoupled

to ground.

INTV

(Pin 6): The Internal 6.9V Regulator Output. The

gate drivers and control circuits are powered from this
voltage. Decouple this pin locally to the IC ground with a
minimum 4.7

F low ESR ceramic capacitor.

GND (Pins 7, 13): Ground Pins. Exposed pad must be tied
to electrical ground.

G2 (Pin 8): Secondary-Side Gate Driver Output. This pin
drives the gates of all of the synchronous rectifiers.

G1 (Pin 9): Primary-Side Gate Driver Output.

SS (Pin 10): Soft-Start. A capacitor between this pin and
ground sets the rate at which the current comparator input
threshold may increase when the IC is initially enabled.
Increasing the size of the capacitor slows down the ramp
rate and reduces the inrush current.

SENSE (Pin 12): Current Sense Input for the Control Loop.
Connect this pin to the current sense resistor in the source
of the primary side power MOSFET. Internal leading edge
blanking is provided.

LTC3806

3806f

OPERATIO

Main Control Loop

The LTC3806 is a constant frequency, current mode
flyback converter controller. A secondary-side gate driver
capable of driving several MOSFET synchronous rectifiers
is provided. To insure best cross regulation, DC/DC con-
verters using this controller operate in forced continuous
conduction (current is always flowing in either the primary
or secondary winding(s) of the transformer.)

For circuit operation, please refer to the Block Diagram of
the IC and Figure 1. In normal operation, the primary-side
power MOSFET is turned on when the oscillator sets the
PWM latch and is turned off when the current comparator
C1 resets the latch. V

OUT1

is divided down and compared

to an internal 1.230V reference by error amplifier EA,
which outputs an error signal at the I

pin. The voltage of

the I

pin sets the current comparator C1 input threshold.

When the load current on either output increases, a fall in
the FB voltage relative to the reference voltage causes the
I

pin to rise increasing the primary-side peak current

thereby maintaining regulation. Regulation of V

OUT2

indirect, occurring via transformer action.

The RUN pin and undervoltage comparators control
whether the IC is enabled or is in a low current state. With

the RUN pin below 1.139V, the chip is off and the input
supply current is typically only 50

A. If the RUN pin is

above 1.230V, most internal circuitry remains off until V

exceeds the undervoltage comparator UV2 threshold. This
reduces start-up current to approximately 80

A allowing

smaller values for C1 and larger values for R1 to be used.

The undervoltage comparator UV1 keeps G1 and G2 low
until INTV

voltage is > 4.7V to insure that gate drivers

will switch the external power MOSFETs properly.

Prior to normal operation, soft-start pin SS is low clamp-
ing the output of the V-to-I converter to a low value causing
current comparator C1 to trip at a low threshold. Once
operation begins, the SS pin ramps up causing the clamp
voltage to rise as well. This allows progressively higher
trip points on comparator C1 and progressively higher
peak currents to be supplied to the primary of the trans-
former. Soft-start is completed when the voltage on the SS
pin exceeds the voltage on the I

pin.

The nominal operating frequency of the LTC3806 is 250kHz.
Since forced continuous operation is used, the noise
spectrum over all operating conditions is well controlled
with virtually all noise occurring at the operating frequency
and its harmonics.

LTC3806

3806f

APPLICATIO S I FOR ATIO

INTV

Regulator Bypassing and Operation

An internal voltage regulator produces the 6.9V supply
that powers the gate drivers and logic circuitry within the
LTC3806. The INTV

regulator can supply up to 50mA

and must be bypassed to ground immediately adjacent to
the IC pins with a minimum of 4.7

F ceramic capacitor.

Good bypassing is necessary to supply the high transient
currents required by the MOSFET gate drivers.

In an actual application, most of the IC supply current is
used to drive the gate capacitances of the power MOSFETs.
As a result, high input voltage applications with large
power MOSFETs can cause the LTC3806 to exceed its
maximum junction temperature rating. The junction tem-
perature can be estimated using the following equations:

Q(TOT)

= I

+ f · Q

= V

+ f ·

)

= T

+ P

TH(JA)

where

is the static supply current

is the total gate charge of all external power MOSFETs

is the power dissipated in the IC

f is the switching frequency, nominally 250kHz

TH(JA)

is the package thermal resistance, junction to

ambient, nominally 34

C/W for the 12-pin DFN package

As an example, consider a 2-output power supply that
uses an Si7450DP primary-side power MOSFET, that has
a maximum total gate charge of 42nC and two Si4840DY
power MOSFETs (one for each output), each of which has
28nC maximum total gate charge.

The total gate charge is:

42nC + 2 · 28nC = 98nC

The total supply current is:

Q(TOT)

= 2000

A + 98nC · 250kHz = 27mA

This demonstrates how significant the gate charge current
can be when compared to static quiescent current in the
IC.

If V

is set to 10V, the power dissipation is:

= 10 · 27mA = 270mW

and the junction temperature (assuming 70 degree ambi-
ent temperature) is:

= 70

C + 270mW · 120

C/W = 102.4

To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked when
operating at high V

. If junction temperature is too high,

using a separate transformer winding to lower V

may be

tried. Prior to adding an additional transformer winding
(which raises transformer cost), be sure to check with
power MOSFET manufacturers for their newest low Q

low R

DS(ON)

devices. Power MOSFET manufacturing tech-

nologies are continually improving, with newer and better
performance devices being introduced almost yearly.

Output Voltage Programming

This IC will generally be used in DC/DC converters with
multiple outputs. The output voltage of the master output
(V

OUT1

) is set by a resistor divider according to the

following formula:

R
R

OUT1

1 230

6
7

The external resistor divider is connected as shown in
Figure 1. The resistors R6 and R7 are typically chosen so
that the error caused by the current flowing into the FB pin
during normal operation is less than 1% (this translates to
a maximum value of R7 of about 120k).

The nominal slave output (V

OUT2

) voltage is set according

to the following formula:

OUT2

= V

OUT1

· N21

where N21 is the turns ratio of the transformer windings
between V

OUT2

and V

OUT1

If additional slave outputs are added their voltage is
determined by the equation:

OUTN

= V

OUT1

· N

where N

is the turns ratio of the transformer windings

between V

OUTN

and V

OUT1

LTC3806

3806f

APPLICATIO S I FOR ATIO

Cross regulation and tracking between the master and slave
outputs are impacted by transformer and secondary-side
power MOSFET selection. Select a power MOSFET with
low on resistance. In addition, a transformer with low
winding resistances and highest coupling coefficient will
have better cross regulation and tracking.

Composite Feedback

In applications where accuracy is important on more than
one output, composite feedback may be used. This sacri-
fices some of the accuracy of one output for improved
accuracy on the other output(s). Figure 2 shows how
composite feedback can be applied to two outputs.

Select a value for R7 less than or equal to 120k. Now
choose the fraction K of the total feedback taken from
V

OUT1

. The higher the fraction used, the tighter V

OUT1

controlled, but the poorer V

OUT2

is controlled (since it

contributes less to the total feedback). The values for R6A
and R6B can now be calculated:

R A

R B

OUT

REF

OUT

REF

This technique can easily be extended to more outputs if
needed.

Programming Turn-On and Turn-Off Thresholds
with the RUN Pin

The LTC3806 leaves a comparator detection circuit and
the voltage reference active even when the device is shut
down (Figure 3). This allows users to accurately program
an input voltage at which the converter will turn on and off.

3806 F02

R6B

R6A

OUT1

OUT2

Figure 2. Composite Feedback

RUN

COMPARATOR

RUN

INPUT

SUPPLY

OPTIONAL

FILTER

CAPACITOR

GND

3806 F03a

BIAS AND

START-UP

CONTROL

1.230V

REFERENCE

RUN

COMPARATOR

1.230V

3806 F03b

RUN

EXTERNAL

LOGIC CONTROL

RUN

COMPARATOR

RUN

INPUT

SUPPLY

GND

1.230V

3806 F03c

Figure 3a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin

Figure 3b. On/Off Control Using External Logic

Figure 3c. External Pull-Up Resistor On
RUN Pin for "Always On" Operation

LTC3806

3806f

The rising threshold voltage on the RUN pin is equal to the
internal reference voltage of 1.230V. The comparator has
91mV of hysteresis to increase noise immunity.

The turn-on and turn-off input voltage thresholds are
programmed using a resistor divider according to the
following formulas:

IN OFF

IN ON

(

)

(

)

1 139

1 230

The resistor R1 is typically chosen to be less than 1M. For
applications where the RUN pin is only to be used as a
logic input, the user should be aware of the 7V Absolute
Maximum Rating for this pin! The RUN pin can be
connected to the input voltage through an external 1M
resistor, as shown in Figure 3c, for "always on" operation.

Application Circuits

A basic LTC3806 application circuit is shown in Figure 1.
External component selection is driven by the character-
istics of the load and the input supply.

Duty Cycle Considerations

Current and voltage stress on the power switch and
synchronous rectifiers, input and output capacitor RMS
currents and transformer utilization (size vs power) are
impacted by duty factor. Unfortunately duty factor cannot
be adjusted to simultaneously optimize all of these re-
quirements. In general, avoid extreme duty factors since
this severely impacts the current stress on most of the
components. A reasonable target for duty factor is 50% at
nominal input voltage. Using this rule of thumb, calculate
the ideal transformer turns ratio:

IDEAL

OUT

APPLICATIO S I FOR ATIO

For a 50% duty factor, this reduces to:

IDEAL

OUT

If N

IDEAL

is integer, use this for your turns ratio. If not, find

a ratio of small integers that comes close to N

IDEAL

. If these

conditions are met, bifilar winding techniques can be used
that will improve coupling coefficient. Cross regulation
will be better and primary-side snubbing may be reduced
or eliminated.

The selected turns ratio doesn't have to be perfectly equal
to N

IDEAL

because a flyback converter's output voltage is

not set through transformer action. Instead, the trans-
former stores energy when the primary-side switch turns
on and transfers this energy to the output(s) by flyback
action when the primary-side switch turns off.

Cross regulation may be improved by using a target duty
factor which is less than 50%. This improves cross
regulation because the secondary-side MOSFETs (syn-
chronous rectifiers) will be on a larger percentage of the
time (thereby increasing the average coupling between the
outputs). Duty factor is reduced by proportionately in-
creasing all turns ratios.

Reduced duty factor has the following effect on MOSFET
stresses:

MOSFET

LOCATION

CURRENT STRESS

VOLTAGE STRESS

Primary

Increased

Reduced

Secondary

Reduced

Increased

The duty factor with the selected turns ratio will equal:

N V

OUT

(

)

While the output(s)/input turns ratio are not critical,

the

turns ratio between outputs are critical and affect the
accuracy of the slave output voltages.

LTC3806

3806f

APPLICATIO S I FOR ATIO

For example, assume we need a regulator that operates
with a nominal 48V input to produce one 3.3V output and
one 5V output. The ideal turns ratio for the 3.3V (master)
output is:

IDEAL1

3 3

0 06875

We select a turns ratio of 1/15 or N1 = 0.066...

For the 5V output, the ideal turns ratio is:

IDEAL2

3 3

0 1010

...

If we choose:

N2 =

and we assume OUT1 is exact, the voltage on slave
output 2 is:

OUT2

3 3

3 3 1 5

4 95

. ·

. · .

This does not include any other errors, so make sure that
the error in V

OUT2

is only a fraction of what your specifica-

tion allows. When dealing with large numbers of outputs
trial and error is usually required to get reasonable turns
ratios on all outputs while keeping the errors (due to
imperfect turns ratios) low.

For the selected turns ratios, the duty factor for this design
with 48V input would be:

N V

OUT

(

)

3 3

0 508

Input Power

The maximum input power is:

Eff

OUTK

where P

OUTK

is the maximum power supplied by output K

and Eff represents the efficiency of the converter.

Continuing the previous example, assume OUT1 delivers
3.3V at 2A and OUT2 delivers 4.95V at 0.5A. For a
conversion efficiency at maximum output power of 80%:

3 3

4 95

0 5

0 80

11 34

· .

Transformer Selection

The transformer primary inductance, L

, is selected based

on the percentage peak-to-peak ripple current (X) in the
transformer relative to its maximum value. In general, X
should range from 20% to 40% ripple current (i.e., X = 0.2
to 0.4). Higher values of ripple will increase conduction
losses, while lower values will require larger cores.

Ripple current and percentage ripple will be largest at
minimum duty factor D, in other words at the highest input
voltage. L

can be calculated from:

f X

IN MAX

MIN

MAX

(

)

where f is nominally 250kHz.

Continuing the example, allow 40% maximum ripple at a
maximum input voltage of 72V:

MIN

3 3

0 407

250000

0 4 11 34

757

· .

· . ·

Some common secondary turns ratios:

OUT

TURNS

2.5

3.3

5.0

1.8

3.3

1.8

2.5

3.3

5.0

LTC3806

3806f

For a minimum input voltage of 36V, the largest duty factor
is:

MAX

3 3

0 579

and the minimum percentage ripple is:

f L

kHz

MIN

MAX

0 579

250

757

11 34

20 2

· .

. %

Transformer Core Selection

Once L

is known, the type of transformer must be selected.

High efficiency converters generally cannot afford the core
loss found in low cost powdered iron cores, forcing the use
of more expensive ferrite cores. Actual core loss is inde-
pendent of core size for a fixed inductance, but is very
dependent on the inductance selected. As inductance in-
creases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore cop-
per losses will increase. Generally, there is a tradeoff be-
tween core losses and copper losses that needs to be
balanced. In addition, increased winding resistance will
degrade cross regulation.

Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can con-
centrate on copper losses and preventing saturation.
Ferrite core material saturates "hard," meaning that the
inductance collapses rapidly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequently, output voltage ripple. Do
not allow the core to saturate! The maximum peak
primary current occurs at minimum V

IN MIN

MAX

MIN

(

)

· 1

Current Sense Resistor Selection

The control circuit limits the maximum voltage drop
across the sense resistor to about 120mV (at low duty

cycle), and only about 70mV at a duty cycle of 92% due to
slope compensation. Use Figure 4 and D

MAX

to determine

the maximum allowable drop in the sense resistor. Using
this value calculate:

SENSE

DROP

APPLICATIO S I FOR ATIO

DUTY CYCLE

MAXIMUM CURRENT SENSE VOLTAGE (mV)

100

150

0.8

3806 F04

0.2

0.4

0.5

1.0

200

= 25

Figure 4. Maximum SENSE Threshold Voltage vs Duty Cycle

Capacitor Selection

In a flyback converter, the input and output current flows
in pulses placing severe demands on the input and output
filter capacitors. The input and output filter capacitors
should be selected based on RMS current ratings and
ripple voltage.

Select an input capacitor with a ripple current rating
greater than:

RMS

IN MIN

MAX

(

)

Continuing the example:

RMS

11 34

1 0 579

0 579

0 269

Low effective series resistance and inductance is also
important in the input capacitor since it affects the electro-
magnetic interference suppression. In some instances
high ESR can also produce stability problems because
flyback converters exhibit a negative input resistance

LTC3806

3806f

characteristic. Refer to Application Note 19 for more
information.

The output capacitor is sized to handle the ripple current
and to insure acceptable output voltage ripple. The output
capacitor should have a ripple current rating greater than:

RMS

OUT

MAX

This should be calculated for each output. For our ex-
ample, the OUT1 capacitor needs an RMS current rating
greater than:

RMS

0 579

1 0 579

2 35

The OUT2 capacitor RMS current rating is calculated in a
similar manner. The capacitor rating should be greater
than 586mA

RMS

. One final note, most capacitor manufac-

turers base their ripple current ratings on only 2000 hours
life. This makes it advisable to further derate the capacitor
or to choose a capacitor rated at a higher temperature than
required.

Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct compo-
nent for a given output ripple voltage. The effects of these
three parameters (ESR, ESL and bulk C) on the output
voltage ripple waveform are illustrated in Figure 5 for a
typical flyback converter.

The capacitance calculation begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging

For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the
ESR step and the charging/discharging

V. This percent-

age ripple will change, depending on the requirements of
the application, and the equations provided below can
easily be modified.

For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the
following equation:

ESR

COUT

OUT

MAX

OUT

(

)

0 01

For the bulk C component, which also contributes 1% to
the total ripple:

OUT

0 01

For many designs it is possible to choose a single capaci-
tor type that satisfies both the ESR and bulk C require-
ments for the design. In certain demanding applications,
however, the ripple voltage can be improved significantly
by connecting two or more types of capacitors in parallel.
For example, using a low ESR ceramic capacitor can
minimize the ESR step, while an electrolytic capacitor can
be used to supply the required bulk C.

APPLICATIO S I FOR ATIO

OUTPUT VOLTAGE

RIPPLE WAVEFORM

SECONDARY

CURRENT

PRIMARY

CURRENT

PRI

COUT

3806 F05

RINGING
DUE TO ESL

PRI

ESR

Figure 5. Typical Flyback Converter Waveforms (Single Output)

LTC3806

3806f

APPLICATIO S I FOR ATIO

Continuing our previous example the filter capacitor for
output 1 needs:

ESR

kHz

COUT

OUT

(

)

0 01 3 3

1 0 579

0 01 3 3

250

242

· .

To get an electrolytic capcitor with an ESR this low would
require C

OUT

much larger than 242

F. Combining a low

ESR ceramic capacitor in parallel with an electrolytic
capacitor provides better filtering at lower cost.

For output 2, the output capacitor needs an ESR less than
42m

and a bulk C greater than 40.4

F. This can be

achieved with a single high performance capacitor such as
a Sanyo OS-CON or equivalent.

Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform
should be verified on a dedicated PC board. Parasitic
inductance from poor layout can have a significant impact
on ripple. Refer to the layout section for details.

Power MOSFET Selection

Important selection criteria for the power MOSFETs in-
clude the "on" resistance R

DS(ON)

, input capacitance,

drain-to-source breakdown voltage (BV

DSS

) and maxi-

mum drain current (I

D(MAX)

Narrow the choices for power MOSFETs by first looking at
the maximum drain currents. For the primary-side power
MOSFET:

IN MIN

MAX

MIN

(

)

· 1

For each secondary-side power MOSFET:

OUT

MAX

MIN

From the remaining MOSFET choices, narrow the field
based on BV

DSS

. Select a primary-side power MOSFET

with a BV

DSS

greater than:

DSS

LKG

IN MAX

OUT MAX

(

)

(

)

where L

LKG

is the primary-side leakage inductance and C

is the primary-side capacitance (mostly from the C

OSS

the primary-side power MOSFET). A snubber may be
added to reduce the leakage inductance related spike. For
more information on snubber design, refer to Application
Note 19.

For each secondary-side power MOSFET, the BV

DSS

should

be greater than:

DSS

OUT

+ V

IN(MAX)

· N

Next, select a logic-level MOSFET with acceptable R

DS(ON)

at the nominal gate drive voltage (usually 6.9V--set by the
INTV

regulator).

Calculate the required RMS currents next. For the primary-
side power MOSFET:

RMSPRI

IN MIN

MAX

(

)

For each secondary-side power MOSFET:

RMSSEC

OUT

MAX

Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET operates at high V

, a term

for transition power loss must be included in order to get
an accurate fix on power dissipation. C

MILLER

is the most

critical parameter in determining the transition loss but is
not directly specified on MOSFET data sheets.

MILLER

can be calculated from the gate charge curve in-

cluded on most data sheets (Figure 6). The curve is gen-
erated by forcing a constant input current into the gate of
a common source, current source loaded stage and then
plotting the gate voltage versus time. The initial slope is the
result of the gate-to-source and the gate-to-drain capaci-
tance. The flat portion of the curve is the result of the Miller
(gate-to-drain) capacitance as the drain voltage drops. The
upper sloping line is due to the gate-to-drain accumulation
capacitance and the gate-to-source capacitance. The Miller

LTC3806

3806f

charge (the increase in coulombs on the horizontal axis
from a to b while the curve is flat) is specified for a given
V

, but can be adjusted for different V

voltages by

multiplying by the ratio of the application V

to the curve

specified V

values. To estimate the C

MILLER

term, take

the change in gate charge from points a and b on the
manufacturers data sheet and divide by the specified V

With C

MILLER

determined, calculate the primary-side power

MOSFET power dissipation:

DPRI

RMSPRI

DS ON

IN MAX

MIN

MILLER

INTVCC

( )

(

)

(

)

(

)

where R

is the GATE1 driver resistance (maximum is

approximately 6

), V

is the typical gate threshold volt-

age for the specified power MOSFET and f is the operating
frequency, typically 250kHz. The term (1 +

) is generally

given for a MOSFET in the form of a normalized R

DS(ON)

temperature curve, but

= 0.005/

C can be used as an

approximation for low voltage MOSFETs.

The secondary-side power MOSFETs typically operate at
substantially lower V

, so transition losses can be ne-

glected. The dissipation may be calculated using:

DSEC

= I

RMSSEC

· R

DS(ON)

(1 +

)

For a known power dissipation in the power MOSFETs, the
junction temperatures can be obtained from the equation:

= T

+ P

· R

TH(JA)

where T

is the ambient temperature and R

TH(JA)

is the

MOSFET thermal resistance from junction to ambient.

Compare T

against your initial estimate for T

and if

necessary, recompute

, power dissipations and T

. Iter-

ate as necessary.

Selecting the Compensation Network

Load step testing can be used to empirically determine
compensation. Application Note 25 provides information
on the technique. When the regulator has multiple out-
puts, compensation should be optimized for the master
output.

PC Board Layout Checklist

1. In order to minimize switching noise and improve out-

put load regulation, the GND pin of the LTC3806 should
be connected directly to 1) the negative terminal of the
INTV

decoupling capacitor, 2) the negative terminal

of the output decoupling capacitors, 3) the bottom ter-
minal of the current sense resistor, 4) the negative ter-
minal of the input capacitor and 5) at least one via to the
ground plane immediately adjacent to Pin 6 (GND).

2. Beware of ground loops in multiple layer PC boards. Try

to maintain one central ground node on the board and
use the input capacitor to avoid excess input ripple for
high output current power supplies. If the ground plane
is to be used for high DC currents, choose a path away
from the small-signal components.

3. Place the C

VCC

capacitor immediately adjacent to the

INTV

and GND pins on the IC package. This capacitor

carries high di/dt MOSFET gate drive currents. A low
ESR X5R 4.7

F ceramic capacitor works well here.

4. The high di/dt loop from the bottom terminal of the

input capacitor through the sense resistor, primary-
side power MOSFET, transformer primary and back
through the input capacitor should be kept as tight as
possible in order to reduce EMI. Also keep the loops
formed by the

outputs as tight as possible.

5. Check the switching waveforms of the MOSFETs using

the actual PC board layout. Measure directly across the
power MOSFET terminals to verify that the BV

DSS

specification of the MOSFET is not exceeded due to
inductive ringing. If this ringing cannot be avoided and

APPLICATIO S I FOR ATIO

MILLER EFFECT

MILLER

= (Q

)/V

DEVICE
UNDER TEST

GATE

3806 F06

Figure 6. Gate Charge Curve and Test Circuit

LTC3806

3806f

exceeds the maximum rating of the device, either choose
a higher voltage device or specify an avalanche-rated
power MOSFET.

6. Place the small-signal components away from high

frequency switching nodes. (All of the small-signal
components on one side of the IC and all of the power
components on the other.) This allows the use of a
pseudo-Kelvin connection for the signal ground, where
high di/dt gate driver currents flow out of the IC ground
pin in one direction (to the bottom plate of the INTV

decoupling capacitor) and small-signal currents flow in
the other direction.

7. Minimize the capacitance between the SENSE pin trace

and any high frequency switching nodes. The LTC3806
contains an internal leading edge blanking time of
approximately 180ns, which should be adequate for
most applications.

APPLICATIO S I FOR ATIO

8. For optimum load regulation and true remote sensing,

the top of the output resistor divider should connect
independently to the top of the the output capacitor
(Kelvin connection), staying away from any high dV/dt
traces. Place the divider resistors near the LTC3806 in
order to keep the high impedance FB node short.

9. For applications with multiple switching power convert-

ers which connect to the same input supply, make sure
that the input filter capacitor for the LTC3806 is not
shared with other converters. AC input current from
another converter could cause substantial input voltage
ripple and this could interfere with the operation of the
LTC3806. A few inches of PC trace or wire (L

100nH)

between the C

of the LTC3806 and the actual source

should be sufficient to prevent current sharing

problems.

Figure 7. Synchronous Flyback

SENSE

GND

RUN

INTV

LTC3806

33k

R10
12.4k

C14

1nF

C16

100pF

C20
4.7

20V

C19

220nF

C15

220nF

R16

76.8k

R17
12.4k

R13

42.3k

R5
232k

R4
47k

C5
2.2

1N4148

25V TO 60V

R3
TBD

C18

100

R14
0.056

Si4490DY

Si7806DN

XFMR_EFD20

Si7806DN

C25

100nF

10V

R18

100k

1nF

B260A

C7
220pF

C6
100

5V
1.5A

3.3V
2A

C26
100

3806 F07

5V
1.5A

C2
10

12V
400mA

C8
470

POSCAP

LTC3806

3806f

Table 1. Recommended Component Manufacturers

VENDOR

COMPONENTS

TELEPHONE

WEB ADDRESS

AVX

Capacitors

207-282-5111

avxcorp.com

BH Electronics

Transformers

952-894-9590

bhelectronics.com

Coiltronics

Transformers

407-241-7876

coiltronics.com

Diodes, Inc.

Diodes

805-446-4800

diodes.com

Fairchild

MOSFETs

408-822-2126

fairchildsemi.com

General Semiconductor

Diodes

516-847-3000

gerneralsemiconductor.com

International Rectifier

MOSFETs, Diodes

310-322-3331

irf.com

IRC

Sense Resistors

361-992-7900

irctt.com

Kemet

Tantalum Capacitors

408-986-0424

kemet.com

Magnetics Inc.

Toroid Cores

800-245-3984

mag-inc.com

Microsemi

Diodes

617-926-0404

microsemi.com

Murata-Erie

Capacitors

770-436-1300

murata.co.jp

Nichicon

Capacitors

847-843-7500

nichicon.com

On Semiconductor

Diodes

602-244-6600

onsemi.com

Panasonic

Capacitors

714-373-7334

panasonic.com

Sanyo

Capacitors

619-661-6835

sanyo.co.jp

Taiyo Yuden

Capacitors

408-573-4150

t-yuden.com

TDK

Capacitors, Transformers

562-596-1212

component.tdk.com

Thermalloy

Heat Sinks

972-243-4321

aavidthermalloy.com

Tokin

Capacitors

408-432-8020

tokin.com

United Chemicon

Capacitors

847-696-2000

chemi-com.com

Vishay/Dale

Resistors

605-665-9301

vishay.com

Vishay/Siliconix

MOSFETs

800-554-5565

vishay.com

Vishay/Sprague

Capacitors

207-324-4140

vishay.com

Zetex

Small-Signal Discretes

631-543-7100

zetex.com

APPLICATIO S I FOR ATIO

SENSE

GND

RUN

INTV

LTC3806

1N4148

C3
4.7

C6
100pF

C5
100

1nF

20V

C8
470nF

Q1
Si7450DP

Q2
Si7358DP

Q3
Si7448DP

C4
330pF

C1
1.5

C2
330

4.7

PULSE PA0031

3806 TA01

OUT

3.3V
8A

R1
220

R10
12.5k

3.3k

R6
51k

R7
12.5k

R5
330k

36V TO 72V

20.5k

R11

100

R2
0.1

TYPICAL APPLICATIO

Synchronous Forward Application

LTC3806

3806f

PACKAGE DESCRIPTIO

UE/DE Package

12-Lead Plastic DFN (4mm

3mm)

(Reference LTC DWG # 05-08-1695)

4.00

0.10

(2 SIDES)

3.00

0.10

(2 SIDES)

NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION

(WGED) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

0.38

0.10

BOTTOM VIEW--EXPOSED PAD

1.70

0.10

(2 SIDES)

0.75

0.05

R = 0.115

TYP

R = 0.20

TYP

0.25

0.05

3.30

0.10

(2 SIDES)

0.50
BSC

PIN 1
NOTCH

PIN 1

TOP MARK

(NOTE 6)

0.200 REF

0.00 0.05

(UE12/DE12) DFN 0603

0.25

0.05

3.30

0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.70

0.05

(2 SIDES)

2.20

0.05

0.50
BSC

0.65

0.05

3.50

0.05

PACKAGE OUTLINE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3806

3806f

LINEAR TECHNOLOGY CORPORATION 2004

LT/TP 0104 1K · PRINTED IN THE USA

PART NUMBER

DESCRIPTION

COMMENTS

1619

Current Mode PWM Controller

300kHz Fixed Frequency, Boost, SEPIC Flyback Topology

LTC1624

Current Mode DC/DC Controller

SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design;

Up to 36V

LTC1700

No R

SENSE

Synchronous Step-Up Controller

Up to 95% Efficiency, Operation as Low as 0.9V Input

LT1725

General Purpose Isolated Flyback Controller

Drives External Power MOSFET, Senses Output Voltage Directly from
Primary Side Switching--No Optoisolator Required, 16-Pin SSOP

LTC1871

Wide Input Range Current Mode No R

SENSE

Controller

50kHz to 1000kHz Frequency; Boost, Flyback and SEPIC Topology

LTC1872

SOT-23 Boost Controller

Delivers Up to 5A, 550kHz Fixed Frequency, Current Mode

LT1910

Protected High Side MOSFET Driver

8V to 48V Power Supply Range; Protected from 15V to 60V Supply
Transients, Short-Circuit Protection, Automatic Restart Timer

LT1930

1.2MHz SOT-23 Boost Converter

Up to 34V Output, 2.6V

16V, Miniature Design

LT1931

Inverting 1.2MHz, SOT-23 Converter

Positive-to-Negative DC/DC Conversion, Miniature Design

LT1950

Single Switch Forward Controller

25V, 25W to 500W, Programmable Slope Compensation

LTC3401/LTC3402

1A/2A, 3MHz Synchronous Boost Converters

Up to 97% Efficiency, Very Small Solution, 0.5V

LT3781/LTC1698

36V to 72V Input Isolated DC/DC Converter Chipset

Synchronous Operation; Overvoltage/Undervoltage Protection;
10W to 100W Power Supply; 1/2-, 1/4-Brick Footprint

LTC3803

SOT-23 Flyback Contoller

Adjustable Slope Compensation, Internal Soft-Start, 200kHz

No R

SENSE

is a trademark of Linear Technology Corporation.

RELATED PARTS

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear.com

TYPICAL APPLICATIO

Figure 8. Mulitple Output Flyback Converter for Telecom

SENSE

GND

RUN

INTV

LTC3806

33k

0603

R3
12.4k
0603

1nF

0603

100pF

0603

C12

220nF

0603

R5
0.033

1206

Si4490

Si7806DN

GND

C15
4.7

10V
0805

R6
12.4k
0603

20.5k

0603

Si7806DN

C10
470

4V POSCAP
7343

C11
100

1210

OUT

2.5V
2A

XFMR EFD20

1A 60V

B260A SMA

C6
470

4V POSCAP
7343

C7
100

1210

C5
47

1812

C4
10

1812

OUT

3.3V
3A

GND

3806 F08

OUT

5V
400mA

OUT

12V
400mA

GND

R2
47k
0805

R1
232k
0805

C13
100

35V TANT
7343

20V

225mW

C14
220nF
0603

C3
2.2

100V
1812

C2
220nF
1206

C1
10

63V
ELEC

1N4148W

SOD123

3.3

25V TO 60V

GND

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC3806EDE

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC3806EDE