1
LTC4212
4212f
APPLICATIO S
U
FEATURES
TYPICAL APPLICATIO
U
DESCRIPTIO
U
s
Allows Safe Board Insertion and Removal
from a Live Backplane
s
Controls Supply Voltages from 2.5V to 16.5V
s
Adjustable Soft-Start with Inrush Current
Limiting
s
Fast Turn-Off Time
s
No External Gate Capacitor is Required
s
Power Good Input with Adjustable Timer and
Glitch Filter
s
Power-Up Timeout Circuit Interfaces with External
Supply Monitors
s
Dual Level Overcurrent Fault Protection
s
Automatic Retry or Latched Mode Operation
s
High Side Drive for an External N-Channel FET
s
MS10 Package
The LTC
4212 is a Hot Swap
TM
controller that allows a
board to be safely inserted and removed from a live
backplane. An internal high side switch driver controls the
gate of an external N-channel MOSFET for supply voltages
ranging from 2.5V to 16.5V. The LTC4212 provides soft-
start and inrush current limiting during the start-up
period. It features a power-up timeout circuit that discon-
nects the system supply when the onboard supplies do not
enter into regulation within an adjustable timeout period.
The controller interfaces with external supply monitor ICs
or directly with the PGOOD pin of a DC/DC converter. After
normal power-up, a programmable power good glitch
filter can be enabled to filter out short term dips in the
supplies.
Two current limit comparators provide dual level
overcurrent circuit breaker protection. The slow com-
parator trips at V
CC
50mV and activates in 18
s. The fast
comparator trips at V
CC
150mV and typically responds
in 500ns.
The LTC4212 can be configured for both latchoff and
autoretry applications and is available in a 10-pin MSOP
package.
s
Electronic Circuit Breaker
s
Hot Board Insertion and Removal
s
Self-Isolating Hot Swap Boards
Hot Swap Controller with
Power-Up Timeout
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
+
V
CC
SENSE
LTC4212
10
F
+
10
F
5V
2.5V
1.5A
3.3V
1.5A
4212 TA01a
GATE
PGT
PGF
TIMER
0.01
F
PGI
ON
V
CC
5V
GND
Z1 = SMAJ10A (TVS)
20k
10k
10
0.007
EDGE
CONNECTOR
(MALE)
Si4410DY
Z1
10k
10k
2.1k
10k
FAULT
GND
FAULT
+
10
F
LT1963-2.5
4.7nF
270pF
100nF
BACKPLANE
CONNECTOR
(FEMALE)
+
10
F
+
10
F
LT1963-3.3
LTC1727-2.5
GND
V
CCA
V
CC3
COMP2.5
V
CC25
COMP3
COMP A
Power-Up Waveforms
ON
5V/DIV
TIMER
1V/DIV
PGT
1V/DIV
PGI
5V/DIV
Hot Swap Controller with Power Good Function
5ms/DIV
2
LTC4212
4212f
Supply Voltage (V
CC
) ............................................... 17V
Input Voltages
ON, PGI ................................................ 0.3V to 17V
SENSE .................................... 0.3V to (V
CC
+ 0.3V)
TIMER, PGT, PGF .................................... 0.3V to 2V
Output Voltages
GATE ............................... Internally Limited (Note 3)
FAULT .................................................. 0.3V to 17V
Operating Temperature Range
LTC4212C .............................................. 0
C to 70
C
LTC4212I ........................................... 40
C to 85
C
Storage Temperature Range ................. 65
C to 150
C
Lead Temperature (Soldering, 10 sec).................. 300
C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ABSOLUTE AXI U RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
(Note 1)
ORDER PART
NUMBER
LTC4212CMS
LTC4212IMS
MS PART
MARKING
LTC5
LTC6
T
JMAX
= 125
C,
JA
= 200
C/ W
1
2
3
4
5
ON
TIMER
PGT
PGF
GND
10
9
8
7
6
FAULT
V
CC
SENSE
GATE
PGI
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
V
CC
Supply Voltage Range
q
2.5
16.5
V
I
CC
V
CC
Supply Current
ON = High, TIMER = Low
q
1
1.5
mA
V
LKO
Internal V
CC
Undervoltage Lockout
V
CC
Low-to-High Transition
q
2.13
2.34
2.47
V
V
LKOHST
V
CC
Undervoltage Lockout Hysteresis
110
mV
I
INON
ON Input Current
V
ON
= V
CC
or GND
1
10
A
I
LEAK
FAULT Leakage Current
V
FAULT
= 15V, Pull-Down Device Off
q
0.1
2.5
A
I
INPGI
PGI Pin Input Current
V
PGI
= V
CC
or GND
1
10
A
I
INSENSE
SENSE Input Current
V
SENSE
= V
CC
or GND
1
10
A
V
CB(FAST)
SENSE Trip Voltage (V
CC
V
SENSE
)
Fast Comparator Trips
q
130
150
170
mV
V
CB(SLOW)
SENSE Trip Voltage (V
CC
V
SENSE
)
Slow Comparator Trips
q
40
50
60
mV
I
GATEUP
GATE Pull-Up Current
Charge Pump On, V
GATE
0.2V
q
12.5
10
7.5
A
I
GATEDOWN
Normal GATE Pull-Down Current
ON Low
q
130
200
270
A
Fast GATE Pull-Down Current
FAULT Latched and Circuit Breaker
50
mA
Tripped or in UVLO, V
GATE
= 15V
V
GATE
External N-Channel Gate Drive
V
GATE
V
CC
(For V
CC
= 2.5V)
q
4.0
8
V
V
GATE
V
CC
(For V
CC
= 2.7V)
q
4.5
8
V
V
GATE
V
CC
(For V
CC
= 3.3V)
q
5.0
10
V
V
GATE
V
CC
(For V
CC
= 5V)
q
10
16
V
V
GATE
V
CC
(For V
CC
= 12V)
q
10
18
V
V
GATE
V
CC
(For V
CC
= 15V), (Note 3)
q
8
15
V
V
GATEOV
GATE Overvoltage Lockout Threshold
q
0.08
0.2
0.3
V
V
ONHI
ON Threshold High
q
1.23
1.316
1.39
V
V
ONLO
ON Threshold Low
q
0.4
0.455
0.5
V
V
PGI
Power Good Input Threshold
q
1.20
1.236
1.26
V
V
PGIHST
Power Good Input Hysterisis
28
mV
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T
A
= 25
C. V
CC
= 5V, unless otherwise noted. (Note 2)
ELECTRICAL CHARACTERISTICS
3
LTC4212
4212f
V
PGFHI
Power Good Glitch Filter High Threshold
q
1.20
1.236
1.26
V
V
PGFHST
Power Good Glitch Filter Hysterisis
(Note 4)
40
mV
V
PGTHI
Power Good Timer High Threshold
q
0.928
0.952
0.976
V
V
PGTLO
Power Good Timer Low Threshold
q
0.640
0.657
0.680
V
V
PGT
V
Power Good Timer Delta Threshold
q
0.283
0.295
0.304
V
I
PGT
Power Good Timer Pin Current
Power Good Timer On, C
PGT
Charging, PGT = 0.65V
q
5.61
5.1
4.59
A
Power Good Timer On, C
PGT
Discharging, PGT = 0.95V
q
4.63
5.2
5.77
A
Power Good Timer Off, PGT = 1.5V
5
mA
I
PGF
Power Good Glitch Filter Pin Current
Power Good Glitch Filter On, C
PGF
Charging
q
5.61
-5.1
4.49
A
Power Good Timer Off, PGF = 1.5V
5
mA
I
TMR
TIMER Current
Timer On, V
TIMER
= 1V
q
2.5
2
1.5
A
Timer Off, TIMER = 1.5V
5
mA
V
TMR
TIMER Threshold
TIMER Low to High
q
1.20
1.236
1.26
V
TIMER High to Low
q
0.15
0.200
0.40
V
V
FAULT
FAULT Threshold
Latched Off Threshold, FAULT High to Low
q
1.20
1.236
1.26
V
V
FAULTHST
FAULT Threshold Hysteresis
50
mV
V
OLFAULT
Output Low Voltage
I
FAULT
= 1.6mA
q
0.14
0.4
V
t
TO
Power Good Time-Out
C
PGT
=10nF, PGT = 0.1V to FAULT Low
q
16.3
18.16
20
ms
t
FAULTLO
Power Good Input Low at Time-Out to
End of 14th PGT Cycle
1
s
GATE Discharging
t
FAULTVG
Valid Power Good Glitch to GATE
PGF > 1.26V
1.5
s
Discharging
t
FAULTFC
FAST COMP Trip to GATE Discharging
V
CB
= 0mV to 200mV Step
q
500
700
ns
t
FAULTSC
SLOW COMP Trip to GATE Discharging
V
CB
= 0mV to 100mV Step
q
10
18
30
s
t
EXTFAULT
FAULT Low to GATE Discharging
V
FAULT
= 5V to 0V
q
1
3
5
s
t
RESET
Circuit Breaker Reset Delay Time
ON Low to FAULT High
q
120
250
s
t
OFF
Turn-Off Time
ON Low to GATE Off
10
s
The
q
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T
A
= 25
C. V
CC
= 5V, unless otherwise noted. (Note 2)
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All current into device pins are positive; all current out of device
pins are negative; all voltages are referenced to ground unless otherwise
specified.
Note 3: An internal clamp limits the GATE pin to a minimum of 10V above
V
CC
. Driving this pin to voltages beyond the clamp may damage the part. If
a lower GATE pin voltage is desired, use an external zener diode. The GATE
capacitance must be < 0.15
F at maximum V
CC
.
Note 4: Guaranteed by design and not tested in production.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4
LTC4212
4212f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
GATE Voltage vs Supply Voltage
V
GATE
V
CC
vs Supply Voltage
GATE Voltage vs Temperature
V
GATE
V
CC
vs Temperature
Supply Current vs Supply Voltage
Supply Current vs Temperature
Undervoltage Lockout
Threshold vs Temperature
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (mA)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
16
4212 G01
4
8
12
20
14
2
6
10
18
TEMPERATURE (
C)
SUPPLY CURRENT (mA)
2.0
2.5
3.0
4212 G02
1.5
1.0
0
0.5
4.0
3.5
V
CC
= 16.5V
V
CC
= 5V
V
CC
= 2.5V
50
0
25
125
25
50
75
100
TEMPERATURE (
C)
2.0
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
2.1
2.3
2.4
2.5
25
25
50
4212 G03
2.2
50
0
75
100
125
FALLING EDGE
RISING EDGE
SUPPLY VOLTAGE (V)
0
GATE VOLTAGE (V)
10
20
30
5
15
25
4
8
12
16
4212 G06
18
2
0
6
10
14
TEMPERATURE (
C)
50
0
GATE VOLTAGE (V)
5
15
20
25
0
25
125
4212 G07
10
25
50
75
100
30
V
CC
= 16.5V
V
CC
= 5V
V
CC
= 2.5V
SUPPLY VOLTAGE (V)
0
0
V
GATE
V
CC
(V)
2
6
8
10
12
14
16
18
4212 G08
4
2
4
6
8
10
18
12
14
16
TEMPERATURE (
C)
0
V
GATE
V
CC
(V)
2
6
8
10
75
18
4212 G09
4
0
25
50
100
50
25
125
12
14
16
V
CC
= 15V
V
CC
= 3.3V
V
CC
= 5V
V
CC
= 12V
Specifications are T
A
= 25
C. V
CC
= 5V, unless
otherwise noted.
GATE Output Source Current vs
Supply Voltage
GATE Output Source Current vs
Temperature
SUPPLY VOLTAGE (V)
7
GATE OUTPUT SOURCE CURRENT (
A)
9
11
13
8
10
12
4
8
12
16
4212 G10
20
2
0
6
10
14
18
TEMPERATURE (
C)
7
GATE OUTPUT SOURCE CURRENT (
A)
8
10
11
12
25
25
50
4212 G11
9
50
0
75
100
125
13
V
CC
= 16.5V
V
CC
= 2.5V
V
CC
= 5V
5
LTC4212
4212f
Fast GATE Pull-Down Current vs
Supply Voltage
Fast GATE Pull-Down Current vs
Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
SUPPLY VOLTAGE (V)
20
FAST GATE PULL-DOWN CURRENT (mA)
40
60
80
30
50
70
4
8
12
16
4212 G14
18
2
0
6
10
14
TEMPERATURE (
C)
20
FAST GATE PULL-DOWN CURRENT (mA)
30
50
60
70
25
25
50
4212 G15
40
50
0
75
100
125
80
Specifications are T
A
= 25
C. V
CC
= 5V, unless
otherwise noted.
V
CB
(SLOW COMP) vs Supply
Voltage
SUPPLY VOLTAGE (V)
0
V
CB
(SLOW COMP) (mV)
52
56
60
16
4212 G26
48
44
50
54
58
46
42
40
4
2
8
6
12
14
10
18
V
CB
(FAST COMP) vs Supply
Voltage
SLOW COMP Trips to GATE
Discharging Delay vs Supply
Voltage
SUPPLY VOLTAGE (V)
0
V
CB
(FAST COMP) (mV)
170
165
160
155
150
145
140
135
130
16
4212 G28
4
8
12
18
14
2
6
10
SUPPLY VOLTAGE (V)
0
SLOW COMP TRIPS TO GATE
DISCHARGING DELAY (
s)
26
24
22
20
18
16
14
12
10
16
4212 G30
4
8
12
18
14
2
6
10
FAST COMP Trips to GATE
Discharging Delay vs Supply
Voltage
FAST COMP Trips to GATE
Discharging Delay vs Temperature
SLOW COMP Trips to GATE
Discharging Delay vs Temperature
TEMPERATURE (
C)
SLOW COMP TRIPS TO GATE
DISCHARGING DELAY (
s)
18
20
22
125
4212 G31
16
14
10
25
25
75
50
0
50
100
12
26
24
V
CC
= 16.5V
V
CC
= 3V
V
CC
= 5V
V
CC
= 15V
V
CC
= 12V
SUPPLY VOLTAGE (V)
0
FAST COMP TRIPS TO GATE
DISCHARGING DELAY (ns)
600
500
400
300
200
100
0
16
4212 G32
4
8
12
18
14
2
6
10
V
CB
= 0mV TO 200mV STEP
TEMPERATURE (
C)
FAST COMP TRIPS TO GATE
DISCHARGING DELAY (ns)
400
500
125
4212 G33
300
200
0
25
25
75
50
0
50
100
100
700
600
V
CB
= 0mV TO 200mV STEP
V
CC
= 16.5V
V
CC
= 3V
V
CC
= 12V
V
CC
= 5V
V
CC
= 15V
Power Good Timeout vs Supply
Voltage
SUPPLY VOLTAGE (V)
15
POWER GOOD TIME-OUT (ms)
19
21
18
20
17
16
4
8
12
16
4212 G40
18
2
0
6
10
14
6
LTC4212
4212f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Specifications are T
A
= 25
C. V
CC
= 5V, unless
otherwise noted.
Power Good Timeout vs
Temperature
PGI Low at Timeout to GATE
Discharging vs Supply Voltage
PGI Low at Timeout to GATE
Discharging vs Temperature
15.0
POWER GOOD TIME-OUT (ms)
18.0
19.0
20.0
17.5
18.5
19.5
17.0
16.5
16.0
15.5
4212 G41
TEMPERATURE (
C)
25
25
50
50
0
75
100
125
SUPPLY VOLTAGE (V)
0
PGI LOW AT TIME-OUT TO GATE DISCHARGING (V)
1.8
1.5
1.2
0.9
0.6
0.3
16
4212 G44
4
8
12
18
14
2
6
10
TEMPERATURE (
C)
0.2
PGI LOW AT TIME-OUT TO GATE DISCHARGING (
s)
2.0
25
25
50
4212 G45
50
0
75
100
125
0.4
0.8
1.2
1.4
1.8
0.6
1.0
1.6
PGF and PGT Pin Current
(Timer or Filter Off)
vs Supply Voltage
PGF and PGT Pin Current
(Timer or Filter Off)
vs Temperature
0
PGF AND PGT CURRENT (TIMER OR FILTER OFF) (mA)
10
9
8
7
6
5
4
3
2
1
4212 G51
TEMPERATURE (
C)
25
25
50
50
0
75
100
125
PGF
PGT
Valid Glitch to GATE Discharging
vs Temperature
Valid Glitch to GATE Discharging
vs Supply Voltage
FAULT V
OL
vs Supply Voltage
SUPPLY VOLTAGE (V)
1.30
VALID GLITCH TO GATE DISCHARGING (
s)
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
4
8
12
16
4212 G52
18
2
0
6
10
14
0.5
VALID GLITCH TO GATE DISCHARGING (
s)
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
4212 G53
TEMPERATURE (
C)
25
25
50
50
0
75
100
125
SUPPLY VOLTAGE (V)
0
FAULT V
OL
(V)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
16
4212 G54
4
8
12
18
14
2
6
10
I
OL
= 5mA
I
OL
= 1mA
FAULT V
OL
vs Temperature
TEMPERATURE (
C)
PGF AND PGT PIN CURRENT (TIMER OR FILTER OFF) (mA)
4
5
6
4212 G50
3
2
0
1
8
7
50
0
25
125
25
50
75
100
TEMPERATURE (
C)
VOL (V)
0.20
0.25
0.30
4212 G55
0.15
0.10
0
0.05
0.40
0.35
50
0
25
125
25
50
75
100
7
LTC4212
4212f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
Specifications are T
A
= 25
C. V
CC
= 5V, unless
otherwise noted.
FAULT Pin Low to GATE
Discharging Time vs Temperature
Circuit Breaker RESET Time vs
Supply Voltage
Turn-Off Time vs Supply Voltage
Circuit Breaker RESET Time vs
Temperature
Turn-Off Time vs Temperature
FAULT Pin Low to GATE
Discharging Time vs Supply
Voltage
SUPPLY VOLTAGE (V)
1.5
FAULT PIN LOW TO GATE DISCHARGING TIME (
s)
2.5
3.5
4.5
2.0
3.0
4.0
4
8
12
16
4212 G58
18
2
0
6
10
14
TEMPERATURE (
C)
1.5
FAULT PIN LOW TO GATE DISCHARGING TIME (
s)
2.0
3.0
3.5
4.0
25
25
50
4212 G59
2.5
50
0
75
100
125
4.5
SUPPLY VOLTAGE (V)
80
CIRCUIT BREAKER RESET TIME (
s)
120
160
200
100
140
180
4
8
12
16
4212 G60
18
2
0
6
10
14
TEMPERATURE (
C)
80
CIRCUIT BREAKER RESET TIME (
A)
100
140
160
180
25
25
50
4212 G61
120
50
0
75
100
125
200
SUPPLY VOLTAGE (V)
5
TURN-OFF TIME (
s)
7
9
11
6
8
10
4
8
12
16
4212 G62
18
2
0
6
10
14
TEMPERATURE (
C)
8.0
TURN-OFF TIME (
s)
9.0
11.0
12.0
12.5
25
25
50
4212 G63
10.0
8.5
10.5
11.5
9.5
50
0
75
100
125
13.0
8
LTC4212
4212f
U
U
U
PI FU CTIO S
ON (Pin 1): On/Off Control Input. The ON pin is used to
enable and disable LTC4212 operation and reset internal
logic and the electronic circuit breaker (ECB). It must be
pulled high (>1.316V) to start the first system timing
cycle. If the ON pin is pulled low (<0.455V typical) for more
than 10
s, the internal logic is reset and the GATE pin is
pulled down by a 200
A current to turn off the external
FET. If the ON pin is pulled low for more than 120
s, the
electronic circuit breaker is reset. This pin is tied to a
resistive divider in latch-off applications or to the FAULT
pin and an external RC circuit in auto-retry applications.
TIMER (Pin 2): System Timer Input. An external capacitor
(C
TIMER
) connected from this pin to ground determines
the duration of the first and second system timing cycles.
The first timing cycle allows time for the board to be
inserted properly. During the second timing cycle, a
soft-start circuit controls the gate of the external
N-channel FET to limit inrush currents from the backplane
supply.
PGT (Pin 3): Power Good Timer Input. An external capaci-
tor (C
PGT
) connected from this pin to ground sets the
power good time-out period. This is the maximum time
allowed for externally monitored DC/DC converters to
power-up into regulation and pull the PGI pin high. The
nominal time-out cycle is 1.81s/
F and begins from the
end of the second system timing cycle. This pin is pulled
to ground by an internal switch when the power good timer
is disabled or when the ECB is tripped.
PGF (Pin 4): Power Good Glitch Filter Input. An external
capacitor (C
PGF
) connected from this pin to ground deter-
mines the power good glitch filter delay. The glitch filter is
enabled if the externally monitored DC/DC converters are
powered up within the power good time-out period (see
Pin 3). If the PGI pin goes low for longer than the filter
delay, the ECB is tripped.
GND (Pin 5): Device Ground Connection. Connect this pin
to the system's analog ground plane.
PGI (Pin 6): Power Good Input Pin. This pin is used by the
power good circuit to sense the open drain RST output or
comparator outputs of an external supply monitor IC or
the PGOOD output of a DC/DC converter. It requires an
external pull-up resistor to a voltage above the V
FAULT
threshold 1.236V. When the power good timer times out
(see Pin 3), PGI must be high to avoid tripping the ECB and
to enable the power good glitch filter.
GATE (Pin 7): Gate Output Pin. The output signal at this
pin is the high side gate drive for the external N-channel
FET pass transistor.
As shown in the Block Diagram, an internal charge pump
supplies a 10
A gate current and sufficient gate voltage to
drive the external FET for supply voltages from 2.5V to
16.5V. The internal charge pump and zener clamps at the
charge pump output determine the gate drive voltage
(
V
GATE
= V
GATE
V
CC
). The charge pump produces a
minimum 4V of
V
GATE
for supplies in the range of 2.5V <
V
CC
< 4.75V. For V
CC
> 4.75V, the
V
GATE
is limited by
zener clamp Z1 connected between the charge pump
output and the V
CC
pin. The
V
GATE
is typically at 12V and
with guaranteed minimum value of 10V. For V
CC
> 15V, the
zener clamp Z2 sets the limitation for
V
GATE
. Z2 clamps
the gate voltage to ground to 28V typically. The minimum
Z2's clamp voltage is 23V. This effectively sets
V
GATE
to
8V minimum.
SENSE (Pin 8): Circuit Breaker Set Pin. With a sense
resistor placed in the power path between V
CC
and SENSE,
the LTC4212's electronic circuit breaker trips if the voltage
across the sense resistor exceeds the thresholds set
internally for the SLOW COMP and the FAST COMP, as
shown in the Block Diagram. The threshold for the SLOW
COMP is V
CB(SLOW)
= 50mV, and the electronic circuit
breaker trips if the voltage across the sense resistor
exceeds 50mV for 18
s.
Under transient conditions where large step current
changes can and do occur over shorter periods of time, a
second (fast) comparator instead trips the electronic
circuit breaker. The threshold for the FAST COMP is set at
V
CB(FAST)
= 150mV, and the circuit breaker trips if the
voltage across the sense resistor exceeds 150mV for more
than 500ns. To disable the electronic circuit breaker,
connect the V
CC
and SENSE pins together.
V
CC
(Pin 9): This is the positive supply input to the LTC4212. The
LTC4212 operates from 2.5V < V
CC
< 16.5V, and the supply
current is typically 1mA. An internal undervoltage lockout circuit
disables the device until the voltage at V
CC
exceeds 2.34V.
9
LTC4212
4212f
U
U
U
PI FU CTIO S
+
+
+
+
SLOW
COMP
50mV
150mV
0.2V
COMP7
M3
18
S
GLITCH FILTER
UVLO
+
FAST
COMP
500ns
DELAY
BG
V
REF
=
1.236V
0.2V
CB
TRIPS
OR UVLO
ON LOW
>10
s
START-UP
CURRENT
REGULATOR
GATE
CHARGING
200
A
10
A
CB TRIPS
V
REF
10
A
7
GATE
8
SENSE
9
V
CC
CHARGE
PUMP
Z1
V
Z
(TYP) = 12V
M2
GND
5
FAULT
10
+
4212 BD
+
+
COMP3
t
TIMER
0.2V
V
REF
COMP4
NORMAL
TIMER
2
ON
1
2
A
M6
V
CC
M5
COMP6
Z2
V
Z
(TYP) = 28V
V
CC
1.316V
0.455V
1.5
s
DELAY
V
REF
4
PGF
+
COMP5
M12
M9
M8
3
PGT
+
COMP9
M1
M10
5
A
5
A
5
A
V
REF
0.65V
0.95V
DISABLE
GLITCH
FILTER
VALID
GLITCH
DISABLE
TIMER
6
PGI
+
COMP8
+
+
COMP2
COMP1
LOGIC
10
s
120
s
200
A
GATE
PULLDOWN
RESET
ECB
0.95V
0.65V
BLOCK DIAGRA
W
FAULT (Pin 10): Open Drain FAULT Output or External
FAULT Input. If the FAST COMP, SLOW COMP or the
power good circuit trips the ECB, the FAULT pin is latched
low. The FAULT pin is an open drain output and is typically
connected by a 10k pull-up resistor to V
CC
. An external
circuit can also trip the ECB by driving FAULT below
1.236V (typical).
10
LTC4212
4212f
Figure 1. ON Pin Sets the Undervoltage
Lockout Voltage Externally
3.3V
R1
10k
R2
10k
ON PIN
(a) V
CC
= 3.3V
5V
R1
20k
R2
10k
ON PIN
(b) V
CC
= 5V
12V
R1
61.9k
R2
10k
ON PIN
(c) V
CC
= 12V
4212 F01
Hot Circuit Insertion
When circuit boards are inserted into or removed from live
backplanes, the supply bypass capacitors can draw huge
transient currents from the backplane power bus as they
charge. The transient current can cause permanent dam-
age to the connector pins as well as cause glitches on the
system supply, causing other boards in the system to
reset.
The LTC4212 is designed to turn a printed circuit board's
supply voltages ON and OFF in a controlled manner, allow-
ing the circuit board to be safely inserted or removed from
a live backplane.
Output Voltage Monitor
Unlike other LTC Hot Swap controller products, the
LTC4212 does not have an FB pin and monitors onboard
DC/DC converters via an external power supply monitor IC
such as the LTC1326-2.5 or the LTC1727. This allows
several DC/DC converters to be monitored at the same
time. The LTC4212's PGI or power good input pin is used
to monitor the RST or comparator outputs of the monitor
IC and it can also be tied directly to the PGOOD pin of a
DC/DC converter.
Undervoltage Lockout
The LTC4212's internal power-on reset circuit initializes
the start-up procedure and ensures the IC is in the proper
state if the input supply voltage exceeds 2.34V. If the
supply voltage falls below 2.23V, the LTC4212 is in
undervoltage lockout (UVLO) mode, and the GATE pin is
pulled low. Since the UVLO circuitry uses hysteresis, the
LTC4212 restarts after the supply voltage rises above
2.34V and the ON pin goes high.
In addition, users can utilize the ON comparator (COMP1)
or the FAULT comparator (COMP6) to effectively set up a
higher undervoltage lockout level. Figure 1 shows the
external resistive divider for the ON pin to adjust the
system's undervoltage lockout voltage. The system will
enter the plug-in cycle after the ON pin rises above 1.316V.
The resistive divider sets the circuit to turn on when V
CC
reaches around 79% of its final value. If a different turn on
V
CC
voltage is desired change the resistive divider ratio
accordingly. The FAULT comparator can also be used to
set a higher undervoltage lockout voltage. If the FAULT
comparator is used for this purpose, the system will wait
for the input voltage to increase above the level set by the
user before starting the second timing cycle. Also, if the
input voltage drops below the set level in normal operating
mode, the electronic circuit breaker (ECB) trips and the
user must cycle the ON pin or V
CC
to restart the system.
OPERATIO
U
System Timing
System timing for the LTC4212 is generated by the TIMER
circuitry (see the Block Diagram). If the LTC4212's inter-
nal timing circuit is off, an internal N-channel FET connects
the TIMER pin to GND. If the timing circuit is enabled, an
internal 2
A current source is then connected to the
TIMER pin to charge C
TIMER
at a rate given by Equation 1:
C
Charge -Up Rate
TIMER
=
2 A
C
TIMER
(1)
When the TIMER pin voltage reaches COMP4's threshold
of 1.236V, the TIMER pin is reset to GND. Equation 2 gives
an expression for the timer period:
t
V
C
A
TIMER
TIMER
=
1 236
2
.
(2)
As a design aid, the LTC4212's timer period as a function
of the C
TIMER
using standard values from 3.3nF to 0.33
F
is shown in Table 1.
The C
TIMER
value is vital to ensure a proper start-up and
reliable operation. This timing period should not be exces-
sive as an output short can occur at start-up causing the
external MOSFET to overheat. A good starting point is to
11
LTC4212
4212f
set C
TIMER
= 10nF and adjust its value accordingly to suit
the specific applications.
Table 1. t
TIMER
vs C
TIMER
C
TIMER
t
TIMER
0.0033
F
2.0ms
0.0047
F
2.9ms
0.0068
F
4.2ms
0.0082
F
5.1ms
0.01
F
6.2ms
0.015
F
9.3ms
0.022
F
13.6ms
0.033
F
20.4ms
0.047
F
29.0ms
0.068
F
42.0ms
0.082
F
50.7ms
0.1
F
61.8ms
0.15
F
92.7ms
0.22
F
136ms
0.33
F
204ms
Power-Up Timeout Circuit
The power-up timeout circuit has two functions. During
power-up, it trips the circuit breaker if the DC/DC convert-
ers on the board do not power-up and do not enter
regulation on time. After normal power-up, it is configured
to trip the circuit breaker if any of the converters exit
regulation for longer than a programmable delay. Once the
circuit breaker is tripped, the LTC4212 is latched off and
the board is disconnected from the system supply. The ON
pin must be taken low for 120
s to reset the circuit breaker
and then high to reconnect the board to the backplane
supply.
The power-up timeout circuit uses three pins: PGI or
power good input pin, PGT or power good timer pin and
PGF or power good filter pin. It is enabled at the end of the
second system timing cycle, provided that the FAULT pin
is high. Prior to being enabled or if FAULT is low, the PGT
and PGF pins are pulled to GND by internal N-channel
FETs, M5 and M12 respectively. When enabled, the
power-up timeout circuit starts the power good timer,
which generates a time-out period before the PGI pin is
sampled.
OPERATIO
U
Power Good Timer
The timer consists of COMP9, M8-M12, two 5
A current
sources and 0.65V and 0.95V threshold voltages for
COMP9.
The PGI pin is normally connected to the RST output pin
or comparator outputs of an external supply monitor IC or
to the PGOOD pin of a DC/DC converter and drives a
comparator, COMP8 which has a threshold voltage of
1.236V and 28mV of hysterisis. The RST and PGOOD pins
are typically open drain pins and require an external pull-
up resistor. The upper end of the resistor must be con-
nected to a voltage greater than the upper threshold of the
PGI comparator (1.236V).
A capacitor, C
PGT
, connected from the PGT pin to ground
programs the time-out period generated by the power
good timer according to Equation 3. Table 2 shows the
power good time-out periods for a list of standard capaci-
tor values.
t
TIMEOUT
= 1.81
C
PGT
(3)
Two 5
A current sources are switched in and out to charge
and discharge C
PGT
between 0.65V and 0.95V for 14
cycles.
Table 2. t
TIMEOUT
vs C
PGT
C
PGT
t
TIMEOUT
3.3nF
5.97ms
4.7nF
8.51ms
6.8nF
12.3ms
8.2nF
14.8ms
0.01
F
18.1ms
0.022
F
39.8ms
0.033
F
59.7ms
0.047
F
85.1ms
0.068
F
123ms
0.082
F
148ms
0.1
F
181ms
0.22
F
136ms
0.33
F
398ms
0.47
F
851ms
0.68
F
1230ms
0.82
F
1480ms
1
F
1810ms
12
LTC4212
4212f
Since the PGT is pulled to GND by M12 before the power
good circuit is enabled, the first positive ramp at the PGT
pin starts from 0V instead of the 0.65V for the subsequent
13 cycles.
Power Good Time-Out
At the end of the time-out period, the PGI pin is sampled.
M12 is turned on to discharge C
PGT
to ground. If the PGI
pin is low when sampled, the DC/DC converters have not
entered into regulation on time and the power good circuit
trips the circuit breaker to latch off the board. If PGI is high
when sampled, the converters powered up into regulation
on time and the board is left powered up. The power good
glitch filter is enabled and it monitors the PGI pin for a low,
an indication that at least one DC/DC converter has dropped
out of regulation. The glitch filter rejects low pulses
shorter than a programmable period.
Power Good Glitch Filter
A glitch filter consisting of COMP5, M5 and a 5
A current
source rejects PGI low pulses that are shorter than the
duration programmed by an external capacitor, C
PGF
,
connected from the PGF pin to GND.
Once the glitch filter is enabled, M5 is switched off
whenever PGI goes low. This allows an internal 5
A
current source to charge the capacitor at the PGF pin. If
PGI stays low for long enough, the voltage at the PGF pin
rises above the upper threshold of COMP5 (1.236V) and
causes the power good circuit to trip the circuit breaker.
For a given C
PGF
capacitance connected between PGF and
GND, the minimum low PGI pulse width needed to trip the
circuit breaker is given by:
t
PGF
= 1.236V (C
PGF
)/5
A + 5
s
(4)
An internal 5pF capacitor and stray MSOP-10 package
capacitance sets t
PGF
to 5
s nominal when C
PGF
is omit-
ted. Table 3 shows t
PGF
values for various standard
capacitors. Tying the PGF pin to ground prevents the
power good glitch filter from tripping the circuit breaker
after normal power-up.
OPERATIO
U
Table 3. t
PGF
vs C
PGF
C
PGF
t
PGF
--
5
s
10pF
7.5
s
22pF
10.4
s
33pF
13.2
s
47pF
16.6
s
68pF
21.8
s
82pF
25.2
s
100pF
29.7
s
220pF
59.3
s
330pF
86.6
s
470pF
121.2
s
680pF
173
s
820pF
208
s
1nF
252
s
Soft-Start or Inrush Current Control
The LTC4212 monitors the load current by sensing the
voltage (V
CC
V
SENSE
) developed across an external
sense resistor (R
SENSE
) connected between the V
CC
and
SENSE pins. During the second timing cycle (see Normal
Operating Sequence) a soft-start circuit turns on the
external N-channel FET gradually to keep inrush currents
in check. The soft-start circuit monitors and servos the
voltage across R
SENSE
to 50mV by either connecting a
10
A pull-up current source to the GATE pin when the
voltage across R
SENSE
is less than 50mV or discharging it
with a 10
A pull-down current source when the voltage
rises above 50mV. Therefore, the inrush current from the
backplane supply is limited to:
I
LIMIT(SOFTSTART)
= 50mV/R
SENSE
(5)
For example, I
LIMIT(SOFTSTART)
= 5A when R
SENSE
= 0.01
.
Assuming that the voltage across the sense resistor does
not exceed 50mV, the voltage at the GATE pin rises at rate
given by:
V
GATE
Slew Rate = dV
GATE
/dt =10
A/C
GATE
(6)
where, C
GATE
= Power MOSFET gate input capacitance
(C
ISS
).
For example, an Si4410DY (a 30V N-channel power
MOSFET) exhibits an approximate C
GATE
of 3300pF at
13
LTC4212
4212f
OPERATIO
U
V
GS
= 10V. From Equation 6, the slew rate is calculated to
be 3.03V/ms.
The inrush current being delivered to the load while the
GATE pin is ramping depends on C
LOAD
and C
GATE
. The
external N-channel MOSFET acts as a source follower so
that its source (load) voltage ramps up at the same rate as
the GATE pin. The output current component for capacitor
charging is given by Equation 7:
I
INRUSH
= C
LOAD
dV
GATE
/dt
(7)
=10
A C
LOAD
/C
GATE
where, C
LOAD
is the total capacitance at the load side of the
MOSFET. For example, if C
GATE
= 3300pF and
C
LOAD
= 2000
F, the inrush current charging C
LOAD
is
6.06A. Note that the soft-start circuit will servo the inrush
to I
LIMIT(SOFTSTART)
or 5A in this example and dV
GATE
/dt
will be lower than calculated from Equation 6.
Frequency Compensation at Soft-Start
If the external MOSFET's gate input capacitance (C
ISS
) is
greater than 600pF, no external gate capacitor is required
at GATE to stabilize the internal current-limiting loop
during soft-start. Otherwise, connect a gate capacitor
between the GATE pin and ground to increase the total gate
capacitance to be equal to or above 600pF. The servo loop
that controls the external MOSFET during current limiting
has a unity-gain frequency of about 105kHz and phase
margin of 80
for external MOSFET gate input capaci-
tances of up to 2.5nF.
Electronic Circuit Breaker
The LTC4212 features an electronic circuit breaker func-
tion that protects against supply overvoltage, externally-
generated fault conditions, shorts or excessive load current
conditions and power good faults. If the circuit breaker
trips, the GATE pin is immediately pulled to ground, the
external N-channel MOSFET is quickly turned OFF and
FAULT is latched low.
The circuit breaker trips whenever the voltage across the
sense resistor exceeds two different levels, set by the
LTC4212's SLOW COMP and FAST COMP thresholds (see
Block Diagram). The SLOW COMP trips the circuit breaker
if the voltage across the SENSE resistor (V
CC
V
SENSE
=
V
CB
) is greater than 50mV for 18
s. The FAST COMP trips
the circuit breaker to protect against fast load overcurrents
if the transient voltage across the sense resistor is greater
than 150mV for 500ns.
The timing diagram of Figure 2 illustrates when the
LTC4212's electronic circuit breaker is armed. After the
first timing cycle, the LTC4212's FAST COMP is armed at
Time Point 6. This ensures that the system is protected
against a short-circuit condition during the second timing
cycle after C
LOAD
has been fully charged. At Time Point 8,
SLOW COMP is armed when the internal control loop is
disengaged.
The timing diagram in Figure 4 illustrates the operation of
the LTC4212 when the load current conditions exceed the
threshold of SLOW COMP (V
CB(SLOW)
> 50mV).
Circuit Breaker Reset
Referring to the Block Diagram, the ON pin drives two
internal comparators, COMP1 and COMP2. COMP1 is
referenced to 1.236V and has a hysterisis of 80mV.
COMP2 is referenced to 0.5V and has a hysterisis of 45mV.
The outputs of the two comparators drive an internal flip-
flop to generate a typical high and low ON pin threshold of
1.31V and 0.455V respectively.
If the voltage at the ON pin is driven below 0.455V for more
than 10
s, all internal control logic except the circuit
breaker is reset. A 200
A pull-down current source is
connected to the GATE pin to pull it down gradually.
Holding the ON pin below 0.455V for 120
s or longer,
resets the circuit breaker. Following reset, the ON pin must
be taken above 1.316V to start a power-up sequence.
Normal Operating Sequence
Figure 2 illustrates the normal power-up sequence for two
different applications. The PGI (RST) and PGF (RST)
waveforms are valid for applications which use the PGI pin
to monitor the RST output of a supply monitor IC. The PGI
(PGOOD) and PGF (PGOOD) waveforms refer to applica-
tions that tie the PGI pin to the PGOOD output
of a DC/DC converter. All other waveforms in Figure 2
are common to both applications. The PGI and PGF
waveforms for applications that connect PGI pin to the
14
LTC4212
4212f
Figure 2. Normal Power-Up, Power Good Glitch Filter and ECB Reset Sequences
CHECK FOR GATE < 0.2V
ON GOES LOW
GLITCH FILTER TRIPS BREAKER
CHECK FOR FAULT HIGH
LOGIC RESET
(200
A GATE PULLDOWN)
FAST COMP ARMED
SLOW COMP & POWER GOOD CIRCUIT ARMED
PGI SAMPLED
CIRCUIT BREAKER RESET
V
CC
V
CC
ON
V
REF
2V TO 34V
V
REF
TIMER
GATE
DC/DC
CONVERTER
OUTPUT
FAULT
PGT
PGI
(RST)
PGF
(RST)
PGI
(PGOOD)
PGF
(PGOOD)
4212 F02
1 2
3
4
5 6
7
8 9
10
11 12
13 14
15
16
17
18
19
20
21
POWER GOOD
TIME-OUT CYCLE
(C
PGT
)
NORMAL POWER-UP SEQUENCE
POWER GOOD GLITCH
FILTER SEQUENCE
ECB RESET
SEQUENCE
200ms
MONITOR DELAY
0.95V
0.65V
1ST TIMING
CYCLE (C
TIMER
)
1ST TIMING
CYCLE (C
TIMER
)
2ND TIMING
CYCLE (C
TIMER
)
SOFT-START
ACTIVE
1.236V
1.236V
OPERATIO
U
15
LTC4212
4212f
applications where PGI monitors the RST output of a
supply monitor like the LTC1326-2.5, the RST and there-
fore the PGI pins are held low for another 200ms until Time
Point 11 (see PGI (RST) waveform). At Time Point 12, the
power good circuit samples the PGI pin. During normal
power-up, PGI will go high before Time Point 12. The
power good circuit disables and resets the power good
timer and M12 is turned ON to pull PGT to ground. The
power good glitch filter is then enabled to monitor the
PGI pin.
Power Good Glitch Filter Sequence
The power good glitch filter sequence is also shown in
Figure 2 from Time Points 12 through 16. When the glitch
filter is enabled, M5, the internal N-channel FET that shorts
the PGF pin to GND is switched OFF whenever PGI is low.
This allows the C
PGF
capacitor to be charged by an internal
5
A current source towards 1.236V. If the PGF pin voltage
exceeds 1.236V, the power good circuit trips the circuit
breaker to latch the part off. Tying PGF to GND disables the
glitch filter and prevents the power good from tripping the
circuit breaker after Time Point 12.
For supply monitors such as the LTC1326-2.5, the glitch
filter is less useful. The comparators in the LTC1326-2.5
that monitor the DC/DC converters have a typical propaga-
tion delay of 13
s. If any of the monitored supplies leave
regulation for more than 13
s, the RST signal will be
pulled low until 200ms after all the supplies re-enter
regulation. The net effect is that the LTC1326-2.5 per-
forms the glitch filtering and rejects pulses shorter than
13
s. The PGOOD output of a DC/DC converter does not
have the 200ms delay of the LTC1326-2.5. Thus any low
PGOOD pulse will immediately cause C
PGF
to be charged
towards 1.236V (Time Points 13 and 14). C
PGF
values can
be selected to reject low pulses that are shorter than some
desired pulse width.
Some supply monitor ICs such as the LTC1727 provide
access to the outputs of comparators monitoring the DC/DC
converters as well as the RST output. The comparator
outputs track the converter output voltages. If the LTC4212
PGI pin is used to monitor the output of a comparator rather
than the RST output of the LTC1727, C
PGF
can be selected
to reject low pulses shorter than a desired pulse width.
comparator outputs of a supply monitor such as the
LTC1727 are similar to PGI (PGOOD) and PGF (PGOOD).
First Timing Cycle
When the PC board makes contact with the backplane
(Time Point 1), V
CC
starts to rise. While V
CC
< 2.23V, the
LTC4212 is in UVLO mode. The GATE pin is pulled to
ground by a 200
A current source to shut off the external
N-channel MOSFET and the TIMER, PGT and PGF pins are
all pulled low by internal N-channel FETs M6, M5 and M12.
When V
CC
rises above the UVLO threshold of 2.34V (Time
Point 2), the LTC4212 waits for the ON pin to go high ( >
1.316V) and checks that the GATE is low (V
GATE
< 0.2V)
before initiating the first timing cycle (Time Point 3).
The first timing cycle begins with the TIMER pin up at a rate
given by Equation 1. At Time Point 4 (the timing period
programmed by C
TIMER
), the TIMER pin voltage equals
V
TMR
= 1.236V. Next the TIMER pin is pulled down by M6
to Time Point 5 where V
TMR
= 0.2V. At Time Point 5, the
LTC4212 checks that the FAULT pin voltage is high (V
FAULT
> 1.236V) before initiating the second timing cycle. If
FAULT is forced low externally, the second timing cycle
will not start and the external N-channel FET stays OFF.
Second Timing Cycle
At the beginning of the second timing cycle (Time Point 6),
the LTC4212 FAST COMP is armed and the soft-start
circuit is enabled. The GATE pin is ramped up at a rate
given by Equation 6. If the inrush current from the backplane
supply (Equation 7) is large enough to cause the voltage
drop across the sense resistor to exceed 50mV, the soft-
start circuit activates to regulate the inrush current (Equa-
tion 5). The soft-start circuit continues to operate until
Time Point 8 when the TIMER pin voltage equals V
TMR
=
1.236V again. At Time Point 8, SLOW COMP is armed and
the power good circuit is enabled.
When the power good circuit is enabled, M12, the internal
N-channel FET shorting the PGT pin to ground is switched
OFF and the power good timer started. The DC/DC convert-
ers enter regulation at Time Point 10. In applications
where the PGI pin is connected to the PGOOD pin of a DC/
DC converter, PGI is pulled high shortly after the converter
enters into regulation (see PGI (PGOOD) waveform). In
OPERATIO
U
16
LTC4212
4212f
150mV, SLOW COMP trips the ECB (Time Point 10). If the
voltage across R
SENSE
jumps above 150mV for 500ns or
more, FAST COMP will trip the ECB.
When the ECB trips, the GATE pin is driven to GND
immediately to shut off the external N-channel FET and
disconnect the board from the backplane supply. The
FAULT pin is latched to a low state and the power good
circuit is reset. The PGT and PGF pins are shorted to
ground by internal N-channel FETs. In order to reset the
fault latch, the ON pin must be taken low for more than
120
s (Time Points 12 to 14). After that, taking the ON pin
high (Time Point 15) starts a new power-up sequence.
Autoretry Sequence
Once the circuit breaker trips, the LTC4212 can be config-
ured to autoretry that is attempt to reconnect the backplane
supply automatically. Both FAULT and ON pins are tied
together to an external pull-up resistor to V
CC
(R
AUTO
) and
to a delay capacitor (C
AUTO
) as shown in Figure 5.
Figure 6 shows two autoretry sequences caused by a
persistent short. When the circuit breaker trips (Time
Point 9), an internal N-channel FET at the FAULT pin is
turned on to pull the pin low. This discharges the autoretry
capacitor, C
AUTO
towards ground. When the ON pin volt-
age drops below 0.455V for 10
s (from Time Point 10),
internal logic is reset and a 200
A current source is
connected to the GATE pin. The GATE pin is already pulled
down to ground at Time Point 9. The circuit breaker is not
reset so that the FAULT pin continues to discharge C
AUTO
.
After the ON pin has dropped below 0.455V for more than
120
s (Time Point 11), the circuit breaker is reset. The
N-channel FET at the FAULT pin is switched off and the
pull-up resistor at the ON pin starts to charge C
AUTO
towards the upper 1.316V threshold of the ON pin. Once
the ON pin voltage rises above 1.316V, the first timing
cycle is started. The total cooling off period for the external
N-channel FET starts at Time Point 9 when the circuit
breaker trips to Time Point 15 when the second timing
cycle is started.
OPERATIO
U
Electronic Circuit Breaker (ECB) Reset Sequence
The ECB reset sequence is shown in Figure 2 from Time
Points 17 through 19. At Time Point 17, the ON pin is taken
low. Ten microseconds later at Time Point 18, the internal
logic is reset and a 200
A source is connected to the GATE
pin to pull the pin to ground. 120
s after ON goes low
(Time Point 19), the ECB is reset. When the ON pin is taken
high at Time Point 20 a new first timing cycle is started. If
the time from Time Point 17 to Time Point 18 is less than
120
s, the ECB is not reset and taking the ON pin high at
Time Point 20 will not start a new first timing cycle.
Power Good Timeout Fault Sequence
Figure 3 shows a power-up sequence in which the DC/DC
converters do not enter regulation on time and the power
good trips the ECB. The sequence is the same as for the
normal power-up in Figure 2 until Time Point 12 when the
power good timer times out and the PGI pin is sampled.
Since PGI is low, the power good circuit trips the ECB. The
GATE pin is pulled to ground immediately to disconnect
power to the board and the FAULT pin is latched to a
low state. The PGT and PGF pins are pulled to GND
internally by N-channel FETs. To reconnect the board to
the backplane supply, the ON pin must be taken low for at
least 120
s to reset the ECB and then high again to start
a new first timing cycle.
Overcurrent Fault Sequence
Figure 4 shows a power-up sequence with SLOW COMP
tripping the ECB. At the beginning of the second timing
cycle (Time Point 6), the GATE pin is connected to the soft-
start circuit and FAST COMP is armed but it does not
usually trip the ECB due to the action of the soft-start
circuit on the GATE pin. The soft-start circuit regulates the
voltage across the R
SENSE
resistor to 50mV. At Time
Point 8, the soft-start circuit is disconnected. A 10
A
current source pulls the GATE pin up and SLOW COMP is
armed. If a short occurs and the voltage across R
SENSE
jumps above 50mV for more than 18
s but is less than
17
LTC4212
4212f
Figure 3. Power Good Time-Out Fault and ECB Reset Sequence
CHECK FOR GATE < 0.2V
ON GOES LOW
CHECK FOR FAULT HIGH
LOGIC RESET
(200
A GATE PULLDOWN)
FAST COMP ARMED
SLOW COMP & POWER GOOD CIRCUIT ARMED
PGI SAMPLED
CIRCUIT BREAKER RESET
V
CC
V
CC
ON
V
REF
2.34V
V
REF
V
REF
TIMER
GATE
DC/DC
CONVERTER
OUTPUT
(RST)
DC/DC
CONVERTER
OUTPUT
(PGOOD)
FAULT
PGT
PGI
PGF
4212 F03
1 2
3
4
5 6
7
8 9
10
11 12
13
14
15
16
17
19
POWER GOOD
TIME-OUT CYCLE
(C
PGT
)
POWER GOOD TIMEOUT FAULT SEQUENCE
ECB RESET
SEQUENCE
< 200ms
0.95V
0.65V
1ST TIMING
CYCLE (C
TIMER
)
2ND TIMING
CYCLE (C
TIMER
)
SOFT-START
ACTIVE
V
OUT
V
OUT
OPERATIO
U
18
LTC4212
4212f
OPERATIO
U
Figure 4. Power-Up with Overcurrent, Slow Comparator Trips the Circuit Breaker
V
CC
V
CC
ON
V
REF
2.34V
V
REF
TIMER
GATE
DC/DC
CONVERTER
OUTPUT
V
CC
V
SENSE
FAULT
PGT
PGI
PGF
4212 F04
1
2
3
4
5
6
7
8
9
10 11
13
12
1415
16
POWER GOOD TIMER
ENABLED (C
PGT
)
0.95V
0.65V
2ND TIMING
CYCLE (C
TIMER
)
1ST TIMING
CYCLE (C
TIMER
)
1ST TIMING
CYCLE (C
TIMER
)
SOFT-START
ACTIVE
V
REF
V
CC
V
SENSE
= 50mV
> 50mV, >18
s
It consists of the time the FAULT pin takes to discharge
C
AUTO
(Time Points 9 to 10), the 120
s needed to reset the
circuit breaker (Time Points 9 to 11), the time it takes the
pull-up resistor at the ON pin to charge C
AUTO
above
1.316V (Time Points 11 to 12) and the elapsed time before
the external N-channel starts to conduct during the second
timing cycle (Time Points 12 to 16).
Sense Resistor Considerations
The fault current level at which the LTC4212's internal
electronic circuit breaker trips is determined by a sense
resistor connected between the LTC4212's V
CC
and SENSE
pins and two separate trip points. The first trip point is set
19
LTC4212
4212f
OPERATIO
U
Figure 5. LTC4212 Autoretry Application
+
V
CC
SENSE
LTC4212
9
1
10
2
3
8
7
10
F
+
10
F 2
3
1
5V
2.5V
1.5A
3.3V
1.5A
4212 F05
6
GATE
PGT
4
PGF
TIMER
C
TIMER
0.01
F
PGI
ON
V
CC
5V
GND
Z1 = SMAJ10A (TVS)
R
AUTO
1M
R
X
10
R
SENSE
0.007
EDGE
CONNECTOR
(MALE)
M1
Si4410DY
Z1
R4
10k
R6
2.1k
R5
10k
R
G
100
FAULT
GND
+
10
F
LT1963-2.5
C
PGT
180nF
C
PGF
18pF
C
X
10nF
BACKPLANE
CONNECTOR
(FEMALE)
5
+
10
F 2
3
1
+
10
F
LT1963-3.3
4
3
LTC1326-2.5
GND
V
CCA
1
V
CC3
6
RST
2
V
CC25
C
AUTO
2
F
Figure 6. Autoretry Sequence
V
CC
ON
V
REF
2.34V
TIMER
GATE
DC/DC
CONVERTER
OUTPUT
V
CC
V
SENSE
FAULT
PGT
PGI
PGF
4212 F06
1 2 3
4 5 6
7 8
10
9
11
12
13 14 15
16 17
18
19
POWER GOOD
TIMER ENABLED
(C
PGT
)
POWER GOOD
TIMER ENABLED
(C
PGT
)
0.95V
0.65V
0.95V
0.65V
2ND
TIMING
CYCLE (C
TIMER
)
1ST
TIMING
CYCLE (C
TIMER
)
1.316V
1.31V
0.455V
0.455V
2ND
TIMING
CYCLE (C
TIMER
)
1ST
TIMING
CYCLE (C
TIMER
)
SOFT-START ACTIVE
SOFT-START ACTIVE
V
REF
V
REF
V
REF
V
CC
V
SENSE
=
50mV
V
CC
V
SENSE
=
50mV
> 50mV, > 18
s
> 50mV, > 18
s
20
LTC4212
4212f
OPERATIO
U
by the SLOW COMP's threshold, V
CB(SLOW)
= 50mV, and
occurs should a load current fault condition exist for more
than 18
s. The current level at which the electronic circuit
breaker trips is given by Equation 8:
I
V
R
mV
R
TRIP SLOW
CB SLOW
SENSE
SENSE
(
)
(
)
=
=
50
(8)
The second trip point is set by the FAST COMP's threshold,
V
CB(FAST)
= 150mV, and occurs during fast load current
transients that exist for 500ns or longer. The current level
at which the circuit breaker trips in this case is given by
Equation 9:
I
V
R
mV
R
TRIP FAST
CB FAST
SENSE
SENSE
(
)
(
)
=
=
150
(9)
As a design aid, the currents at which electronic circuit
breaker trips for common values for R
SENSE
are shown in
Table 4.
Table 4. I
TRIP(SLOW)
and I
TRIP(FAST)
vs R
SENSE
R
SENSE
I
TRIP(SLOW)
I
TRIP(FAST)
0.005
10A
30A
0.006
8.3A
25A
0.007
7.1A
21A
0.008
6.3A
19A
0.009
5.6A
17A
0.01
5A
15A
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4212's
V
CC
and SENSE pins are strongly recommended. The
drawing in Figure 7 illustrates the correct way of making
connections between the LTC4212 and the sense resistor.
PCB layout should be balanced and symmetrical to mini-
mize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
The power rating of the sense resistor should accommo-
date steady-state fault current levels so that the compo-
nent is not damaged before the circuit breaker trips.
Table 5 in the Appendix lists sense resistors that can be
used with the LTC4212's circuit breaker.
Calculating Circuit Breaker Trip Current
For a selected R
SENSE
value, the nominal load current that
trips the circuit breaker is given by Equation 10:
IRC-TT SENSE RESISTOR
LR251201R010F
OR EQUIVALENT
0.01
, 1%, 1W
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
TO
V
CC
TO
SENSE
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
W
4212 F07
Figure 7. Making PCB Connections to the Sense Resistor
I
V
R
mV
R
TRIP NOM
CB NOM
SENSE NOM
SENSE NOM
(
)
(
)
(
)
(
)
=
=
50
(10)
The minimum load current that trips the circuit breaker is
given by Equation 11.
I
V
R
mV
R
TRIP MIN
CB MIN
SENSE MAX
SENSE MAX
(
)
(
)
(
)
(
)
=
=
40
(11)
where
R
R
R
SENSE MAX
SENSE NOM
TOL
(
)
(
)
=
+
1
100
The maximum load current that trips the circuit breaker is
given in Equation 12.
I
V
R
mV
R
TRIP MAX
CB MAX
SENSE MIN
SENSE MIN
(
)
(
)
(
)
(
)
=
=
60
(12)
where
R
R
R
SENSE MIN
SENSE NOM
TOL
(
)
(
)
=
1
100
21
LTC4212
4212f
OPERATIO
U
For example:
If a sense resistor with 7m
5% R
TOL
is used for current
limiting, the nominal trip current I
TRIP(NOM)
= 7.1A. From
Equations 11 and 12, I
TRIP(MIN)
= 5.4A and I
TRIP(MAX)
=
9.02A respectively.
For proper operation and to avoid the circuit breaker
tripping unnecessarily, the minimum trip current
(I
TRIP(MIN)
) must exceed the circuit's maximum operating
load current. For reliability purposes, the operation at the
maximum trip current (I
TRIP(MAX)
) must be evaluated
carefully. If necessary, two resistors with the same R
TOL
can be connected in parallel to yield an R
SENSE(NOM)
value
that fits the circuit requirements.
Power MOSFET Selection Criteria
To start the power MOSFET selection process, choose the
maximum drain-to-source voltage, V
DS(MAX)
, and the
maximum drain current, I
D(MAX)
of the MOSFET. The
V
DS(MAX)
rating must exceed the maximum input supply
voltage (including surges, spikes, ringing, etc.) and the
I
D(MAX)
rating must exceed the maximum short-circuit
current in the system during a fault condition. In addition,
consider three other key parameters: 1) the required gate-
source (V
GS
) voltage drive, 2) the voltage drop across the
drain-to-source on resistance, R
DS(ON)
and 3) the maxi-
mum junction temperature rating of the MOSFET.
Power MOSFETs are classified into two categories: stan-
dard MOSFETs (R
DS(ON)
specified at V
GS
= 10V) and
logic-level MOSFETs (R
DS(ON)
specified at V
GS
= 5V). The
absolute maximum rating for V
GS
is typically
20V for
standard MOSFETs. However, the V
GS
maximum rating
for logic-level MOSFETs ranges from
8V to
20V de-
pending upon the manufacturer and the specific part
number. The LTC4212's GATE overdrive as a function of
V
CC
is illustrated in the Typical Performance curves. Logic-
level MOSFETs are recommended for low supply voltage
applications and standard MOSFETs can be used for appli-
cations where supply voltage is greater than 4.75V.
Note that in some applications, the gate of the external
MOSFET can discharge faster than the output voltage
when the circuit breaker is tripped. This causes a negative
V
GS
voltage on the external MOSFET. Usually, the selected
external MOSFET should have a
V
GS(MAX)
rating that is
higher than the operating input supply voltage to ensure
that the external MOSFET is not destroyed by a negative
V
GS
voltage. In addition, the
V
GS(MAX)
rating of the
MOSFET must be higher than the gate overdrive voltage.
Lower
V
GS(MAX)
rating MOSFETs can be used with the
LTC4212 if the GATE overdrive is clamped to a lower
voltage. The circuit in Figure 8 illustrates the use of zener
diodes to clamp the LTC4212's GATE overdrive signal if
lower voltage MOSFETs are used.
V
CC
V
OUT
*USER SELECTED VOLTAGE CLAMP
(A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED)
1N4688 (5V)
1N4692 (7V): LOGIC-LEVEL MOSFET
1N4695 (9V)
1N4702 (15V): STANDARD-LEVEL MOSFET
4212 F08
R
SENSE
GATE
D2*
D1*
Q1
R
G
200
Figure 8. Optional Gate Clamp for Lower V
GS(MAX)
MOSFETs
The R
DS(ON)
of the external pass transistor should be low
to make its drain-source voltage (V
DS
) a small percentage
of V
CC
. At a V
CC
= 2.5V, V
DS
+ V
RSENSE
= 0.1V yields 4%
error at the output voltage. This restricts the choice of
MOSFETs to very low R
DS(ON)
. At higher V
CC
voltages, the
V
DS
requirement can be relaxed in which case MOSFET
package dissipation (P
D
and T
J
) may limit the value of
R
DS(ON)
. Table 6 lists some power MOSFETs that can be
used with the LTC4212.
For reliable circuit operation, the maximum junction tem-
perature (T
J(MAX)
) for a power MOSFET should not exceed
the manufacturer's recommended value. This includes
normal mode operation, start-up, current-limit and
autoretry mode in a fault condition. Under normal condi-
tions the junction temperature of a power MOSFET is given
by Equation 13:
MOSFET Junction Temperature,
T
J(MAX)
T
A(MAX)
+
JA
P
D
(13)
22
LTC4212
4212f
Table 5 lists some current sense resistors that can be used
with the circuit breaker. Table 6 lists some power MOSFETs
that are available. Table 7 lists the web sites of several
manufacturers. Since this information is subject to change,
please verify the part numbers with the manufacturer.
OPERATIO
U
where
P
D
= (I
LOAD
)
2
R
DS(ON)
JA
= junction-to-ambient thermal resistance
T
A(MAX)
= maximum ambient temperature
If a short circuit happens during start-up, the external
MOSFET can experience a big single pulse energy. This is
especially true if the applications only employed a small
gate capacitor or no gate capacitor at all. Consult the safe
operating area (SOA) curve of the selected MOSFET to
ensure that the T
J(MAX)
is not exceeded during start-up.
Using Staggered Pin Connectors
The LTC4212 can be used on either a printed circuit board
or on the backplane side of the connector. Printed circuit
board edge connectors with staggered pins are recom-
mended as the insertion and removal of circuit boards do
sequence the pin connections. Supply voltage and ground
connections on the printed circuit board should be wired
to the edge connector's long pins or blades. Control and
status signals (like FAULT and ON) passing through the
card's edge connector should be wired to short length pins
or blades.
PCB Connection Sense
There are a number of ways to use the LTC4212's ON pin
to detect whether the printed circuit board has been fully
seated in the backplane before the LTC4212 commences
a start-up cycle.
An example is shown in the schematic on the front page
of this data sheet. In this case, the LTC4212 is mounted
on the PCB and a 20k/10k resistive divider is connected to
the ON pin. On the edge connector, R1 is wired to a short
pin. Until the connectors are fully mated, the ON pin is held
low, keeping the LTC4212 in an off state. Once the
connectors are mated, the resistive divider is connected
to V
CC
, V
ON
> 1.316V and the LTC4212 begins a start-up
cycle.
PCB Layout Considerations
For proper operation of the LTC4212's circuit breaker
function, a 4-wire Kelvin connection to the sense resistors
is highly recommended. In Hot Swap applications where
load currents can reach 10A or more, narrow PCB tracks
exhibit more resistance than wider tracks and operate at
more elevated temperatures. Since the sheet resistance of
1 ounce copper foil is approximately 0.54m
/square,
track resistances add up quickly in high current applica-
tions. Thus, to keep PCB track resistance and temperature
rise to a minimum, PCB track width must be appropriately
sized. Consult Appendix A of LTC Application Note 69 for
details on sizing and calculating trace resistances as a
function of copper thickness.
In the majority of applications, it will be necessary to use
plated-through vias to make circuit connections from
component layers to power and ground layers internal to
the PC board. For 1 ounce copper foil plating, a good
starting point is 1A of DC current per via, making sure the
via is properly dimensioned so that solder completely fills
any void. For other plating thicknesses, check with your
PCB fabrication facility.
APPE DIX
U
Table 5. Sense Resistor Selection Guide
CURRENT LIMIT VALUE
PART NUMBER
DESCRIPTION
MANUFACTURER
1A
LR120601R050
0.05
0.5W 1% Resistor
IRC-TT
2A
LR120601R025
0.025
0.5W 1% Resistor
IRC-TT
2.5A
LR120601R020
0.02
0.5W 1% Resistor
IRC-TT
3.3A
WSL2512R015F
0.015
1W 1% Resistor
Vishay-Dale
5A
LR251201R010F
0.01
1.5W 1% Resistor
IRC-TT
10A
WSR2R005F
0.005
2W 1% Resistor
Vishay-Dale
23
LTC4212
4212f
Table 6. N-Channel Selection Guide
CURRENT LEVEL (A)
PART NUMBER
DESCRIPTION
MANUFACTURER
0 to 2
MMDF3N02HD
Dual N-Channel SO-8
ON Semiconductor
R
DS(ON)
= 0.1
, C
ISS
= 455pF
2 to 5
MMSF5N02HD
Single N-Channel SO-8
ON Semiconductor
R
DS(ON)
= 0.025
, C
ISS
= 1130pF
5 to 10
MTB50N06V
Single N-Channel DD Pak
ON Semiconductor
R
DS(ON)
= 0.028
, C
ISS
= 1570pF
10 to 20
MTB75N05HD
Single N-Channel DD Pak
ON Semiconductor
R
DS(ON)
= 0.0095
, C
ISS
= 2600pF
Table 7. Manufacturers' Web Sites
MANUFACTURER
WEB SITE
TEMIC Semiconductor
www.temic.com
International Rectifier
www.irf.com
ON Semiconductor
www.onsemi.com
Harris Semiconductor
www.semi.harris.com
IRC-TT
www.irctt.com
Vishay-Dale
www.vishay.com
Vishay-Siliconix
www.vishay.com
Diodes, Inc.
www.diodes.com
APPE DIX
U
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
MSOP (MS) 0603
0.53
0.152
(.021
.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 0.27
(.007 .011)
TYP
0.127
0.076
(.005
.003)
0.86
(.034)
REF
0.50
(.0197)
BSC
1 2 3 4 5
4.90
0.152
(.193
.006)
0.497
0.076
(.0196
.003)
REF
8
9
10
7 6
3.00
0.102
(.118
.004)
(NOTE 3)
3.00
0.102
(.118
.004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010)
0
6
TYP
DETAIL "A"
DETAIL "A"
GAUGE PLANE
5.23
(.206)
MIN
3.20 3.45
(.126 .136)
0.889
0.127
(.035
.005)
RECOMMENDED SOLDER PAD LAYOUT
0.305
0.038
(.0120
.0015)
TYP
0.50
(.0197)
BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
24
LTC4212
4212f
LT/TP 0304 1K PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2003
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear.com
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1421
Two Channels, Hot Swap Controller
Operates from 3V to 12V and Supports 12V
LTC1422
Single Channel, Hot Swap Controller
Operates from 2.7V to 12V
LT1640AL/LT1640AH
Negative Voltage Hot Swap Controller
Operates from 10V to 80V
LTC1642
Single Channel, Hot Swap Controller
Overvoltage Protection and Foldback Current Limit
LTC1643AL/LTC1643AH
PCI-Bus Hot Swap Controller
3.3V, 5V and
12V for PCI and CPCI
LTC1647
Dual Channel, Hot Swap Controller
Operates from 2.7V to 16.5V
LTC4210-1/LTC4210-2
Single Channel, Hot Swap Controller
Hot Swap Controller with Active Current Limiting
LTC4211
Single Channel, Hot Swap Controller
Overvoltage and Overcurrent Protection
LTC4230
Triple Channel, Hot Swap Controller
Triple Hot Swap Controller with Multifunction Current Control
LTC4241
PCI-Bus Hot Swap Controller
With 3.3V Auxiliary Standby Channel
LTC4251/LTC4251-1/
48V Voltage Hot Swap Controller
Negative Voltage Hot Swap Controller in SOT-23
LTC4251-2
LTC4252
48V Hot Swap Controller
48V Hot Swap Controller in 8-Pin or 10-Pin MSOP
LTC4253
Triple Power Supply Sequenced 48V Hot Swap Controller
48V Hot Swap Controller with Triple Supply Sequencing
in 16-Pin SSOP
LT4256-1/LT4256-2
Positive Voltage Hot Swap Controller
Operates from 10.8V to 80V, Autoretry/Latch Off
+
V
CC
SENSE
LTC4212
9
1
10
2
3
8
7
10
F
+
10
F 2
3
1
5V
2.5V
1.5A
3.3V
1.5A
4212 TA02
6
GATE
PGT
4
PGF
TIMER
C
TIMER
0.01
F
PGI
ON
V
CC
5V
GND
Z1 = SMAJ10A (TVS)
R
X
10
R
SENSE
0.007
EDGE
CONNECTOR
(MALE)
M1
Si4410DY
Z1
R4
10k
R6
2.1k
R5
10k
FAULT
GND
FAULT
+
10
F
LT1963-2.5
C
PGT
180nF
C
PGF
18pF
C
X
100nF
BACKPLANE
CONNECTOR
(FEMALE)
5
+
10
F 2
3
1
+
10
F
LT1963-3.3
4
3
LTC1326-2.5
GND
V
CCA
1
V
CC3
6
RST
2
V
CC25
R2
20k
R1 10k
R3
10k
TYPICAL APPLICATIO
U
Monitoring DC/DC Converters with the LTC1326-2.5 Supply Monitor
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