LTC4556
1
4556f
The LTC
4556 provides all necessary power control, level
translation and supervisory functions for a smart card or
S.A.M. card interface. The part contains a low noise charge
pump** plus LDO for generating V
CC
power, as well as all
necessary level shifting circuitry.
The card voltage can be set to either 1.8V, 3V or 5V. The
LTC4556 includes a card detection channel with automatic
debounce circuitry. To reduce wiring costs, the LTC4556
interfaces to a microcontroller via a simple 4-wire serial
interface. Multiple devices may be connected in daisy-
chain fashion so that the number of wires to the card
socket board is independent of the number of sockets.
Status data is returned over the same interface.
Extensive security features ensure proper deactivation
sequencing in the event of a supply fault or a smart card
electrical fault. The smart card pins can withstand greater
than 10kV ESD in-situ with no additional components.
The LTC4556 is available in a small, low profile (0.75mm),
4mm
4mm QFN package.
s
Handheld Payment Terminals
s
Pay Telephones
s
ATM Machines
s
POS Terminals
s
Computer Keyboards
s
Multiple S.A.M. Sockets
, LTC and LT are registered trademarks of Linear Technology Corporation.
s
Electrical Specifications Are ISO7816-3 and EMV
Compatible
s
Control/Status Serial Port May be Daisy-Chained
for Multicard Applications
s
Automatic Shutdown on Electrical Faults
s
Buck Boost Charge Pump Generates 5V, 3V or 1.8V
Outputs (Smart Card Classes A, B and C)
s
Automatic Level Translation
s
Dynamic Pull-Ups Deliver Fast Signal Rise Times*
s
Supervisory Functions Prevent Smart Card Faults
s
Low Operating Current: 250
A Typical
s
V
IN
: 2.7V to 5.5V
s
Ultralow Shutdown Current
s
>10kV ESD on Smart Card Pins
s
Small 24-Pin 4mm
4mm QFN Package
Smart Card Interface
with Serial Control
4-WIRE
COMMAND
INTERFACE
4-WIRE
CARD
INTERFACE
SMART CARD
C8
C4
I/O
RST
CLK
V
CC
18
17
16
15
14
13
19
20
12
9
11
6
1
10
8
2
3
4
5
21
22
23
24
DV
CC
V
BATT
GND
FAULT
D
IN
D
OUT
SCLK
LD
DATA
R
IN
SYNC
ASYNC
PRES
UNDERV
240k
LTC4556
1
F
1
F
4556 TA01
1
F
1
F
0.1
F
C
+
C
CPO
180k
INPUT
POWER
RST
5V/DIV
10
s/DIV
4556 G11.eps
Deactivation Sequence
I/O
5V/DIV
V
CC
5V/DIV
CLK
5V/DIV
*U.S. Patent No. 6,356,140
**U.S. Patent No. 6,411,531
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
LTC4556
2
4556f
V
BATT
, DV
CC
, CPO, FAULT,
UNDERV to GND ....................................... 0.3V to 6.0V
PRES, DATA, R
IN
, SYNC, ASYNC,
LD, D
IN
, SCLK to GND ............... 0.3V to (DV
CC
+ 0.3V)
I/O, CLK ....................................... 0.3V to (V
CC
+ 0.3V)
ORDER PART
NUMBER
T
JMAX
= 125
C,
JA
= 37
C/W
EXPOSED PAD (PIN 25) IS SGND.
MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
LTC4556EUF
ABSOLUTE AXI U
RATI GS
W
W
W
U
PACKAGE/ORDER I FOR ATIO
U
U
W
(Note 1)
ELECTRICAL CHARACTERISTICS
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
BATT
= 3.3V, DV
CC
= 3.3V unless otherwise noted.
I
CC
(Note 5) .......................................................... 65mA
V
CC
Short-Circuit Duration ............................... Indefinite
Operating Temperature Range (Note 4) .. 40
C to 85
C
Storage Temperature Range ................. 65
C to 125
C
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Power Supply
V
BATT
Operating Voltage
q
2.7
5.5
V
I
VBATT
Operating Current
V
CC
= 5V, I
CC
= 0
A
q
250
400
A
I
VBATT
Shutdown Current
No Card Present, V
CPO
= 0V
q
0.5
1.75
A
DV
CC
Operating Voltage
q
1.7
5.5
V
I
DVCC
Operating Current
q
5
25
A
I
DVCC
Shutdown Current
q
0.2
1.5
A
Charge Pump
R
OLCP
5V Mode Open-Loop
V
BATT
= 3.075V, I
CPO
= I
CC
= 60mA, (Note 3)
q
8.2
17
Output Resistance
CPO Turn On Time
I
CC
= 0mA, 10% to 90%
q
0.6
1.5
ms
25
TOP VIEW
UF PACKAGE
24-LEAD (4mm
4mm) PLASTIC QFN
DV
CC
DATA
R
IN
SYNC
ASYNC
FAULT
C8
C4
I/O
RST
CLK
V
CC
LD
SCLK
D
OUT
D
IN
UNDERV
PRES
NC
GND
C
V
BATT
C
+
CPO
24 23 22 21 20 19
7
8
9
10 11 12
6
5
4
3
2
1
13
14
15
16
17
18
UF PART
MARKING
4556
LTC4556
3
4556f
ELECTRICAL CHARACTERISTICS
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
BATT
= 3.3V, DV
CC
= 3.3V unless otherwise noted.
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Smart Card Supply
V
CC
Output Voltage
5V Mode, 0 < I
CC
< 60mA
q
4.65
5.0
5.35
V
3V Mode, 0 < I
CC
< 50mA
q
2.75
3.0
3.25
V
1.8V Mode, 0 < I
CC
< 30mA
q
1.65
1.8
1.95
V
V
CC
Turn On-Time
I
CC
= 0mA, 10% to 90%
q
0.8
1.5
ms
Undervoltage Detection
Relative to Nominal Output
q
9
5
2.5
%
Overcurrent Detection
q
60
110
150
mA
Smart Card Detection
Debounce Time (
PRES to
D7)
q
15
32
60
ms
PRES Pull-Up Current
V
PRES
= 0
q
1
2.5
A
Deactivation Time (
RST to V
CC
= 0.4V)
I
CC
= 0mA, C
VCC
= 1
F
q
100
250
s
CLK (Non-Bidirectional Modes)
Low Level Output Voltage (V
OL
), (Note 2)
Sink Current = 200
A
q
0.2
V
High Level Output Voltage (V
OH
), (Note 2)
Source Current = 200
A
q
V
CC
0.2
V
Rise/Fall Time, (Note 2)
Loaded with 50pF, 10% to 90%
q
16
ns
CLK Frequency, (Note 2)
q
10
MHz
RST, C4, C8
Low Level Output Voltage (V
OL
), (Note 2)
Sink Current = 200
A
q
0.2
V
High Level Output Voltage (V
OH
), (Note 2)
Source Current = 200
A
q
V
CC
0.2
V
Rise/Fall Time, (Note 2)
Loaded with 50pF, 10% to 90%
q
100
ns
I/O, CLK (CLK Specifications in Bidirectional Mode Only)
Low Level Output Voltage (V
OL
), (Note 2)
Sink Current = 1mA (V
DATA
= 0V or V
SYNC
= 0V)
q
0.3
V
High Level Output Voltage (V
OH
), (Note 2)
Source Current = 20
A (V
DATA
= V
DVCC
or
q
0.85 V
CC
V
V
SYNC
= V
DVCC
)
Rise/Fall Time, (Note 2)
Loaded with 50pF, 10% to 90%
q
500
ns
Short Circuit Current, (Note 2)
V
DATA
= 0V or V
SYNC
= 0V
q
5
10
mA
DATA, SYNC (SYNC Specifications in Bidirectional Mode Only)
Low Level Output Voltage (V
OL
)
Sink Current = 500
A (V
I/O
= 0V or V
CLK
= 0V)
q
0.3
V
High Level Output Voltage (V
OH
)
Source Current = 20
A (V
I/O
= V
CC
or V
CLK
= V
CC
)
q
0.8 DV
CC
V
Rise/Fall Time
Loaded with 50pF
q
500
ns
R
IN
, D
IN
, SCLK, LD, SYNC, ASYNC (SYNC Specifications for Non-Bidirectional Mode)
Low Input Threshold (V
IL
)
q
0.15 DV
CC
V
High Input Threshold (V
IH
)
q
0.85 DV
CC
V
Input Current (I
IH
/I
IL
)
q
1
1
A
D
OUT
Low Level Output Voltage (V
OL
)
Sink Current = 200
A
q
0.3
V
High Level Output Voltage (V
OH
)
Source Current = 200
A
q
DV
CC
0.3
V
UNDERV
Threshold
q
1.17
1.23
1.29
V
Leakage Current
V
UNDERV
= 3.3V
q
50
nA
LTC4556
4
4556f
ELECTRICAL CHARACTERISTICS
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
C. V
BATT
= 3.3V, DV
CC
= 3.3V unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: This specification applies to all three smart card voltage classes:
1.8V, 3V and 5V.
Note 3: R
OLCP
(2V
BATT
V
CPO
)/I
CPO
; V
CPO
will depend upon total load
(I
CC
) and minimum supply voltage V
BATT
. See Figure 6.
Note 4: The LTC4556E is guaranteed to meet performance specifications
from 0
C to 70
C. Specifications over the 40
C to 85
C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: Based on long term current density limitation.
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
V
BATT
SUPPLY VOLTAGE (V)
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY CURRENT (
A)
4556 G01
500
400
300
200
100
0
T
A
= 25
C
I
CC
= 0
A
V
CC
= 5V
V
CC
= 1.8V
V
CC
= 3V
TEMPERATURE (
C)
40
15
10
35
60
85
SHORT-CIRCUIT CURRENT (mA)
4556 G02
6.0
5.5
5.0
4.5
4.0
3.5
DV
CC
= V
BATT
= 3.3V
V
CC
= 5V
CLK
I/O
TEMPERATURE (
C)
40
15
10
35
60
85
OUTPUT RESISTANCE (
)
4556 G03
10
9
8
7
6
V
BATT
= 2.7V
V
CPO
= 4.9V
No Load Supply Current vs V
BATT
I/O and CLK Short-Circuit Current
vs Temperature
(CLK in Bidirectional Mode)
Charge Pump Open-Loop Output
Resistance vs Temperature
(2V
BATT
V
CPO
) / I
CPO
FAULT
Low Level Output Voltage (V
OL
)
Sink Current = 200
A
q
0.005
0.3
V
Leakage Current
V
FAULT
= 5.5V
q
1
A
Serial Port Timing
t
DS
D
IN
Valid to SCLK Setup
8
ns
t
DH
D
IN
Valid to SCLK Hold
8
ns
t
DD
D
OUT
Output Delay
C
LOAD
= 15pF
15
60
ns
t
L
SCLK Low Time
50
ns
t
H
SCLK High Time
50
ns
t
LW
LD Pulse Width
50
ns
t
CL
SCLK to LD
50
ns
t
LC
LD to SCLK
0
ns
LTC4556
5
4556f
TYPICAL PERFOR A CE CHARACTERISTICS
U
W
TEMPERATURE (
C)
40
15
10
35
60
85
LOAD CURRENT (mA)
4556 G04
140
130
120
110
100
90
80
V
BATT
= 3.3V
V
CC
= 1.8V, CPO = 4V
V
CC
= 3V, CPO = 5.5V
V
CC
= 5V, CPO = 5.5V
V
BATT
SUPPLY VOLTAGE (V)
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
DEBOUNCE TIME (ms)
4556 G05
50
45
40
35
30
25
T
A
= 85
C
T
A
= 25
C
T
A
= 40
C
TEMPERATURE (
C)
40
15
10
35
60
85
I/O LOW OUTPUT VOLTAGE (mV)
4556 G06
200
175
150
125
100
V
DATA
= V
SYNC
= 0V
I
OL
= 1mA
V
BATT
= 3V
V
CC
= 1.8V
V
CC
= 3V, 5V
LOAD CURRENT (mA)
EXTRA INPUT CURRENT (mA)
6
5
4
3
2
1
0
0.01
1
10
4556 G07
0.1
100
V
BATT
= 3.3V
T
A
= 25
C
V
CC
Overcurrent Shutdown
Threshold vs Temperature
Card Detection Debounce Time vs
V
BATT
Supply Voltage
Bidirectional Channel (I/O) Low
Output Level vs Temperature
Extra Input Current vs
Load Current (I
BATT
2I
CC
)
V
BATT
Shutdown Current vs
Supply Voltage
DV
CC
Shutdown Current vs Supply
Voltage
Charge Pump and LDO Activation
Deactivation Sequence
Data I/O Channel
V
CPO
5V/DIV
V
CC
5V/DIV
I/O
5V/DIV
1ms/DIV
4556 G10
10
s/DIV
4556 G11.eps
I/O
2V/DIV
DATA
2V/DIV
100ns/DIV
4556 G12
RST
5V/DIV
I/O
5V/DIV
V
CC
5V/DIV
CLK
5V/DIV
V
BATT
SUPPLY VOLTAGE (V)
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY CURRENT (
A)
4556 G08
3.0
2.5
2.0
1.5
1.0
0.5
0
T
A
= 85
C
T
A
= 25
C
T
A
= 40
C
V
DVCC
= V
BATT
V
DVCC
SUPPLY VOLTAGE (V)
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY CURRENT (
A)
4556 G09
1.0
0.8
0.6
0.4
0.2
0
T
A
= 25
C
T
A
= 85
C
T
A
= 40
C
V
BATT
= V
DVCC
LTC4556
6
4556f
CPO (Pin 12): Charge Pump. CPO is the output of the
charge pump. When the smart card requires power, the
charge pump will charge CPO to either 3.7V or 5.35V
depending on what smart card voltage is required. A low
impedance 1
F X5R or X7R ceramic capacitor is required
on CPO.
V
CC
(Pin 13): Card Socket. The V
CC
pin should be con-
nected to the V
CC
pin of the smart card socket. The
activation of the V
CC
pin is controlled by the serial port (see
Tables 1 and 2) and can be set to 0V, 1.8V, 3V or 5V.
CLK (Pin 14): Card Socket. The CLK pin should be con-
nected to the CLK pin of the smart card socket. The CLK
signal can be derived from either the SYNC input or the
ASYNC input depending on which type of card is being
accessed. The card type is selected via the serial port (see
Tables 1 and 3). In bidirectional mode, the CLK pin be-
comes an input/output with the microcontroller side
SYNC pin.
RST (Pin 15): Card Socket. This pin should be connected
to the RST pin of the smart card socket. The RST signal is
derived from the R
IN
pin. When the card is selected, its
RST pin follows R
IN
. When the card is deselected, the RST
pin holds the current value on R
IN
.
I/O (Pin 16): Card Socket. The I/O pin connects to the I/O
pin of the smart card socket. When the smart card is
selected, its I/O pin connects to the DATA pin. When the
smart card is deselected, its I/O pin returns to the idle
state (H).
C4, C8 (Pins 17, 18): Card Socket. These pins connect to
the C4 and C8 pins of synchronous memory cards on the
smart card socket. The signal for these pins is unidirec-
tional and can only be sent to the card. Data for C4 and C8
is transmitted via the DATA pin and may be selected in
place of I/O via the serial port (see Table 4). When either
C4 or C8 is selected, it will follow the DATA pin. When it is
deselected, it will remain latched at its current state.
PRES (Pin 19): Card Socket. The PRES pin is used to
detect the presence of a smart card. It should be connected
to a normally open detection switch on the smart card
acceptor's socket. This pin has a pull-up current source
on-chip so no external components are required.
PI FU CTIO S
U
U
U
DV
CC
(Pin 1): Power. Reference voltage for the control
logic.
DATA (Pin 2): Input/Output. Microcontroller side data I/O
pin. The DATA pin provides the bidirectional communica-
tion path to the smart card. The card may be selected to
communicate via the DATA pin. If several LTC4556s are
connected in parallel, the DATA pin can be made high
impedance by selecting neither card socket. The C4 and C8
synchronous card pins can be selected to connect to the
DATA pin via the serial port (see Table 4).
R
IN
(Pin 3): Input. The R
IN
pin supplies the RST signal to
the smart card. It is level shifted and transmitted directly
to the RST pin of a selected card. When the card is
deselected, the RST pin is latched at its current state.
SYNC (Pin 4): Input-Input/Output. The SYNC pin provides
the clock input for synchronous smart cards. When a
synchronous card is selected, its CLK pin follows SYNC
directly. When a synchronous card is deselected, the CLK
pin is latched at its current state. In bidirectional mode, the
SYNC pin becomes an input/output with the smart card
CLK pin.
ASYNC (Pin 5): Input. The ASYNC pin provides the clock
input for asynchronous cards and should be connected to
a free running clock. The clock signal to the smart card can
be a
1,
2,
4 or
8 version of the signal on ASYNC.
Asynchronous cards can also be placed in clock stop
mode with the clock stopped either high or low.
FAULT (Pin 6): Output. The FAULT pin can be used as an
interrupt to a microcontroller to indicate when a fault has
occurred. It is an open drain output, which is logically
equivalent to D4 . (See Table 1)
NC (Pin 7): No Connection to chip. May be grounded.
GND (Pin 8): Ground. Power ground for the chip. This pin
should be connected directly to a low impedance ground
plane.
C
, C
+
(Pins 9, 11): Charge Pump. Charge pump flying
capacitor pins. A 1
F X5R or X7R ceramic capacitor
should be connected from C
+
to C
.
V
BATT
(Pin 10): Power. Supply voltage for analog and
power sections of the LTC4556.
LTC4556
7
4556f
SCLK. D
OUT
can be connected directly to a microcontroller
or the D
IN
pin of another LTC4556 or LTC1955 for daisy
chained operation.
SCLK (Pin 23): Input. The SCLK pin clocks the serial port.
Each new data bit is received on the rising edge of SCLK.
SCLK should be left high during idle times and should not
be clocked when LD is low.
LD (Pin 24): Input. The falling edge of this pin loads the
current state of the shift register into the command regis-
ter. Command changes to the smart card will be updated
on the falling edge of LD. The rising edge of LD latches
status information into the shift register for the next read/
write cycle.
SGND (Pin 25): Exposed Pad. Must be soldered to PCB
Ground.
UNDERV (Pin 20): Input. The UNDERV pin provides
security by supplying a precision undervoltage threshold
for external supply monitoring. An external resistive volt-
age divider programs the desired undervoltage threshold.
Once UNDERV falls below 1.23V, the LTC4556 automati-
cally begins the deactivation sequence.
If external supply monitoring is not required, the UNDERV
pin should be connected to either V
BATT
or DV
CC
.
D
IN
(Pin 21): Input. Input for the serial port. Command
data is shifted into D
IN
synchronously with SCLK. D
IN
can
be connected directly to a microcontroller or the D
OUT
pin
of another LTC4556 or LTC1955 for daisy chained
operation.
D
OUT
(Pin 22): Output. Output for the serial port. Smart
card status data is shifted out of D
OUT
synchronously with
PI FU CTIO S
U
U
U
BLOCK DIAGRA
W
C4
C8
I/O
RST
CLK
V
CC
V
BATT
DV
CC
GND
CHARGE PUMP
FAULT
UNDERV
1.23V
PRES
4556 BD
SMART
CARD
SOCKET
DIGITAL
SUPPLY
SMART
CARD
COMMUNICATIONS
SERIAL PORT
COMMAND/STATUS
DATA
C
+
C
CPO
+
RESET
CONTROL
LOGIC
STATUS DATA
COMMAND LATCH
SHIFT REGISTER
+
D
IN
D
OUT
SCLK
LD
CLOCK
CONTROL
LOGIC
CHARGE
PUMP
DATA
ASYNC
SYNC
R
IN
24
23
22
21
3
4
5
2
6
1
20
19
15
14
18
17
13
11
9
8
10
12
LDO
16
LTC4556
8
4556f
Serial Port
The microcontroller compatible serial port provides all of
the command and control inputs for the LTC4556 as well
as the status of the smart card. Data on the D
IN
input is
loaded on the rising edge of SCLK. D7 is loaded first and
D0 last. At the same time the command bits are being
shifted into the D
IN
input, the status bits are being shifted
out of the D
OUT
output. The status bits are presented to
D
OUT
on the rising edge of SCLK. Once all bits have been
clocked into the shift register, the command data is loaded
into the command latch by bringing LD low. At this time
the command latch is updated and the LTC4556 will begin
to act on the new command set. When LD is low, the shift
register is transparent to the status data of the smart card
channel. The status data is latched into the shift register on
the rising edge of LD. SCLK should be held in the high state
when idle and should only be clocked when LD is high.
Likewise LD should only be brought high when SCLK is
high. Figure 2 shows the operation of the serial port.
Multiple LTC4556s may be daisy chained together by
connecting the D
OUT
pin of one LTC4556 to the D
IN
pin of
another. Figure 7 shows an example of an LTC4556 daisy
chained together with LTC1955s.
The maximum clock rate for the serial port is 10MHz.
The serial port controls the following parameters of the
smart card socket:
Selection/deselection of the smart card
V
CC
voltage level of the card (5V/3V/1.8V/0V)
Clock mode of the card (synchronous, asynchronous
or bidirectional)
Operating mode of asynchronous cards (clock stop
high, low,
1,
2,
4 or
8)
Selection of the I/O, C4 or C8 pins
The serial port provides the following status data:
It indicates the presence or absence of the smart card.
It indicates the readiness of the smart card V
CC
supply.
Communication with the smart card is disabled until its
power supply voltage has reached the final value.
It indicates fault status. In the event of an electrical or
ATR fault, the fault is reported. For electrical faults, the
LTC4556 will automatically deactivate the smart card.
Table 1 illustrates the command inputs and status outputs
associated with each bit of the serial data word.
Three voltage options are available from the LTC4556: 5V,
3V and 1.8V. Bits D0, D1 determine which voltage is
selected. Setting both control bits to 0 deactivates the card
and sets the smart card supply voltage to 0V. Table 2
shows the operation of the supply control bits.
The CLK pin to the smart card can be programmed for
various modes. Both synchronous and asynchronous
cards are supported. There are several options available
with asynchronous cards. Table 3 shows how all clock
options are obtained using bits D5D7.
Figure 2. Serial Port Timing Diagram
D
IN
SCLK
LD
X
D0
D7
X
D1
D
OUT
D7 FROM
INPUT
D0
D7
4556 F02
D6
D5
D7
D1
t
LC
t
DH
t
DD
t
DS
t
H
t
L
t
LW
t
CL
D6
D2
OPERATIO
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LTC4556
9
4556f
To receive status data from the serial port, a read/write
operation must be performed. When polling for the pres-
ence of a smart card, the input word may be set to $00
since this is the shutdown command for the LTC4556.
Data Channel
The data channel is level shifted to the appropriate V
CC
voltages at the I/O pin.
An NMOS pass transistor performs the level shifting. The
gate of the NMOS transistor is biased such that the
transistor is completely off when both sides have relin-
quished the channel. If one side of the channel asserts an
L, then the transistor will convey the L to the other side.
OPERATIO
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Table 3. Clock Options
D7
D6
D5
CLOCK MODE
0
0
0
Synchronous Mode
0
0
1
Bidirectional Mode
0
1
0
Asynchronous Stop Low
0
1
1
Asynchronous Stop High
1
0
0
Asynchronous
1
1
0
1
Asynchronous
2
1
1
0
Asynchronous
4
1
1
1
Asynchronous
8
Table 2. V
CC
and Shutdown Options
D1
D0
STATUS
0
0
V
CC
= 0V (Shutdown)
0
1
V
CC
= 1.8V
1
0
V
CC
= 3V
1
1
V
CC
= 5V
Table 1. Serial Port Commands
STATUS OUTPUT
BIT
COMMAND INPUT
0
D0
V
CC
Options
0
D1
(See Table 2)
0
D2
Card Select/Deselect
0
D3
Card Communications
Card Electrical Fault
D4
Options (See Table 4)
Card ATR Fault
D5
Card Clock Options
Card V
CC
Ready
D6
(See Table 3)
Card Present
D7
Table 4. Communications Options
D4
D3
COMMUNICATION MODE
0
0
Nothing Selected
0
1
C4 Connected to DATA Pin
1
0
C8 Connected to DATA Pin
1
1
I/O Connected to DATA Pin
Note that current passes from the receiving side of the
channel to the transmitting side. The low output voltage of
the receiving side will be dependent upon the voltage at the
transmitting side plus the IR drop of the pass transistor.
When a card socket is selected, it becomes a candidate to
drive data on the DATA pin and likewise receive data from
the DATA pin. When a card socket is deselected, the
voltage on its I/O pin will return to the idle state (H) and the
DATA side of that channel will become high impedance.
The LTC4556 includes provision for unidirectional com-
munication with the C4 and C8 pins of the smart card. The
C4, C8 and I/O pins are individually multiplexed to the
DATA pin using bits D3 and D4 as shown in Table 4.
Dynamic Pull-Up Current Sources
The current sources on the bidirectional pins (DATA, I/O)
are dynamically activated to achieve a fast rise time with a
relatively small static current. Once a bidirectional pin is
relinquished, a small start up current begins to charge the
node. An edge rate detector determines if the pin is
released by comparing its slew rate with an internal
reference value. If a valid transition is detected, a large
pull-up current enhances the edge rate on the node. The
higher slew rate corroborates the decision to charge the
node thereby affecting a dynamic form of hysteresis.
Figure 3. Dynamic Pull-Up Current Sources
+
dv
dt
V
REF
LOCAL
SUPPLY
BIDIRECTIONAL
PIN
4556 F03
I
START
LTC4556
10
4556f
Clock Channel
As described in the section Serial Port, the LTC4556
supports both synchronous and asynchronous smart
cards. When bits D5-D7 are set to 0s, the clock channel is
in synchronous mode.
In synchronous mode, the CLK pin follows the SYNC pin
for a channel that is selected. If the channel is deselected
(via the serial port) the CLK line is latched at its current
value.
When control bits D7, D6 and D5 are set to 0, 0 and 1
respectively, the clock channel is in bidirectional mode.
This mode permits clock stretching when communicating
with bidirectional cards. The bidirectional level translation
circuit is identical to the I/O-DATA circuit. A low can be
asserted from either the SYNC pin or the CLK pin and the
other pin will follow. The low can be "handed off" to affect
clock stretching if both sides assert at the same time. It will
not run as fast as the unidirectional synchronous or
asynchronous modes but does employ accelerating pull-
up sources on both sides for maximum clock rate.
In asynchronous mode the CLK pin follows either the
ASYNC pin (
1 mode) or a divided version of this pin. The
CLK pin can also be stopped high or low. The available
divider ratios include
2,
4 and
8. When switching
between divider ratios, the internal selection circuitry
ensures that no spikes or glitches appear on the CLK pin.
Consequently, it may take up to 8 clock pulses for the clock
frequency change command to take affect. Synchroniza-
tion circuitry ensures that no glitches occur when entering
or exiting one of the stop modes. For example, when
entering Stop Low mode, the selection circuitry waits for
the next falling edge of the CLK signal to make the change.
Likewise if Stop High is selected it will occur on the next
rising edge.
Deselection of an asynchronous card does not affect its
CLK pin. Its clock can be started, stopped or its divider
ratio changed at any time.
To clean up the duty cycle of the incoming clock in
asynchronous applications, any of the clock divider modes
2,
4 or
8 will yield a very nearly 50% duty cycle.
Additional synchronization circuitry prevents glitches from
occurring when switching between synchronous mode
and asynchronous mode. Because of this circuitry, two
edges (a falling edge followed by a rising edge) are
necessary at the CLK pin to switch modes from asynchro-
nous to synchronous. For example, if clock stop mode is
engaged, the clock channel will not change modes until
clock stop mode is disengaged.
Both SYNC and ASYNC inputs are independently level
shifted to the appropriate voltage for the CLK pin (5V, 3V,
1.8V).
Reset Channel
When the card is selected, the reset channel provides a level
shifted path from the R
IN
pin to the RST pin. When the card
is deselected its RST pin is latched at the current value of
R
IN
.
Smart Card Detection Circuit
The PRES pin is used to detect the presence of a smart
card. An automatic debounce circuit waits until a smart
card has been present for a continuous period of typically
32ms. Once a valid card indication exists, the status bit is
updated and may be polled by cycling data through the
serial port. The D
OUT
pin (equivalent to D7) of the serial
port can be used to indicate the presence of a card in real
time if LD is held low.
The PRES pin has a built-in pull-up current source so no
external components are required for switch detection.
The pull-up current source is designed to have a small
current when the pin voltage is below approximately 1V
but somewhat higher current when the pin voltage reaches
1V. This helps maintain low power dissipation when a card
is present and yet fast response time to a card removal.
Activation/Deactivation
For maximum flexibility, the activation sequencing of the
smart card is left to the application programmer. However,
deactivation can be achieved either manually or automati-
cally. An electrical fault condition will trigger the automatic
deactivation.
OPERATIO
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LTC4556
11
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The built-in deactivation sequence can be executed via the
serial port simply by setting the control bits D0 and D1
to 0. The deactivation sequence is outlined below.
1. The RST pin is immediately brought low.
2. The deactivation of the CLK pin depends upon which
type of card is used:
If the smart card was set to asynchronous mode then
the CLK pin will be latched low on its next falling edge.
If no falling edges occur within 5
s (min) then the CLK
line is forced low.
If the smart card was set to synchronous mode then the
CLK pin is immediately latched at its current value
(either high or low) and then forced low after a duration
of 5
s (min). During the 5
s timeout period, changes
on SYNC will be ignored.
3. The I/O, C4 and C8 pins are brought low.
4. The V
CC
pin is brought low.
Upon activation, to comply with relevant smart card stan-
dards, none of the smart card signal pins will be allowed
to go high before the smart card supply voltage (V
CC
) has
reached its final value.
Electrical Fault Detection
Several types of faults are detected by the LTC4556. They
include V
CC
undervoltage, V
CC
overcurrent, CLK, RST, C8,
C4 short circuit, card removal during a transaction, failed
answer to reset (ATR), supply undervoltage or UNDERV
and chip overtemperature. To prevent false errors from
plaguing the microcontroller, the electrical faults are acted
upon only after a 5
s (min) timeout period. Card removal
during transaction faults initiate the deactivation sequence
immediately.
V
CC
undervoltage faults are determined by comparing the
actual output voltage with the internal reference voltage. If
the output is more than ~5% below its set point for the
entire timeout period, the fault is reported and the deacti-
vation sequence is initiated.
V
CC
overcurrent faults are detected by comparing the
output current of the LDOs with an internal reference level.
If the current of the LDO is more than 110mA (typ) for the
entire timeout period, the fault is reported and the deacti-
vation sequence is initiated.
CLK and RST faults are detected by comparing the outputs
of these pins with their expected signals. If the signal on
a pin is incorrect for the entire timeout period, the fault is
reported and the deactivation sequence is initiated.
The clock channel is a special case. Since it can have a free
running clock, the error indication is accumulated over a
longer period of time without being cleared. Even though
the clock may be running, an error will still be detected.
An overtemperature fault is detected by sensing the junc-
tion temperature of the IC. If the junction temperature
exceeds approximately 150
C for the entire timeout
period, the fault is reported by setting the fault bit (D4) and
the deactivation sequence is initiated.
A card removal fault is determined as soon as the PRES pin
is high. Once this occurs the fault is reported and the
deactivation sequence is initiated.
If no card is present, and the application software attempts
to power up a card socket, an automatic fault will result.
Short circuits on the I/O line will not be detected by the fault
detection hardware; however, a short circuit from I/O to
V
CC
will be compliant with the maximum current limits set
by applicable standards (<15mA). The same is true of the
CLK pin when it is set to bidirectional mode.
Answer to Reset (ATR) Fault Detection
Answer to Reset faults are detected by an internal counter
that is started once the RST line goes high. If the DATA pin
remains high for 40,000 clock cycles, the ATR fault bit is
set in the serial port's status register (see Table 1).
An ATR fault can not occur if the clock mode is set to
synchronous. ATR faults will only occur for asynchronous
smart cards.
OPERATIO
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LTC4556
12
4556f
ATR faults are cleared by bringing the RST pin low via R
IN
.
An ATR fault will not automatically deactivate the smart
card. It is the application programmer's responsibility to
check the status register for ATR faults and deactivate the
smart card in accordance with smart card standards.
Generally, the application has 50ms (EMV 2.1.3.1, 2.1.3.2)
from the 40,000th clock pulse to deactivate the card.
Once the LTC4556 receives the deactivation command, it
will shut down the smart card in less than 250
s.
OPERATIO
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Using the FAULT Pin
The FAULT pin can be used as an interrupt to a microcon-
troller. It is an open-drain output and generally requires a
pull-up resistor. The FAULT pin will go low when an
electrical fault occurs. The FAULT pin is logically equiva-
lent to D4 (see Table 1).
LTC4556
13
4556f
10kV ESD Protection
All smart card pins (CLK, RST, I/O, C4, C8 and V
CC
) can
withstand over 10kV of human body model ESD in-situ. In
order to ensure proper ESD protection, careful board
layout is required. The GND pin should be tied directly
to a ground plane. The multilayer ceramic chip V
CC
capaci-
tor should be located very close to the V
CC
pin and tied
immediately to the ground plane.
Capacitor Selection
Warning: A polarized capacitor such as tantalum or alumi-
num should never be used for the flying capacitor since its
voltage can reverse upon start up of the LTC4556. Low
ESR ceramic capacitors should always be used for the
flying capacitor.
A total of four capacitors are required to operate the
LTC4556. An input bypass capacitor is required at V
BATT
and DV
CC
. An output bypass capacitor is required on the
smart card V
CC
pin. A charge pump flying capacitor is
required from C
+
to C
and a charge storage capacitor is
required on the charge pump out pin CPO.
To prevent excessive noise spikes due to charge pump
operation, low ESR (equivalent series resistance) multi-
layer ceramic chip capacitors are strongly recommended.
There are several types of ceramic capacitors available
each having considerably different characteristics. For
example, X7R/X5R ceramic capacitors have excellent volt-
age and temperature stability but relatively low packing
density. Y5V ceramic capacitors have apparently higher
packing density but poor performance over their rated
voltage or temperature ranges. Under certain voltage and
temperature conditions Y5V and X7R/X5R ceramic ca-
pacitors can be compared directly by case size rather than
specified value for a desired minimum capacitance.
Placement of the capacitors is critical for correct operation
of the LTC4556. Because the charge pump generates large
current steps, all of the capacitors should be placed as
close to the LTC4556 as possible. The low impedance
APPLICATIO S I FOR ATIO
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nature of multilayer ceramic chip capacitors will minimize
voltage spikes but only if the power path is kept very short
(i.e., minimum inductance). The V
BATT
node should be
especially well bypassed. The capacitor for this node
should be directly adjacent to the QFN package. The CPO
and flying capacitors should be very close as well. The
LTC4556 can tolerate more distance between the LDO
capacitor and the V
CC
pin.
Figure 4 shows an example of a tight printed circuit board
layout using single layer copper. For best performance a
multilayer board can be used and should employ a solid
ground plane on at least one layer.
The following capacitors are recommended for use with
the LTC4556:
TYPE
VALUE
CASE SIZE
MURATA P/N
BATT, CPO,
X5R
1
F
0603
GRM39 X5R 105K 6.3
C
FLY
, V
CC
CDV
CC
X5R
0.1
F
0402
GRM36 X5R 104K 10
V
CC
GND
V
BATT
CPO
4556 F04
Figure 4. Optimum Single Layer PCB Layout
LTC4556
14
4556f
Daisy-Chained Operation
For applications requiring more than one card socket, the
serial port of the LTC4556 is designed to be easily daisy-
chained. The D
OUT
pin of one LTC4556 can be connected
directly to the D
IN
pin of another LTC4556 or LTC1955.
Rather than sending one 8-bit byte before asserting LD,
the microcontroller should send one 8-bit byte per device.
LD should only be asserted after all devices have been
updated. Figure 7 shows an LTC4556 cascaded in daisy
chain fashion with two LTC1955s. In this case the
microcontroller would write five 8-bit bytes before assert-
ing the LD pin.
Interfacing to a Microcontroller
The serial port of the LTC4556 can be connected directly
to a 68HC11 style microcontroller's serial port. The micro-
controller should be configured as the master device and
its clock's idle state should be set to high (MSTR = 1,
CPOL = 1 and CPHA = 0 for the MC68HC11 family).
Figure 5 shows the recommended configuration and di-
rection of data flow. Note that an additional I/O line is
necessary for LD to load the data once it has shifted around
the loop. Command data is latched into the command
register on the falling edge of the LD signal. The LTC4556
will begin to act on new command data as soon as LD goes
low. Any general purpose microcontroller I/O line can be
configured to control the LD pin.
The status of the LTC4556 is returned over the serial port.
Status data is latched into the shift register on the rising
edge of the LD pin. Whenever the system is waiting for
status data from the LTC4556, its LD pin should be held
low.
Figure 5. Microcontroller Interface
CARD
4556 F05
D
IN
D
OUT
SCLK
LD
LTC4556
MOSI
MISO
SCK
I/O
CONTROLLER
APPLICATIO S I FOR ATIO
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15
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Asynchronous Card Detection
Since the shift register is transparent when LD is held
low, D
OUT
is the same as D7. Recall from Table 1 that D7
indicates the status of the card detection channel. Thus
it is not necessary to perform an entire read/write opera-
tion to determine the card detection status. With LD low,
D
OUT
can be used to generate a real time card detection
interrupt.
Using the UNDERV Pin
The UNDERV pin can be used to add protection against a
supply undervoltage fault. By using two external program-
ming resistors, the undervoltage detection can be set to an
arbitrary level (Figure 8). To ensure that the smart card is
properly shut down, there must be sufficient energy
available in the input bypass capacitor to run it until the
deactivation cycle begins. It can take approximately 30
s
from the detection of a fault until the deactivation se-
quence begins. It is desirable to maintain the V
BATT
supply
at 2.7V or greater during this period.
Consider the following (worst-case) example:
1) The UNDERV pin is programmed to trip below 3.1V.
2) It is possible to have the card activated at 5V and
drawing 60mA.
Since the output voltage is programmed to 5V, the charge
pump will be acting as a voltage doubler. With the card
drawing 60mA, the input current will be 2 (60mA)
or about 120mA. Allowing the V
BATT
supply to droop
from 3.1V to 2.7V during the 30us timeout period
the input capacitance would need to be at least
120mA/[(3.1V 2.7V)/30
s] or 9
F.
Zero Shutdown Current
Although the LTC4556 is designed to have very low
shutdown current it can still draw over a microampere on
both DV
CC
and V
BATT
when in shutdown. For applications
that require virtually zero shutdown current, the DV
CC
pin
can be grounded. This will reduce the V
BATT
current to well
under a single microampere. Internal logic ensures that
the LTC4556 is in shutdown when DV
CC
is grounded.
Note, however, that all of the logic signals that are refer-
enced to DV
CC
(D
IN
, SCLK, LD, DATA, R
IN
, SYNC and
ASYNC) will have to be at 0V as well to prevent ESD diodes
to DV
CC
from being forward biased.
Operation at Higher Supplies
If a 5.5V to 6V supply voltage is available, it is possible to
achieve some power savings by overriding the charge
pump. The higher supply can be connected directly to the
CPO pin. As long as the voltage on CPO is higher than that
at which it ordinarily regulates (5.35V or 3.7V depending
on voltage selections) the charge pump's oscillator will
not run. This configuration can give considerable power
savings since the charge pump is not being used.
APPLICATIO S I FOR ATIO
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16
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A voltage source is still needed on both DV
CC
and V
BATT
in
this configuration. Recall that DV
CC
sets the logic refer-
ence level for all the control and smart card communica-
tion pins. The voltage on V
BATT
can be any convenient level
that meets the parameters in the Electrical Characteristics
table.
The 5.5V to 6V supply can be left permanently connected
to CPO but there will be approximately 5
A of current flow
into CPO when the LTC4556 is in shutdown.
Charge Pump Strength
Under low V
BATT
conditions, the amount of current avail-
able to the smart card is limited by the charge pump.
Figure 6 shows how the LTC4556 can be modeled as a
Thevenin equivalent circuit to determine the amount of
current available given the effective input voltage, 2V
BATT
and the effective open-loop output resistance, R
OLCP
.
From Figure 6, the available current is given by:
I
V
V
R
CC
BATT
CPO
OLCP
2
R
OLCP
is dependent on a number of factors including the
switching term, 1/(f
OSC
C
FLY
), internal switch resis-
tances and the nonoverlap period of the switching circuit.
However, for a given R
OLCP
, the minimum CPO voltage can
be determined from the following expression:
V
V
I
R
CPO
BATT
CC
OLCP
2
(
)
The LDO has been designed to meet all applicable smart
card standards for V
CC
with V
CPO
as low as 5.13V. Given
this information, trade-offs can be made by the user with
regard to total consumption (I
CC
) and minimum supply
voltage.
Changing the Smart Card Supply Voltage
Although the LTC4556 control system will allow the smart
card voltage to be changed from one value to the next
without an interim power down, this is not recommended.
When changing from a higher voltage to a lower voltage
there will generally not be a problem; however, changing
from a lower voltage to a higher voltage can result in both
an undervoltage condition or an overcurrent condition.
The likely result is that the LTC4556 will automatically
deactivate. Applicable smart card standards specify that
the smart card supply be powered to zero before applying
a new voltage.
Compliance Testing
Inductance due to long leads on type approval equipment
can cause ringing and overshooot that leads to testing
problems. Small amounts of capacitance and damping
resistors can be included in the application without com-
promising the normal electrical performance of the
LTC4556 or smart card system. Generally a 100
resistor
and a 20pF capacitor will accomplish this as shown in
Figure 9.
APPLICATIO S I FOR ATIO
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+
LDO
2V
BATT
4556 F06
CPO
R
OLCP
V
CC
Figure 6. Equivalent Open-Loop Circuit
LTC4556
17
4556f
Figure 7. An LTC4556 and Two LTC1955s Daisy Chained Together
4-WIRE
COMMAND
INTERFACE
4-WIRE
CARD
INTERFACE
SMART CARD
LTC4556
1
F
1
F
1
F
D
IN
D
OUT
SCLK
LD
DATA
R
IN
SYNC
ASYNC
CPO
INPUT
POWER
FAULT
V
BATT
GND
DV
CC
UNDERV
FAULT
PRES
C
+
C
VENDOR CARD
VENDOR CARD
LTC1955
4.7
F
D
IN
D
OUT
SCLK
LD
DATA
R
IN
SYNC
ASYNC
CPO
V
BATT
GND
DV
CC
UNDERV
FAULT
VENDOR CARD
VENDOR CARD
4556 F07
LTC1955
4.7
F
D
IN
D
OUT
SCLK
LD
DATA
R
IN
SYNC
ASYNC
CPO
V
BATT
GND
DV
CC
UNDERV
FAULT
4.7
F
4.7
F
10
8
12, 13
9, 10
12, 13
9, 10
1
19
6
20
24
23
24
23
1
21
22
23
24
2
3
4
5
1
27
28
26
25
29
30
32
31
9
11
1
F
PRES A
PRES B
C
+
C
21
2
11
14
1
F
PRES A
PRES B
C
+
C
21
2
11
14
27
28
26
25
29
12
15
15
30
32
31
APPLICATIO S I FOR ATIO
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APPLICATIO S I FOR ATIO
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SMART
CARD
SOCKET
I/O
CLK
RST
V
CC
C7
C3
C2
C1
C5
LTC4556
100
100
100
1
F
0.1
F
20pF
4556 F09
20pF
20pF
Fiugre 9. Additional Components for Improved Compliance Testing
20
LTC4556
4556 F08
R2
R1
MAIN SUPPLY
V
TRIP
= 1.23V (1 + R1/R2)
UNDERV
Figure 8. Setting the Undervoltage Trip Point
LTC4556
19
4556f
PACKAGE DESCRIPTIO
U
UF Package
24-Lead Plastic QFN (4mm
4mm)
(Reference LTC DWG # 05-08-1697)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
4.00
0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)--TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.38
0.10
24
0.23 TYP
(4 SIDES)
23
1
2
BOTTOM VIEW--EXPOSED PAD
2.45
0.10
(4-SIDES)
0.75
0.05
R = 0.115
TYP
0.25
0.05
0.50 BSC
0.200 REF
0.00 0.05
(UF24) QFN 1103
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70
0.05
0.25
0.05
0.50 BSC
2.45
0.05
(4 SIDES)
3.10
0.05
4.50
0.05
PACKAGE OUTLINE
LTC4556
20
4556f
PART NUMBER
DESCRIPTION
COMMENTS
LTC1555L/LTC1555L-1.8
1MHz, SIM Power Supply and Level Translator
V
IN
: 2.6V to 6.6V, V
OUT
= 1.8V/3V/5V, I
Q
= 32
A,
for 1.8V/3V/5V SIM Cards
I
SD
< 1
A, SSOP16
LTC1555/LTC1556
650kHz, SIM Power Supply and Level Translator
V
IN
: 2.7V to 10V, V
OUT
= 3V/5V, I
Q
= 60
A, I
SD
< 1
A,
for 3V/5V SIM Cards
SSOP16, SSOP20
LTC1755/LTC1756
850kHz, Smart Card Interface with Serial Control for 3V/5V
V
IN
: 2.7V to 7V, V
OUT
= 3V/5V, I
Q
= 60
A, I
SD
< 1
A,
Smart Card Applications
SSOP16, SSOP24
LTC1955
Dual Smart Card Interface with Serial Control for 1.8V/3V/5V
V
IN
: 3V to 5.5V, V
OUT
= 1.8V/3V/5V, I
Q
= 200
A,
Smart Card Applications
I
SD
< 1
A, QFN32
LTC1986
900kHz, SIM Power Supply for 3V/5V SIM Cards
V
IN
: 2.6V to 4.4V, V
OUT
= 3V/5V, I
Q
= 14
A, I
SD
< 1
A,
ThinSOT
LTC4555
SIM Power Supply and Level Translator
V
IN
: 3V to 6V, V
OUT
= 1.8V/3V, I
Q
= 40
A, I
SD
< 1
A,
for 1.8V/3V SIM Cards
QFN16
LTC4557
Dual SIM/Smart Card Power Supply and Level Translator
V
IN
: 2.7V to 5.5V, V
OUT
= 1.8V/3V, I
Q
= 250
A, I
SD
< 1
A,
for 1.8V/3V Cards
QFN16
ThinSOT is a trademark of Linear Technology Corporation.
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
q
FAX: (408) 434-0507
q
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
LT/TP 0604 1K PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATIO
U
SMART CARD
LTC4556EUF
1
F
D
IN
DV
CC
V
CC
UNDERV
V
BATT
ASYNC
D
OUT
SCLK
R
IN
LD
DATA
I/O
C4
C8
RST
CLK
V
CC
CPO
V
GND
C
9
11
12
C
+
FAULT
4556 TA02
6
20
1
4
10
21
22
23
24
5
3
2
42
41
43
44
24
9
1
16
17
18
15
14
13
PRES
19
C7
C4
C8
C2
C3
C1
8
1
F
28
15
0.1
F
V
+
1
5
0.1
F
1
F
0.1
F
C5
RD
TD
GND
DB9
0.1
F
1k
0.1
F
XIRQ
19
37
0.1
F
180k
Li-ION
4.7
F
262k
+
RST
2
1
36
V
CC18
4
5
V
CC3
3
V
CCA
GND
LTC1728ES5-1.8
DREN
17
RXEN
16
MOD B
21
V
DD
V
RH
45
22
26
27
18
20
XTAL
EXTAL
V
RL
V
SS
GND
MODA
47k
RST
47k
RESET
FAULT
(MOSI) PD3
38
IRQ
(2MHz) E
(MISO) PD2
25
24
40
39
DR1IN
RX1OUT
7
8
2
3
DR1OUT
RX1IN
PD1 (TXD)
PD0 (RXD)
(SCK) PD4
PB0
(SS) PD5
(IC3) PA0
28
PC0
SYNC
4
46
PA7
29
PC1
0.1
F
3
C2
2
C2
+
0.1
F
6
C1
5
C1
+
0.1
F
26
C3
27
C3
+
10M
8.000MHz
27pF
27pF
MC68L11E9PB2
LTC1348CG
Battery-Powered RS232 to Smart Card Interface
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