LTC694-3.3/LTC695-3.3

3.3V Microprocessor

Supervisory Circuits

3.3V

100

0.1

POWER

POWER TO
CMOS RAM

SYSTEM

0.1

2.4V

51k

18k

694/5-3.3 TA01

MICROPROCESSOR RESET, BATTERY BACK-UP,
RAM WRITE PROTECTION, POWER WARNING AND
WATCHDOG TIMING ARE ALL IN A SINGLE CHIP
FOR 3.3V MICROPROCESSOR SYSTEM

LTC695-3.3

BATT

PFI

OUT

GND

DECODER OUTPUT
RAM CS

P RESET

P NMI

I/O LINE

CE IN

CE OUT

RESET

PFO

WDI

0.1

100

GND

OUT

LT1129-3.3

OUT SENSE

SHDN

SUPPLY VOLTAGE (V)

RESET OUTPUT VOLTAGE (V)

694/5-3.3 TA02

RESET Output Voltage vs

Supply Voltage

UL Recognized File # E145770

Guaranteed Reset Assertion at V

= 1V

Pin Compatible with LTC694/LTC695
for 3.3V Systems

200

A Typical Supply Current

Fast (30ns Typ) On-Board Gating of
RAM Chip Enable Signals

SO-8 and S16 Packages

2.90V Precision Voltage Monitor

Power OK/Reset Time Delay: 200ms or Adjustable

Minimum External Component Count

A Maximum Standby Current

Voltage Monitor for Power-Fail or
Low-Battery Warning

Thermal Limiting

Performance Specified Over Temperature

The LTC

694-3.3/LTC695-3.3 provide complete 3.3V

power supply monitoring and battery control functions.
These include power-on reset, battery back-up, RAM write
protection, power failure warning and watchdog timing.
The devices are pin compatible upgrades of the LTC694/
LTC695 that are optimized for 3.3V systems. Operating
power consumption has been reduced to 0.6mW (typical)
and 3

W maximum in battery back-up mode. Micropro-

cessor reset and memory write protection are provided
when the supply falls below 2.9V. The RESET output is
guaranteed to remain logic low with V

as low as 1V.

The LTC694-3.3/LTC695-3.3 power the active RAMs with
a charge pumped NMOS power switch to achieve low
dropout and low supply current. When primary power is
lost, auxiliary power, connected to the battery input pin,
powers the RAMs in standby through an efficient PMOS
switch.

For an early warning of impending power failure, the
LTC694-3.3/LTC695-3.3 provide an internal comparator
with a user-defined threshold. An internal watchdog timer
is also available, which forces the reset pins to active
states when the watchdog input is not toggled prior to a
preset time-out period.

, LTC and LT are registered trademarks of Linear Technology Corporation.

3.3V Low Power Systems

Critical

P Power Monitoring

Intelligent Instruments

Battery-Powered Computers and Controllers

Automotive Systems

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

LTC694-3.3/LTC695-3.3

PRODUCT SELECTIO GUIDE

BSOLUTE

Terminal Voltage

...................................................... 0.3V to 6V

BATT

.................................................. 0.3V to 6V

All Other Inputs .................. 0.3V to (V

OUT

+ 0.3V)

Input Current

.............................................................. 100mA

BATT

............................................................ 25mA

GND .............................................................. 10mA

OUT

Output Current ................. Short-Circuit Protected

Power Dissipation ............................................. 500mW
Operating Temperature Range

LTC694C-3.3/LTC695C-3.3 .................. 0

C to 70

LTC694I-3.3/LTC695I-3.3 ............... 40

C to 85

Storage Temperature Range ................ 65

C to 150

Lead Temperature (Soldering, 10 sec) ................. 300

(Notes 1 and 2)

PACKAGE/ORDER I FOR ATIO

(Note 3)

LTC694CN8-3.3
LTC694IN8-3.3

JMAX

= 110

= 180

C/W

TOP VIEW

VBATT

OUT

PFO

PFI

GND

S8 PACKAGE

8-LEAD PLASTIC SO

WDI

RESET

LTC694CS8-3.3
LTC694IS8-3.3

6943
694I3

TOP VIEW

OUT

PFI

GND

WDI

BATT

PFO

RESET

N8 PACKAGE
8-LEAD PDIP

JMAX

= 110

= 130

C/W

S8 PART

MARKING

TOP VIEW

N PACKAGE

16-LEAD PDIP

OUT

BATT

GND

BATT ON

OSC IN

LOW LINE

OSC SEL

WDO

CE IN

RESET

CE OUT

WDI

PFI

PFO

JMAX

= 110

= 130

C/W

ORDER PART

NUMBER

LTC695CN-3.3
LTC695IN-3.3

LTC695CSW-3.3
LTC695ISW-3.3

ORDER PART

NUMBER

JMAX

= 110

= 130

C/W

TOP VIEW

SW PACKAGE

16-LEAD PLASTIC WIDE SO

BATT

OUT

GND

BATT ON

LOW LINE

OSC IN

OSC SEL

RESET

WDO

CE IN

CE OUT

WDI

PFO

PFI

Consult factory for Military grade parts.

RESET

CONDITIONAL

THRESHOLD

WATCHDOG

BATTERY

POWER-FAIL

RAM WRITE

PUSH-BUTTON

BATTERY

PINS

(V)

TIMER

BACK-UP

WARNING

PROTECT

RESET

BACK-UP

LTC694-3.3

2.90

LTC695-3.3

2.90

LTC690

4.65

LTC691

4.65

LTC694

4.65

LTC695

4.65

LTC699

4.65

LTC1232

4.37/4.62

LTC1235

4.65

LTC694-3.3/LTC695-3.3

ELECTRICAL C

HARA TERISTICS

The

denotes specifications which apply over the operating temperature

range, otherwise specifications are at T

= 25

C. V

= 3.3V, V

BATT

= 2V, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Battery Back-Up Switching

Operating Voltage Range

3.0

5.50

BATT

1.5

2.75

OUT

Output Voltage

OUT

= 1mA

0.1

0.01

0.2

0.01

OUT

= 50mA

0.8

0.4

OUT

in Battery Back-Up Mode

OUT

= 250

A, V

< V

BATT

0.1

BATT

0.02

Supply Current (Exclude I

OUT

)

OUT

50mA, V

= 3.6V

0.2

0.6

0.2

1.0

Supply Current in Battery Back-Up Mode

= 0V, V

BATT

= 2V

0.04

Battery Standby Current (+ = Discharge, = Charge)

3.6V > V

> V

BATT

+ 0.2V

0.02

0.10

Battery Switchover Threshold (V

BATT

)

Power Up

Power Down

Battery Switchover Hysteresis

BATT ON Output Voltage (Note 4)

SINK

= 800

0.3

BATT ON Output Short-Circuit Current (Note 4)

BATT ON = V

OUT

, Sink Current

BATT ON = 0V, Source Current

0.5

Reset and Watchdog Timer

Reset Voltage Threshold

2.8

2.9

3.0

Reset Threshold Hysteresis

Reset Active Time

OSC SEL HIGH, V

= 3V

160

200

240

140

200

280

Watchdog Time-Out Period, Internal Oscillator

Long Period, V

= 3V

1.2

1.6

2.0

sec

1.0

1.6

2.25

sec

Short Period, V

= 3V

100

120

100

140

Watchdog Time-Out Period, External Clock (Note 5)

Long Period, V

= 3V

4032

4097

Clock

Short Period, V

= 3V

960

1025

Cycles

Reset Active Time PSRR

ms/V

Watchdog Time-Out Period PSRR, Internal OSC

Short Period

ms/V

Long Period

ms/V

Minimum WDI Input Pulse Width

= 0.4V, V

= 3V

200

RESET Output Voltage at V

= 1V

SINK

= 10

A, V

= 1V

200

RESET and LOW LINE Output Voltage (Note 4)

SINK

= 400

A, V

= 2.8V

0.3

SOURCE

= 0.1

A, V

= 3V

2.3

RESET and WDO Output Voltage (Note 4)

SINK

= 400

A, V

= 3V

0.3

SOURCE

= 0.1

A, V

= 2.8V

2.3

RESET, RESET, WDO, LOW LINE

Output Source Current

Output Short-Circuit Current (Note 4)

Output Sink Current

LTC694-3.3/LTC695-3.3

ELECTRICAL C

HARA TERISTICS

The

denotes specifications which apply over the operating temperature

range, otherwise specifications are at T

= 25

C. V

= 3.3V, V

BATT

= 2V, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

WDI Input Threshold

Logic Low

0.4

Logic High

2.3

WDI Input Current

WDI = V

OUT

WDI = 0V

Power-Fail Detector

PFI Input Threshold

1.25

1.3

1.35

PFI Input Threshold PSRR

0.3

mV/V

PFI Input Current

0.01

PFO Output Voltage (Note 4)

SINK

= 800

0.3

SOURCE

= 0.1

2.3

PFO Short-Circuit Source Current (Note 4)

PFI = HIGH, PFO = 0V

PFI = LOW, PFO = V

OUT

PFI Comparator Response Time (Falling)

= 20mV, V

= 15mV

PFI Comparator Response Time (Rising) (Note 4)

= 20mV, V

= 15mV

with 10k

Pull-Up

Chip Enable Gating

CE IN Threshold

0.45

1.9

CE IN Pull-Up Current (Note 6)

CE OUT Output Voltage

SINK

= 800

0.3

SOURCE

= 400

OUT

0.50

SOURCE

= 1

A, V

= 0V

OUT

0.05

CE IN Propagation Delay

= 20pF

CE OUT Output Short-Circuit Current

Output Source Current

Output Sink Current

Oscillator

OSC IN Input Current (Note 6)

OSC SEL Input Pull-Up Current (Note 6)

OSC IN Frequency Range

OSC SEL = 0V

125

kHz

OSC SEL = 0V, C

OSC

= 47pF

kHz

Note 5: The external clock feeding into the circuit passes through the
oscillator before clocking the watchdog timer. Variation in the time-out
period is caused by phase errors which occur when the oscillator divides
the external clock by 64. The resulting variation in the time-out period is
64 plus one clock of jitter.

Note 6: The input pins of CE IN, OSC IN and OSC SEL have weak internal
pull-ups which pull to the supply when the input pins are floating.

Note 1: Absolute Maximum Ratings are those values beyond which the life
of device may be impaired.

Note 2: All voltage values are with respect to GND.

Note 3: For military temperature range parts, consult the factory.

Note 4: The output pins of BATT ON, LOW LINE, PFO, WDO, RESET and
RESET have weak internal pullups of typically 3

A. However, external pull-

up resistors may be used when higher speed is required.

LTC694-3.3/LTC695-3.3

Output Voltage vs Load Current

Power Failure Input Threshold
vs Temperature

Output Voltage vs Load Current

Reset Voltage Threshold vs
Temperature

Reset Active Time vs
Temperature

LOAD CURRENT (mA)

OUTPUT VOLTAGE (V)

3.30

3.25

3.20

3.15

3.10

3.05

3.00

694/5-3.3 G01

SLOPE = 4.6

= 3.3V

BATT

= 2.4V

= 25

HARA TERISTICS

TYPICAL PERFOR

LOAD CURRENT (

OUTPUT VOLTAGE (V)

400

694/5-3.3 G02

100

200

300

500

2.40

2.39

2.38

2.37

2.36

2.35

= 0V

BATT

= 2.4V

= 25

SLOPE = 90

TEMPERATURE (

PFI INPUT THRESHOLD (V)

1.310

1.308

1.306

1.304

1.302

1.300

1.298

1.296

1.294

694/5-3.3 G03

100

125

= 3.3V

TIME (

3.5

3.0

2.5

2.0

1.5

1.0

0.5

694/5-3.3 G04

1.305V

1.285V

= 3.3V

= 25

PFI

= 20mV STEP

PFO OUTPUT VOLTAGE (V)

PFI

1.3V

30pF

PFO

TIME (

3.5

3.0

2.5

2.0

1.5

1.0

0.5

694/5-3.3 G06

1.315V
1.295V

PFI

= 20mV STEP

PFO OUTPUT VOLTAGE (V)

= 3.3V

= 25

PFI

1.3V

30pF

10k

3.3V

PFO

TEMPERATURE (

RESET ACTIVE TIME (ms)

694/5-3.3 G07

100

125

220

210

200

190

180

170

160

150

= 3.3V

TEMPERATURE (

RESET VOLTAGE THRESHOLD (V)

2.90

2.89

2.88

2.87

2.86

2.85

2.84

694/5-3.3 G08

100

125

= 3.3V

SUPPLY VOLTAGE (V)

RESET OUTPUT VOLTAGE (V)

694/5-3.3 TA02

RESET Output Voltage vs
Supply Voltage

Power-Fail Comparator
Response Time

TIME (

3.5

3.0

2.5

2.0

1.5

1.0

0.5

694/5-3.3 G05

1.315V
1.295V

120

100

PFI

= 20mV STEP

180

160

140

PFO OUTPUT VOLTAGE (V)

= 3.3V

= 25

PFI

1.3V

30pF

PFO

Power-Fail Comparator
Response Time

Power-Fail Comparator
Response Time with Pull-Up
Resistor

LTC694-3.3/LTC695-3.3

PI FU CTIO S

: 3.3V Supply Input. The V

pin should be bypassed

with a 0.1

F capacitor.

OUT

: Voltage Output for Backed Up Memory. Bypass with

a capacitor of 0.1

F or greater. During normal operation,

OUT

obtains power from V

through an NMOS power

switch, M1, which can deliver up to 50mA and has a typical
on resistance of 5

. When V

is lower than V

BATT

, V

OUT

is internally switched to V

BATT

. If V

OUT

and V

BATT

are not

used, connect V

OUT

to V

BATT

: Back-Up Battery Input. When V

falls below V

BATT

auxiliary power connected to V

BATT

, is delivered to V

OUT

through PMOS switch, M2. If back-up battery or auxiliary
power is not used, V

BATT

should be connected to GND.

GND: Ground Pin.

BATT ON: Battery On Logic Output from Comparator C2.
BATT ON goes low when V

OUT

is internally connected to

. The output typically sinks 25mA and can provide base

drive for an external PNP transistor to increase the output
current above the 50mA rating of V

OUT

. BATT ON goes

high when V

OUT

is internally switched to V

BATT

PFI: Power Failure Input. PFI is the noninverting input to
the power-fail comparator, C3. The inverting input is
internally connected to a 1.3V reference. The power failure
output remains high when PFI is above 1.3V and goes low
when PFI is below 1.3V. Connect PFI to GND or V

OUT

when

C3 is not used.

PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When V

is lower than V

BATT

, C3 is shut down and

PFO is forced low.

RESET: Logic Output for

P Reset Control. Whenever V

falls below either the reset voltage threshold (2.90V,
typically) or V

BATT

, RESET goes active low. After V

returns to 3.3V, the reset pulse generator forces RESET to
remain active low for a minimum of 140ms. When the
watchdog timer is enabled but not serviced prior to a
preset time-out period, the reset pulse generator also
forces RESET to active low for a minimum of 140ms for

every preset time-out period (see Figure 11). The reset
active time is adjustable on the LTC695-3.3. An external
push-button reset can be used in connection with the
RESET output. See Push-Button Reset in Applications
Information section.

RESET: Active High Logic Ouput. It is the inverse of
RESET.

LOW LINE: Logic Output from Comparator C1. LOW LINE
indicates a low line condition at the V

input. When V

falls below the reset voltage threshold (2.90V typically),
LOW LINE goes low. As soon as V

rises above the reset

voltage threshold, LOW LINE returns high (see Figure 1).
LOW LINE goes low when V

drops below V

BATT

(see

Table 1).

WDI: Watchdog Input. WDI is a three-level input. Driving
WDI either high or low for longer than the watchdog time-
out period, forces both RESET and WDO low. Floating WDI
disables the watchdog timer. The timer resets itself with
each transition of the watchdog input (see Figure 11).

WDO: Watchdog Logic Output. When the watchdog input
remains either high or low for longer than the watchdog
time-out period, WDO goes low. WDO is set high whenever
there is a transition on the WDI pin, or LOW LINE goes low.
The watchdog timer can be disabled by floating WDI (see
Figure 11).

CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN
can be derived from microprocessor's address line and/or
decoder output. See Applications Information section and
Figure 5 for additional information.

CE OUT: Logic Output on the Chip Enable Gating Circuit.
When V

is above the reset voltage threshold, CE OUT is

a buffered replica of CE IN. When V

is below the reset

voltage threshold CE OUT is forced high (see Figure 5).

OSC SEL: Oscillator Selection Input. When OSC SEL is
high or floating, the internal oscillator sets the reset active
time and watchdog time-out period. Forcing OSC SEL low,
allows OSC IN to be driven from an external clock signal or
an external capacitor can be connected between OSC IN
and GND.

LTC694-3.3/LTC695-3.3

OSC IN: Oscillator Input. OSC IN can be driven by an
external clock signal or an external capacitor can be
connected between OSC IN and GND when OSC SEL is
forced low. In this configuration the nominal reset active
time and watchdog time-out period are determined by the
number of clocks or set by the formula (see Applications

Information section). When OSC SEL is high or floating,
the internal oscillator is enabled and the reset active time
is fixed at 200ms typical for the LTC695-3.3. OSC IN
selects between the 1.6 seconds and 100ms typical
watchdog time-out periods. In both cases, the time-out
period immediately after a reset is 1.6 seconds typical.

D AGRA

BLOCK

PI FU CTIO S

CHARGE

PUMP

VBATT

VCC

CE IN

PFI

OSC IN

OSC SEL

WDI

RESET PULSE

GENERATOR

WATCHDOG

TIMER

RESET

BATT ON

VOUT

1.3V

GND

OSC

TRANSITION

DETECTOR

WDO

RESET

PFO

LOW LINE

CE OUT

694/5-3.3 BD

LTC694-3.3/LTC695-3.3

Figure 1. Reset Active Time

= RESET ACTIVE TIME

V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS

694/5-3.3 F01

RESET

LOW LINE

PPLICATI

I FOR ATIO

Microprocessor Reset

The LTC694-3.3/LTC695-3.3 use a bandgap voltage refer-
ence and a precision voltage comparator C1 to monitor the
3.3V supply input on V

(see Block Diagram). When V

falls below the reset voltage threshold, the RESET output
is forced to active low state. The reset voltage threshold
accounts for a 10% variation on V

, so the RESET output

becomes active low when V

falls below 3.0V (2.9V

typical). On power-up, the RESET signal is held active low
for a minimum of 140ms after reset voltage threshold is
reached to allow the power supply and microprocessor to
stabilize. The reset active time is adjustable on the LTC695-
3.3. On power-down, the RESET signal remains active low
even with V

as low as 1V. This capability helps hold the

microprocessor in stable shutdown condition. Figure 1
shows the timing diagram of the RESET signal.

The precision voltage comparator, C1, typically has 40mV
of hysteresis which ensures that glitches at V

pin do not

activate the RESET output. Response time is typically
10

s. To help prevent mistriggering due to transient loads,

the V

pin should be bypassed with a 0.1

F capacitor with

the leads trimmed as short as possible.

The LTC695-3.3 has two additional outputs: RESET and
LOW LINE. RESET is an active high output and is the
inverse of RESET. LOW LINE is the output of the precision
voltage comparator C1. When V

falls below the reset

voltage threshold, LOW LINE goes low. LOW LINE returns
high as soon as V

rises above the reset voltage threshold.

Battery Switchover

The battery switchover circuit compares V

to the V

BATT

input, and connects V

OUT

to whichever is higher. When

rises to 70mV above V

BATT

, the battery switchover

comparator, C2, connects V

OUT

to V

through a charge-

pumped NMOS power switch, M1. When V

falls to

50mV above V

BATT

, C2 connects V

OUT

to V

BATT

through a

PMOS switch, M2. C2 has typically 20mV of hysteresis to
prevent spurious switching when V

remains nearly

equal to V

BATT

. The response time of C2 is approximately

During normal operation, the LTC694-3.3/LTC695-3.3
use a charge-pumped NMOS power switch to achieve low
dropout and low supply current. This power switch can
deliver up to 50mA to V

OUT

from V

and has a typical on

resistance of 5

. The V

OUT

pin should be bypassed with

a capacitor of 0.1

F or greater to ensure stability. Use of

a larger bypass capacitor is advantageous for supplying
current to heavy transient loads.

When operating currents larger than 50mA are required
from V

OUT

, or a lower dropout (V

-V

OUT

voltage differen-

tial) is desired, the LTC695-3.3 should be used. This
product provides BATT ON output to drive the base of an
external PNP transistor (Figure 2). If higher currents are
needed with the LTC694-3.3, a high current Schottky
diode can be connected from the V

pin to the V

OUT

to supply the extra current.

LTC694-3.3/LTC695-3.3

PPLICATI

I FOR ATIO

3.3V

2.4V

0.1

BATT

LTC695-3.3

OUT

GND

ANY PNP POWER TRANSISTOR

694/5-3.3 F02

BATT ON

3.3V

2.4V

0.1

BATT

LTC694-3.3
LTC695-3.3

OUT

GND

694/5-3.3 F03

OUT

BATT

I =

Figure 2. Using BATT ON to Drive External PNP Transistor

The LTC694-3.3/LTC695-3.3 are protected for safe area
operation with short-circuit limit. Output current is limited
to approximately 200mA. If the device is overloaded for a
long period of time, thermal shutdown turns the power
switch off until the device cools down. The threshhold
temperature for thermal shutdown is approximately 155

with about 10

C of hysteresis which prevents the device

from oscillating in and out of shutdown.

The PNP switch used in competitive devices was not
chosen for the internal power switch because it injects
unwanted current into the substrate. This current is col-
lected by the V

BATT

pin in competitive devices and adds to

the charging current of the battery which can damage
lithium batteries. The LTC694-3.3/LTC695-3.3 use a charge-
pumped NMOS power switch to eliminate unwanted charg-
ing current while achieving low dropout and low supply
current. Since no current goes to the substrate, the current
collected by V

BATT

pin is strictly junction leakage.

A 125

PMOS switch connects the V

BATT

input to V

OUT

battery back-up mode. The switch is designed for very low
dropout voltage (input-to-output differential). This feature
is advantageous for low current applications such as
battery back-up in CMOS RAM and other low power CMOS
circuitry. The supply current in battery back-up mode is
1

A maximum.

The operating voltage at the V

BATT

pin ranges from 1.5V to

2.75V. The charging resistor for rechargeable batteries
should be connected to V

OUT

since this eliminates the

discharge path that exists when the resistor is connected
to V

(Figure 3).

Figure 3. Charging External Battery Through V

OUT

Replacing the Back-Up Battery

When changing the back-up battery with system power
on, spurious resets can occur while the battery is removed
due to battery standby current. Although battery standby
current is only a tiny leakage current, it can still charge up
the stray capacitance on the V

BATT

pin. The oscillation

cycle is as follows: When V

BATT

reaches within 50mV of

, the LTC694-3.3/LTC695-3.3 switch to battery back-

up. V

OUT

pulls V

BATT

low and the device goes back to

normal operation. The leakage current then charges up the
V

BATT

pin again and the cycle repeats.

If spurious resets during battery replacement pose no
problems, then no action is required. Otherwise, a resistor
from V

BATT

to GND will hold the pin low while changing the

battery. For example, the battery standby current is 1

maximum over temperature so the external resistor re-
quired to hold V

BATT

below V

is:

50mV

1 A

With V

= 3V, a 2.7M resistor will work. With a 2V battery,

this resistor will draw only 0.7

A from the battery, which

is negligible in most cases.

If battery connections are made through long wires, a 10

to 100

series resistor and a 0.1

F capacitor are recom-

mended to prevent any overshoot beyond V

due to the

lead inductance (Figure 4).

LTC694-3.3/LTC695-3.3

Table 1 shows the state of each pin during battery back-up.
When the battery switchover section is not used, connect
V

BATT

to GND and V

OUT

to V

Memory Protection

The LTC695-3.3 includes memory protection circuitry
which ensures the integrity of the data in memory by
preventing write operations when V

is at invalid level.

Two additional pins, CE IN and CE OUT, control the Chip
Enable or Write inputs of CMOS RAM. When V

is 3.3V,

CE OUT follows CE IN with a typical propagation delay of
30ns. When V

falls below the reset voltage threshold or

BATT

, CE OUT is forced high, independent of CE IN. CE

OUT is an alternative signal to drive the CE, CS, or Write
input of battery backed up CMOS RAM. CE OUT can also
be used to drive the Store or Write input of an EEPROM,
EAROM or NOVRAM to achieve similar protection. Figure
5 shows the timing diagram of CE IN and CE OUT.

CE IN can be derived from the microprocessor's address
decoder output. Figure 6 shows a typical nonvolatile
CMOS RAM application.

Memory protection can also be achieved with the LTC694-
3.3 by using RESET as shown in Figure 7.

Power-Fail Warning

The LTC694-3.3/LTC695-3.3 generate a Power Failure
Output (PFO) for early warning of failure in the
microprocessor's power supply. This is accomplished by

Figure 5. Timing Diagram for CE IN and CE OUT

PPLICATI

I FOR ATIO

2.7M

0.1

BATT

LTC694-3.3
LTC695-3.3

GND

694/5-3.3 F04

Figure 4. 10

/0.1

F Combination Eliminates Inductive

Overshoot and Prevents Spurious Resets During Battery
Replacement. The 2.7M Pulls the V

BATT

Pin to Ground

While the Battery is Removed, Eliminating Spurious Resets

SIGNAL

STATUS

C2 monitors V

for active switchover

OUT

is connected to V

BATT

through an internal PMOS switch

BATT

The supply current is 1

A maximum.

BATT ON

Logic high. The open-circuit output voltage is equal to V

OUT

PFI

Power failure input is ignored

PFO

Logic low

RESET

Logic low

RESET

Logic high. The open-circuit output voltage is equal to V

OUT

LOW LINE Logic low

WDI

Watchdog input is ignored.

WDO

Logic high. The open-circuit output voltage is equal to V

OUT

CE IN

Chip Enable input is ignored.

CE OUT

Logic high. The open-circuit output voltage is equal to V

OUT

OSC IN

OSC IN is ignored

OSC SEL

OSC SEL is ignored

Table 1. Input and Output Status in Battery Back-Up Mode

CE IN

OUT

= V

BATT

CE OUT

OUT

= V

BATT

V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
RESET THRESHOLD HYSTERESIS

694/5-3.3 F05

LTC694-3.3/LTC695-3.3

PPLICATI

I FOR ATIO

3.3V

2.4V

0.1

BATT

LTC695-3.3

OUT

GND

694/5-3.3 F06

RESET

CE IN

CE OUT

RESET

0.1

FROM DECODER

30ns PROPAGATION DELAY

62512

RAM

GND

Figure 9. Monitoring

Regulated DC Supply with the

LTC694-3.3/LTC695-3.3's Power-Fail Comparator

694/5-3.3 F09

0.1

6.5V

2.7M

3.3V

R1
27k

R2
16k

R5
5k

GND

PFO
PFI

LTC694-3.3
LTC695-3.3

10k

OUT

LT1129-3.3

SHDN

OUT SENSE

ADJ

Figure 6. A Typical Nonvolatile CMOS RAM Application

Figure 7. Write Protect for RAM with LTC694-3.3

3.3V

2.4V

0.1

BATT

OUT

GND

694/5-3.3 F07

RESET

0.1

62128

RAM

CS1

CS2

GND

LTC694-3.3

100

694/5-3.3 F08

0.1

PFO

GND

R4
10k

PFI

LTC694-3.3
LTC695-3.3

R1
51k

R2
16k

200k

3.3V

OUT

LT1129-3.3

SHDN

OUT SENSE

ADJ

Figure 8. Monitoring

Unregulated DC Supply with the

LTC694-3.3/LTC695-3.3's Power-Fail Comparator

comparing the power failure input (PFI) with an internal
1.3V reference.

PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 3.3V output. The
voltage divider ratio can be chosen such that the voltage
at the PFI pin falls below 1.3V several milliseconds before
the 3.3V supply falls below the maximum reset voltage
threshold 3.0V. PFO is normally used to interrupt the
microprocessor to execute shutdown procedure between
PFO and RESET or RESET.

The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resis-
tor between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:

When PFO output is low, R3 sinks current from the
summing junction at the PFI pin.

V =1.3V 1+

When PFO output is high, the series combination of R3 and
R4 source current into the PFI summing junction.

1.3V 1

(3.3V 1.3V)R1

1.3V(R3 R4)

Assuming R4

R3,V

3 V

HYSTERESIS

Example 1: The circuit in Figure 8 demonstrates the use of
the power-fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of the
supply input V

is 100mV/ms and the total time to execute

a shutdown procedure is 8ms. Also the noise of V

200mV. With these assumptions in mind, we can reason-
ably set V

= 5V which is 1.6V greater than the sum of

maximum reset voltage threshold and the dropout voltage
of the LT1129-3.3 (3V + 0.4V) and V

HYSTERESIS

= 850mV.

LTC694-3.3/LTC695-3.3

PPLICATI

I FOR ATIO

3 V

850mV

HYSTERESIS

3.88 R1

Choose R3 = 200k and R1 = 51k. Also select R4 = 10k
which is much smaller than R3.

5V =1.3V 1+

(3.3V 1.3V)51

1 3 210

(

)

R2 = 15.8k, Choose nearest 5% resistor 16k and recalcu-
late V

1.3V 1

16k

(3.3V 1.3V)51

1.3V(210k

1.3V 1

51k

16 k

51k

2 00k

(4.96V 3.4V)

100mV/ms

15.6ms

4 96

)

HYSTERESIS

= 5.77V 4.96V = 810mV

The 15.6ms allows enough time to execute shutdown
procedure for microprocessor and 810mV of hysteresis
would prevent PFO from going low due to the noise of V

Example 2: The circuit in Figure 9 can be used to measure
the regulated 3.3V supply to provide early warning of
power failure. Because of variations in the PFI threshold,
this circuit requires adjustment to ensure the PFI com-
parator trips before the reset threshold is reached. Adjust
R5 such that the PFO output goes low when the V

supply

reaches the desired level (e.g., 3.1V).

Monitoring the Status of the Battery

C3 can also monitor the status of the memory back-up
battery (Figure 10). If desired, the CE OUT can be used to
apply a test load to the battery. Since CE OUT is forced high
in battery back-up mode, the test load will not be applied
to the battery while it is in use, even if the microprocessor
is not powered.

Watchdog Timer

The LTC694-3.3/LTC695-3.3 provide a watchdog timer
function to monitor the activity of the microprocessor. If
the microprocessor does not toggle the watchdog input
(WDI) within a seleced time-out period, RESET is forced to
active low for a minimum of 140ms. The reset active time
is adjustable on the LTC695-3.3. Since many systems can
not service the watchdog timer immediately after a reset,
the LTC695-3.3 has a longer time-out period (1.0 second
minimum) right after a reset is issued. The normal time-
out period (70ms minimum) becomes effective following
the first transition of WDI after RESET is inactive. The
watchdog time-out period is fixed at 1.0 second minimum
on the LTC694-3.3. Figure 11 shows the timing diagram of
watchdog time-out period and reset active time. The
watchdog time-out period is restarted as soon as RESET
is inactive. When either a high-to-low or low-to-high
transition occurs at the WDI pin prior to time-out, the
watchdog time is reset and begins to time out again. To
ensure the watchdog time does not time out, either a high-
to-low or low-to-high transition on the WDI pin must
occur at or less than the minimum time-out period. If the
input to the WDI pin remains either high or low, reset
pulses will be issued every 1.6 seconds typically. The
watchdog time can be deactivated by floating the WDI pin.
The timer is also disabled when V

falls below the reset

voltage threshold or V

BATT

2.4V

3.3V

694/5-3.3 F10

R1
1M

20k

R2
1.6M

OPTIONAL TEST LOAD

LOW-BATTERY SIGNAL
TO

P I/O PIN

I/O PIN

BATT

GND

PFI

LTC695-3.3

CE IN

PFO

CE OUT

Figure 10. Back-Up Battery Monitor with Optional Test Load

LTC694-3.3/LTC695-3.3

PPLICATI

I FOR ATIO

= RESET ACTIVE TIME

= NORMAL WATCHDOG TIME-OUT PERIOD

= WATCHDOG TIME-OUT PERIOD IMMEDIATELY

AFTER A RESET

= 3.3V

WDO

WDI

RESET

694/5-3.3 F11

The LTC695-3.3 provides an additional output (Watchdog
Output, WDO) which goes low if the watchdog timer is
allowed to time out and remains low until set high by the
next transition on the WDI pin. WDO is also set high when
V

falls below the reset voltage threshold or V

BATT

The LTC695-3.3 has two additonal pins, OSC SEL and OSC
IN, which allow reset active time and watchdog time-out
period to be adjusted per Table 2. Several configurations
are shown in Figure 12.

OSC IN can be driven by an external clock signal or an
external capacitor can be connected between OSC IN and
GND when OSC SEL is forced low. In these configurations,
the nominal reset active time and watchdog time-out
period are determined by the number of clocks or set by
the formula in Table 2. When OSC SEL is high or floating,
the internal oscillator is enabled and the reset active time
is fixed at 140ms minimum for the LTC695-3.3. OSC IN
selects between the 1 second and 70ms minimum normal
watchdog time-out periods. In both cases, the time-out
period immediately after a reset is at least 1 second.

Figure 12. Oscillator Configurations

Figure 11. Watchdog Time-Out Period and Reset Active Time

EXTERNAL CLOCK

INTERNAL OSCILLATOR

1.6 SECOND WATCHDOG

INTERNAL OSCILLATOR

100ms WATCHDOG

EXTERNAL OSCILLATOR

GND

OSC SEL

OSC IN

FLOATING
OR HIGH

LTC695-3.3

FLOATING
OR HIGH

LTC695-3.3

694/5-3.3 F12

3.3V

LTC694-3.3/LTC695-3.3

PPLICATI

I FOR ATIO

Table 2. LTC695-3.3 Reset Active Time and Watchdog Time-Out Selections

Push-Button Reset

The LTC694-3.3/LTC695-3.3 do not provide a logic input
for direct connection to a push-button. However, a push-
button in series with a 100

resistor connected to the

RESET output pin (Figure 13) provides an alternative for
manual reset. Connecting a 0.1

F capacitor to the RESET

pin debounces the push-button input.

The 100

resistor in series with the push-button is

required to prevent the ringing, due to the capacitance and
lead inductance, from pulling the RESET pins of the MPU
and LTC69X below ground.

Capacitor Back-Up with 74HC4016 Switch

3.3V

100

LTC694-3.3
LTC695-3.3

GND

694/5-3.3 F13

RESET

0.1

MPU

(e.g. 68HC05)

RESET

Figure 13. The External Push-Button Reset

R1
10k

R2
30k

0.1

100

3.3V

OUT

BATT

74HC4016

694/5-3.3 TA03

LOW LINE

GND

LTC695-3.3

400ms

· C

70pF

1.6 sec

· C

70pF

WATCHDOG TIME-OUT PERIOD

RESET ACTIVE TIME

IMMEDIATELY

NORMAL

AFTER RESET

OSC SEL

OSC IN

(Short Period)

(Long Period)

LTC695-3.3

Low

External Clock Input

1024 CLKs

4096 CLKs

2048 CLKs

Low

External Capacitor*

Floating or High

Low

100ms

1.6 sec

200ms

Floating or High

1.6 sec

200ms

*The nominal internal frequency is 10.24kHz. The nominal oscillator frequency with external capacitor is f

OSC

(Hz) =

800ms

· C

70pF

184,000

C(pF) · 1025

PPLICATI

TYPICAL

LTC694-3.3/LTC695-3.3

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

S16 (WIDE) 0396

NOTE 1

0.398 0.413*

(10.109 10.490)

0.394 0.419

(10.007 10.643)

0.037 0.045

(0.940 1.143)

0.004 0.012

(0.102 0.305)

0.093 0.104

(2.362 2.642)

0.050

(1.270)

TYP

0.014 0.019

(0.356 0.482)

TYP

NOTE 1

0.009 0.013

(0.229 0.330)

0.016 0.050

(0.406 1.270)

0.291 0.299**

(7.391 7.595)

0.010 0.029

(0.254 0.737)

NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

N8 Package 8-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

N8 1197

0.100

0.010

(2.540

0.254)

0.065

(1.651)

TYP

0.045 0.065

(1.143 1.651)

0.130

0.005

(3.302

0.127)

0.020

(0.508)

MIN

0.018

0.003

(0.457

0.076)

0.125

(3.175)

MIN

0.009 0.015

(0.229 0.381)

0.300 0.325

(7.620 8.255)

0.325

+0.035
0.015

+0.889
0.381

8.255

(

)

0.255

0.015*

(6.477

0.381)

0.400*

(10.160)

MAX

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

SW Package 16-Lead Plastic Small Outline (Wide 0.300)

(LTC DWG # 05-08-1620)

N16 1197

0.009 0.015

(0.229 0.381)

0.300 0.325

(7.620 8.255)

0.325

+0.035
0.015

+0.889
0.381

8.255

(

)

0.255

0.015*

(6.477

0.381)

0.770*

(19.558)

MAX

0.020

(0.508)

MIN

0.125

(3.175)

MIN

0.130

0.005

(3.302

0.127)

0.065

(1.651)

TYP

0.045 0.065

(1.143 1.651)

0.018

0.003

(0.457

0.076)

0.100

0.010

(2.540

0.254)

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

N Package 16-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

0.150 0.157**

(3.810 3.988)

0.189 0.197*

(4.801 5.004)

0.228 0.244

(5.791 6.197)

0.016 0.050
0.406 1.270

0.010 0.020

(0.254 0.508)

TYP

0.008 0.010

(0.203 0.254)

SO8 0996

0.053 0.069

(1.346 1.752)

0.014 0.019

(0.355 0.483)

0.004 0.010

(0.101 0.254)

0.050

(1.270)

TYP

DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC694-3.3/LTC695-3.3

LINEAR TECHNOLOGY CORPORATION 1993

69453fa LT/TP 0399 2K REV A · PRINTED IN USA

Write Protect for Additional RAMs

PPLICATI

TYPICAL

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

FAX: (408) 434-0507

www.linear-tech.com

PART NUMBER

DESCRIPTION

COMMENTS

LTC1326

Micropower Precision Triple Supply Monitor

4.725V, 3.118V, 1V Thresholds (

0.75%)

LTC1536

Micropower Triple Supply Monitor for PCI Applications

Meets PCI t

FAIL

Timing Specifications

RELATED PARTS

BATT

LTC695-3.3

OUT

GND

694/5-3.3 TA04

LOW LINE

CE IN

CE OUT

0.1

30ns PROPAGATION
DELAY

LH5168SH

RAM A

3.3V

2.4V

0.1

LH5116S

RAM C

CS2

LH5116S

RAM B

CS A

CS B

CS C

CS1

OPTIONAL CONNECTION FOR
ADDITIONAL RAMs

CS2

0.1

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC694CN8-3.3

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LTC694CN8-3.3