DEVICES INCORPORATED

L29C520/521

4 x 8-bit Multilevel Pipeline Register

Pipeline Registers

08/02/2000LDS.520/1-P

u Four 8-bit Registers
u

u Implements Double 2-Stage Pipeline

or Single 4-Stage Pipeline Register

u Hold, Shift, and Load Instructions
u

u Separate Data In and Data Out Pins
u

u High-Speed, Low Power CMOS

Technology

u Three-State Outputs
u

u Replaces IDT29FCT520/IDT29FCT521

and AMD Am29520/Am29521

u Package Styles Available:

· 24-pin PDIP
· 28-pin PLCC, J-Lead

FEATURES

DESCRIPTION

L29C520/521

4 x 8-bit Multilevel Pipeline Register

DEVICES INCORPORATED

The L29C520 and L29C521 are pin-
for-pin compatible with the
IDT29FCT520/IDT29FCT521 and
AMD Am29520/Am29521, imple-
mented in low power CMOS.

The L29C520 and L29C521 contain
four registers which can be configured
as two independent, 2-level pipelines
or as one 4-level pipeline.

The Instruction pins, I

1-0

, control the

loading of the registers. For either
device, the registers may be config-
ured as a four-stage delay line, with
data loaded into R1 and shifted
sequentially through R2, R3, and R4.
Also, for the L29C520, data may be
loaded from the inputs into either R1
or R3 with only R2 or R4 shifting. The
L29C521 differs from the L29C520 in
that R2 and R4 remain unchanged
during this type of data load, as
shown in Tables 1 and 2. Finally, I

1-0

may be set to prevent any register
from changing.

The S

1-0

select lines control a 4-to-1

multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allows simultaneous write
and read operations on different
registers.

Register Selected

ABLE

UTPUT

ELECT

Description

HOLD

ALL REGISTERS ON HOLD

ABLE

L29C521 I

NSTRUCTION

ABLE

Description

HOLD

ALL REGISTERS ON HOLD

ABLE

L29C520 I

NSTRUCTION

ABLE

L29C520/521 B

LOCK

IAGRAM

MUX

REG 1

REG 2

REG 3

REG 4

MUX

8-0

7-0

1-0

CLK

DEVICES INCORPORATED

L29C520/521

4 x 8-bit Multilevel Pipeline Register

Pipeline Registers

08/02/2000LDS.520/1-P

Storage temperature ........................................................................................................... 65°C to +150°C

Operating ambient temperature ........................................................................................... 55°C to +125°C

supply voltage with respect to ground ............................................................................ 0.5 V to +7.0 V

Input signal with respect to ground ........................................................................................ 3.0 V to +7.0 V

Signal applied to high impedance output ............................................................................... 3.0 V to +7.0 V

Output current into low outputs ............................................................................................................. 25 mA

Latchup current ............................................................................................................................... > 400 mA

AXIMUM

ATINGS

Above which useful life may be impaired (Notes 1, 2, 3, 8)

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Output High Voltage

= Min., I

= 15.0 mA

2.4

Output Low Voltage

= Min., I

= 24.0 mA

0.5

Input High Voltage

2.0

Input Low Voltage

(Note 3)

0.0

0.8

Input Current

Ground

(Note 12)

µA

Output Leakage Current

Ground

OUT

(Note 12)

µA

CC1

Current, Dynamic

(Notes 5, 6)

CC2

Current, Quiescent

(Note 7)

1.5

LECTRICAL

HARACTERISTICS

Over Operating Conditions (Note 4)

PERATING

ONDITIONS

To meet specified electrical and switching characteristics

Mode

Temperature Range (Ambient)

Supply

Voltage

Active Operation, Commercial

0°C to +70°C

4.75 V

5.25 V

Active Operation, Military

55°C to +125°C

4.50 V

5.50 V

DEVICES INCORPORATED

L29C520/521

4 x 8-bit Multilevel Pipeline Register

Pipeline Registers

08/02/2000LDS.520/1-P

1234567890123456

1234567890123456789012345678901212345678901234

L29C520/521

14*

Symbol

Parameter

Min

Max

Min

Max

Clock to Output Delay

SEL

Select to Output Delay

Clock Pulse Width

Instruction Setup Time

Instruction Hold Time

Data Setup Time

Data Hold Time

ENA

Three-State Output Enable Delay

(Note 11)

DIS

Three-State Output Disable Delay

(Note 11)

OMMERCIAL

PERATING

ANGE

(0°C to +70°C)

Notes 9, 10 (ns)

SWITCHING CHARACTERISTICS

L29C520/521

30*

24*

16*

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Clock to Output Delay

SEL

Select to Output Delay

Clock Pulse Width

Instruction Setup Time

Instruction Hold Time

Data Setup Time

Data Hold Time

ENA

Three-State Output Enable Delay

(Note 11)

DIS

Three-State Output Disable Delay

(Note 11)

ILITARY

PERATING

ANGE

(55°C to +125°C)

Notes 9, 10 (ns)

WITCHING

AVEFORMS

HIGH IMPEDANCE

ENA

DIS

7-0

CLK

SEL

1-0

7-0

1234567890123456789

ISCONTINUED

PEED

RADE

DEVICES INCORPORATED

L29C520/521

4 x 8-bit Multilevel Pipeline Register

Pipeline Registers

08/02/2000LDS.520/1-P

1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.

2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.

3. This device provides hard clamping of
transient undershoot and overshoot. In-
put levels below ground or above V

will be clamped beginning at 0.6 V and
V

+ 0.6 V. The device can withstand

indefinite operation with inputs in the
range of 0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.

4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.

5. Supply current for a given applica-
tion can be accurately approximated by:

where

N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.

7. Tested with all inputs within 0.1 V of
V

or Ground, no load.

8. These parameters are guaranteed
but not 100% tested.

NCV F

NOTES

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t

DIS

test), and input levels of nominally

0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified I

and I

at an output

voltage of V

min and V

max

respectively. Alternatively, a diode
bridge with upper and lower current
sources of I

and I

respectively,

and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.

This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

a. A 0.1 µF ceramic capacitor should be
installed between V

and Ground

leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device V

and the tester common, and device
ground and tester common.

b. Ground and V

supply planes

must be brought directly to the DUT
socket or contactor fingers.

c. Input voltages should be adjusted to
compensate for inductive ground and V

noise to maintain required DUT input
levels relative to the DUT ground pin.

10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.

11. For the t

ENA

test, the transition is

measured to the 1.5 V crossing point
with datasheet loads. For the t

DIS

test,

the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, V

, is set at 3.5 V for Z-to-0

and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.

12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

DUT

0.2 V

DIS

ENA

0.2 V

1.5 V

3.5V Vth

1.5 V

0V Vth

Measured V

with I

= 10mA and I

= 10mA

Measured V

with I

= 10mA and I

= 10mA

IGURE

B. T

HRESHOLD

EVELS

IGURE

A. O

UTPUT

OADING

IRCUIT

DEVICES INCORPORATED

L29C520/521

4 x 8-bit Multilevel Pipeline Register

Pipeline Registers

08/02/2000LDS.520/1-P

0°C to +70°C -- C

OMMERCIAL

CREENING

55°C to +125°C -- MIL-STD-883 C

OMPLIANT

55°C to +125°C -- C

OMMERCIAL

CREENING

24-pin -- 0.3" wide

28-pin

CLK

GND

Top

View

17 18

13 14 15 16

CLK

GND

L29C520 -- ORDERING INFORMATION

Plastic DIP

(P2)

L29C520PC22

Plastic J-Lead Chip Carrier

(J4)

L29C520JC22

Speed

22 ns

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: L29C521PC22

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: L29C521PC22