DEVICES INCORPORATED
LF3312
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
LOGIC Devices Incorporated
1
September 14, 2005 LDS.3312 N
Video Imaging Product
Near-Full/Empty Flags With Programmable
Thresholds
Flexible Pointer Manipulation
Write and Read Pointers may be indepen-
dently jumped to arbitrary address locations
Write or Read Pointers can be manipulated
in real-time based on external 24bit address
LF3312s may be Cascaded for depth and
width, supporting HDTV, Multiframe SDTV,
and other high resolution formats
Seamless address space is maintained
with up to 16 cascaded devices
Built-in ITU-R BT.656 TRS detection and
Synchronization
Set & Clear Read/Write Pointer Control Pins
Choice of Control Interfaces:
Two-wire Serial Microprocessor Interface
Parallel Microprocessor Interface
Input Enable Control (Write Mask) for freeze-
frame applications
Output Enable Control (Data Skipping)
JTAG Boundary Scan - IEEE 1149.1
172 ball LBGA package
1.8V Internal Core Power Supply
3.3V I/O Supply
DTV/HDTV Video Stream Buffer
Frame Synchronization
CCTV Security Camera Systems
Time Base Correction (TBC)
Freeze-Frame Buffer
Regional Read/Write for Picture-in-Picture (PIP)
Field-Based or Frame-Based Comb Filtering
Video Capture & Editing Systems
Deep Data Buffering
Video Special Effects (Rotation, Zoom)
Test Pattern Generation
Motion Detection or Frame-to-Frame Correlation
12,441,600-bit Frame Memory
74.25MHz Max Data Rate
May be Organized Into the Following
Configurations:
1,555,200 x 8-bit (single channel)
1,244,160 x 10-bit (single channel)
1,036,800 x 12-bit (single channel)
777,600 x 16-bit (width expansion - dual channel)
622,080 x 20-bit (width expansion - dual channel)
518,400 x 24-bit (width expansion - dual channel)
777,600 x 8-bit (each of two parallel channels)
622,080 x 10-bit (each of two parallel channels)
518,400 x 12-bit (each of two parallel channels)
Operating Modes:
Random Access with External Address Port
(Single-channel)
FIFO With Asynchronous I/O (Single-channel)
FIFO With Asynchronous I/O (Dual-channel)
Synchronous Shift Register (Single-channel)
Synchronous Shift Register (Dual-channel)
FIFO + shift register; Channel B Synchronized to
Channel A
Shift register + FIFO; One channel Synchronized
to the other
Features
Applications
NOTE: This Preliminary Datasheet references LF3312BGC Engineering Samples
with an ES marking under the part designation.
MEMORY
12Mbit
JTAG
PARALLEL
INTERFACE
WRITE
POINTER
READ
POINTER
RANDOM ACCESS
ADDRESSING
FLAGS
INPUT
DATA
PORTS
OUTPUT
DATA
PORTS
A/B WEN
A/B REN
A/B SET
RSET
A/B IEN
A/B MARK
TDI
TDO
TRST
TMS
TCLK
(x8,x10, x12)
TWO-WIRE SERIAL
INTERFACE
INPUT
CONTROL
OUTPUT
CONTROL
A/B WCLK
A/B CLR
RCLK
RCLR
A/B PE
A/B PF
A/B COLLIDE
SDA SCL
(x8,x10, x12)
CE
WE
RE
ADDR
DATA
AIN
BIN
AOUT
BOUT
8
6
LOAD
PROGRAM
.
.
.
.
DEVICES INCORPORATED
LF3312
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
LOGIC Devices Incorporated
September 14, 2005 LDS.3312 N
Video Imaging Product
2
The LF3312 is a 12,441,600-bit memory device which can be configured by the user into either a two-
data-port single-channel or a four-data-port dual-channel architecture. The input data ports may be clocked
simultaneously or asynchronously with one another and with the output ports. Using the four 12-bit data
ports provided, the user can operate the chip as one or two 8, 10, or 12-bit channels or as a single 16, 20, or
24-bit channel, without wasting any memory resources. Since reads are non-destructive, a given data value,
once written into the memory core, may be read as many times as desired. A user requiring more storage
can cascade up to sixteen LF3312s into a larger array.
A great deal of memory addressing flexibility is offered with the LF3312. In addition to simple clearing of the
Write and Read pointers, either pointer may be set/jumped to any location within the entire address space.
Real-time random-access Writing or Reading is also supported through an external address port.
The device is controlled by sixteen instruction words of eight bits each, which may be programmed or
verified via a standard I
2
C 2-wire serial or parallel microprocessor interface.
The 3-bit OPMODE control selects one of the chip's operating modes, each of which has versatile submode
options:
- One-Channel FIFO With Asynchronous I/O
- Two-Channel FIFO; Both Channels Sychronized to External Signals
- One-Channel Synchronous Shift Register (Single Clock; User-set Latency)
- Two-Channel Synchronous Shift Register (Single Clock; User-set Latencies)
- One-Channel Framestore With Random Access
- Two-Channel FIFO; Channel A Synchronized to Channel B
- Two-Channel FIFO; Channel B Synchronized to Channel A
LF3312 Overview
LF3312 Functional Block Diagram
MEMORY CELL ARRAY A
AIN
11-0
12
BIN
11-0
12
AOUT
11-0
12
BOUT
11-0
*
12
BOE
AOE
518,400 x 12-bit
622,080 x 10-bit
777,600 x 8-bit
MEMORY CELL ARRAY B
518,400 x 12-bit
622,080 x 10-bit
777,600 x 8-bit
APE
APF
FLAG
GENERATOR A
WRITE
CONTROL A
ASET
ACLR
AWEN
AWCLK
READ
CONTROL A
RSET
RCLR
RCLK
AREN
BPE
BPF
FLAG
GENERATOR B
READ
CONTROL B
RCLK
AMARK
ACOLLIDE, BCOLLIDE
RSET
RCLR
AWCLK
AMARK
BWCLK
BMARK
BREN
AIEN
WRITE
CONTROL B
BSET
BCLR
BWEN
BWCLK
BMARK
BIEN
MASTER
CONTROL
I C
2
SCL
SDA
PROGRAM
CHIP_ADDR
6-0
7
PDATA
8
PADDR
6
CSB
REB
WEB
DEVICES INCORPORATED
LF3312
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
LOGIC Devices Incorporated
September 14, 2005 LDS.3312 N
Video Imaging Product
3
Figure 1. Dual Channel FIFO Mode Functional Block Diagram
MEMORY CELL ARRAY
AIN
11-0
12
AOUT
11-0
12
APE
APF
FLAG
GENERATOR
AOE
1,036,800 x 12-bit
1,244,160 x 10-bit
1,555,200 x 8-bit
READ
CONTROL
READ
CONTROL A
RCLK
AREN
RSET
RCLR
ACOLLIDE
AMARK
WRITE
CONTROL A
ASET
ACLR
AWEN
AWCLK
AMARK
AIEN
MASTER
CONTROL
I C
2
SCL
SDA
PROGRAM
CHIP_ADDR
6-0
7
PDATA
8
PADDR
6
CSB
REB
WEB
MEMORY CELL ARRAY
AIN
11-0
12
ADDR
11-0 =
BIN
11-0
12
AOUT
11-0
ADDR
23-12 =
BOUT
11:0
12
AOE
1,036,800 x 12-bit
1,244,160 x 10-bit
1,555,200 x 8-bit
12
ADDRESS
CONTROL
READ
CONTROL
RCLK
AREN
RSET
RCLR
24
WRITE
CONTROL A
ASET
ACLR
AWEN
AWCLK
AMARK
AIEN
MASTER
CONTROL
I C
2
SCL
SDA
PROGRAM
CHIP_ADDR
6-0
7
PDATA
8
PADDR
6
CSB
REB
WEB
DEVICES INCORPORATED
LF3312
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
LOGIC Devices Incorporated
4
September 14, 2005 LDS.3312 N
Video Imaging Product
Figure 2. Single Channel FIFO Mode Functional Block Diagram
Figure 3. Random Access Mode Functional Block Diagram
DEVICES INCORPORATED
LF3312
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
LOGIC Devices Incorporated
September 14, 2005 LDS.3312 N
Video Imaging Product
5
Operating Modes
Asynchronous single-channel FIFO mode (OPMODE = 3)
In OPMODE 3, the LF3312 is configured as a single channel First-In-First-Out 12Mbit memory, with
independent read and write clocks to allow for asynchronous operation. This mode is ideal for buffering or
burst data applications. Arbitrary write/read pointer jumping is supported in all FIFO modes. In this mode
the device can re-time a data stream according to a read sync signal (RSET or RCLR) and either ITU-R656
Timing Reference Signals (TRS) embedded within the incoming (video) data or the falling edge of a write
sync signal applied to ACLR, ASET, or AMARK.
As a single channel FIFO, the LF3312 must have AWCLK and BWCLK tied together as must be AWEN
with BWEN, and AIEN with BIEN. The input (write) and output (read) clocks need not be synchronous with
one another, although the memory core will eventually fill or empty if they differ in average frequency. After
it "fills," the LF3312 continues writing and the oldest data gets written over. If the memory core "empties"
(and neither the read nor write pointer have been set or cleared during run-time) the read pointer stops
incrementing, and the device re-reads the last written sample until more data is written. In either case,
when the read and write addresses reach equality, the ACOLLIDE flag will go high, to alert the host. The
almost-full and almost-empty flags provide advance warning of these conditions whenever user-selected
"fullness" or "emptiness" thresholds, expressed in approximate eightieths of the memory core size, are
exceeded. For example, if the 1/80 and 79/80 thresholds are enabled, flag APE will go HIGH whenever the
read pointer lags behind the write pointer by less than 1/80 of the memory space, and flag APF will go HIGH
whenever the read pointer leads the write pointer by this amount. (Calculations are performed modulo the
total address space.) The data input and output are sequential and the timing between write and read sync
signals dynamically determines the effective delay (depth) of the FIFO.
The `stop reading when empty' FIFO-mode behavior can be avoided by making sure LOAD is HIGH and
issuing any write or read pointer SET or CLR command at any time. This effectively gets the device out
of this `read-pointer-halting' mode from that point onwards, but invalidates the flags. Random Access Mode
allows free manipulation of the r/w pointers, and never halts the read pointer without being commanded
to do so using AREN or BREN. Since Random Access mode naturally increments the r/w pointers
sequentially, like in FIFO mode, it may be a better mode to use if pointer manipulation of a single-channel
of memory is desired.
Dual-channel asynchronous FIFO mode (OPMODE = 7; power-on default)
OPMODE 7 operates identically to the single channel FIFO (OPMODE 3), with two independent chanels.
In dual-channel asynchronous FIFO mode, the device can accept two asynchronous data streams and
automatically adjust the latency of each to bring it into alignment with an output sync signal applied to RSET
or RCLR. Again, the user may reference input synchronization either to ACLR, ASET, BCLR, and BSET,
to AMARK and BMARK, or to embedded TRS. The data read/output clock need not be synchronous with
either of the two input clocks, which likewise need not be synchronous with one another. If memory core
A or B "empties" or "fills" completely, ACOLLIDE and/or BCOLLIDE respectively, will be set accordingly if
the write and read pointers collide.
The data Word that BMARK `marks' (by going LOW during that xWCLK cycle) in the input data stream
will be the first synchronized AOUT/BOUT data word. If N full frames of Channel A data have been
loaded into AIN before the first Channel B data frame is loaded into BIN, the second frame of B channel
data will be synchronized to the (N+1)th Channel A frame. (there will be N frames difference between
Channel A and B).
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