DEVICES INCORPORATED

LMA1010/2010

16 x 16-bit Multiplier-Accumulator

Multiplier-Accumulators

08/16/2000LDS.10/2010-P

u 20 ns Multiply-Accumulate Time
u

u Replaces Fairchild TMC2210,

Cypress CY7C510, IDT 7210L,
and AMD Am29510

u Two's Complement or Unsigned

Operands

u Accumulator Performs Preload,

Accumulate, and Subtract

u Three-State Outputs
u

u 68-pin PLCC, J-Lead

FEATURES

DESCRIPTION

LMA1010/2010

16 x 16-bit Multiplier-Accumulator

DEVICES INCORPORATED

The LMA1010 and LMA2010 are
high-speed, low power 16-bit
multiplier-accumulators. The LMA1010
and LMA2010 are functionally identical;
they differ only in packaging. Full mili-
tary ambient temperature range opera-
tion is achieved with advanced CMOS
technology.

The LMA1010 and LMA2010 produce
the 32-bit product of two 16-bit numbers.
The results of a series of multiplications
may be accumulated to form the sum of
products. Accumulation is performed to
35-bit precision with the multiplier prod-
uct sign extended as appropriate.

Data present at the A and B input regis-
ters is latched on the rising edges of
CLK A and CLK B respectively. RND,

TC, ACC, and SUB controls are latched
on the rising edge of the logical OR of
CLK A and CLK B. TC specifies the
input as two's complement
(TC HIGH) or unsigned magnitude
(TC LOW). RND, when HIGH, adds `1'
to the most significant bit position of
the least significant half of the product.
Subsequent truncation of the 16 least
significant bits produces a result
correctly rounded to 16-bit preci-
sion.

ACC and SUB control accumulator
operation. ACC HIGH results in
addition of the multiplier product and
the accumulator contents, with the result
stored in the accumulator register on the
rising edge of CLK R. ACC and SUB
HIGH results in subtraction of the
accumulator contents from the
multiplier product, with the result stored
in the accumulator register. With ACC
LOW and SUB LOW, no accumulation
occurs and the next product is loaded
directly into the accumulator register.
ACC LOW and SUB HIGH is undefined.

The LMA1010/2010 output register
(accumulator register) is divided into
three independently controlled sec-
tions. The least significant result
(LSR) and most significant result
(MSR) registers are 16 bits in length.
The extended result register (XTR) is
3 bits long. The output signals R

15-0

and input signals B

15-0

share the same

bidirectional pins.

Each output register has an indepen-
dent output enable control. In addition
to providing three-state control of the
output buffers, when OEX, OEM, or OEL
are HIGH and PREL is HIGH, data can be
preloaded via the bidirectional output
pins into the respective output registers.
Data present on the output pins is
latched on the rising edge of CLK R. The
interrelation of PREL and the enable
controls is summarized in Table 1.

LMA1010/2010 B

LOCK

IAGRAM

A REGISTER

B REGISTER

15-0

ACC

CLK A

CLK B

RND

31-16

R + A

R A

PASS R

LEM

LEL

LEX

34-32

PRELOAD

CONTROL

LOGIC

CLK R

ACCUMULATOR

SUB

OEL

OEX
OEM

PREL

LEL

LEX
LEM

OEL

OEX

OEM

OEX

OEM

OEL

DEVICES INCORPORATED

LMA1010/2010

16 x 16-bit Multiplier-Accumulator

Multiplier-Accumulators

08/16/2000LDS.10/2010-P

ABLE

1. P

RELOAD

RUTH

ABLE

PREL = Preload data to appropriate register
OUT = Register available on output pins
Z

= High impedance state

PREL OEX

OEM

OEL

XTR

MSR LSR

OUT

PREL

PREL PREL

PREL

PREL PREL

PREL PREL PREL

IGURE

NPUT

ORMATS

15 14 13

(Sign)

15 14 13

(Sign)

Fractional Two's Complement (TC = 1)

15 14 13

(Sign)

15 14 13

(Sign)

Integer Two's Complement (TC = 1)

15 14 13

Unsigned Fractional (TC = 0)

15 14 13

Unsigned Integer (TC = 0)

IGURE

UTPUT

ORMATS

31 30 29

18 17 16

34 33 32

(Sign)

Fractional Two's Complement

Integer Two's Complement

Unsigned Fractional

Unsigned Integer

MSR

LSR

31 30 29

18 17 16

31 30 29

18 17 16

31 30 29

18 17 16

15 14 13

XTR

34 33 32

(Sign)

15 14 13

34 33 32

15 14 13

34 33 32

15 14 13

DEVICES INCORPORATED

LMA1010/2010

16 x 16-bit Multiplier-Accumulator

Multiplier-Accumulators

08/16/2000LDS.10/2010-P

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Output High Voltage

= Min., I

= 2.0 mA

2.4

Output Low Voltage

= Min., I

= 8.0 mA

0.5

Input High Voltage

2.0

Input Low Voltage

(Note 3)

0.0

0.8

Input Current

Ground

(Note 12)

µA

Output Leakage Current

Ground

OUT

(Note 12)

µA

CC1

Current, Dynamic

(Notes 5, 6)

CC2

Current, Quiescent

(Note 7)

1.0

Storage temperature ........................................................................................................... 65°C to +150°C

Operating ambient temperature ........................................................................................... 55°C to +125°C

supply voltage with respect to ground ............................................................................ 0.5 V to +7.0 V

Input signal with respect to ground ........................................................................................ 3.0 V to +7.0 V

Signal applied to high impedance output ............................................................................... 3.0 V to +7.0 V

Output current into low outputs ............................................................................................................. 25 mA

Latchup current ............................................................................................................................... > 400 mA

AXIMUM

ATINGS

Above which useful life may be impaired (Notes 1, 2, 3, 8)

PERATING

ONDITIONS

To meet specified electrical and switching characteristics

LECTRICAL

HARACTERISTICS

Over Operating Conditions (Note 4)

Mode

Temperature Range (Ambient)

Supply

Voltage

Active Operation, Commercial

0°C to +70°C

4.75 V

5.25 V

Active Operation, Military

55°C to +125°C

4.50 V

5.50 V

DEVICES INCORPORATED

LMA1010/2010

16 x 16-bit Multiplier-Accumulator

Multiplier-Accumulators

08/16/2000LDS.10/2010-P

1234567890

123456789012345678901234567890121234567890123456789012345

12345678901234567890123456789

12345678901

OMMERCIAL

PERATING

ANGE

(0°C to +70°C)

Notes 9, 10 (ns)

SWITCHING CHARACTERISTICS

ILITARY

PERATING

ANGE

(55°C to +125°C)

Notes 9, 10 (ns)

123456789012345678901234

ISCONTINUED

PEED

RADE

WITCHING

AVEFORMS

HIGH IMPEDANCE

15-0

ENA

DIS

CLK A
CLK B

CLK R

OE*

OUTPUT

PRELOAD

34-0

PREL

*includes OEX, OEM, OEL

LMA1010/2010

65*

55*

45*

35*

20*

Symbol

Parameter

Min Max Min Max Min Max Min Max Min Max Min Max

Clocked Multiply Time

Clock Pulse Width

Input Register Setup Time

Input Register Hold Time

Preload Setup Time

Preload Hold Time

Output Delay

ENA

Three-State Output Enable Delay

(Note 11)

DIS

Three-State Output Disable Delay

(Note 11)

LMA1010/2010

75*

65*

55*

40*

30*

25*

Symbol

Parameter

Min Max Min Max Min Max Min Max Min Max Min Max

Clocked Multiply Time

Clock Pulse Width

Input Register Setup Time

Input Register Hold Time

Preload Setup Time

Preload Hold Time

Output Delay

ENA

Three-State Output Enable Delay

(Note 11)

DIS

Three-State Output Disable Delay

(Note 11)

DEVICES INCORPORATED

LMA1010/2010

16 x 16-bit Multiplier-Accumulator

Multiplier-Accumulators

08/16/2000LDS.10/2010-P

1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.

2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.

3. This device provides hard clamping of
transient undershoot and overshoot. In-
put levels below ground or above V

will be clamped beginning at 0.6 V and
V

+ 0.6 V. The device can withstand

indefinite operation with inputs in the
range of 0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.

4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.

5. Supply current for a given applica-
tion can be accurately approximated by:

where

N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.

7. Tested with all inputs within 0.1 V of
V

or Ground, no load.

8. These parameters are guaranteed
but not 100% tested.

NCV F

NOTES

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t

DIS

test), and input levels of nominally

0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified I

and I

at an output

voltage of V

min and V

max

respectively. Alternatively, a diode
bridge with upper and lower current
sources of I

and I

respectively,

and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.

This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

a. A 0.1 µF ceramic capacitor should be
installed between V

and Ground

leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device V

and the tester common, and device
ground and tester common.

b. Ground and V

supply planes

must be brought directly to the DUT
socket or contactor fingers.

c. Input voltages should be adjusted to
compensate for inductive ground and V

noise to maintain required DUT input
levels relative to the DUT ground pin.

10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.

11. For the t

ENA

test, the transition is

measured to the 1.5 V crossing point
with datasheet loads. For the t

DIS

test,

the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, V

, is set at 3.5 V for Z-to-0

and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.

12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

DUT

0.2 V

DIS

ENA

0.2 V

1.5 V

3.5V Vth

1.5 V

0V Vth

Measured V

with I

= 10mA and I

= 10mA

Measured V

with I

= 10mA and I

= 10mA

IGURE

B. T

HRESHOLD

EVELS

IGURE

A. O

UTPUT

OADING

IRCUIT

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