DEVICES INCORPORATED

LMU16/216

16 x 16-bit Parallel Multiplier

Multipliers

08/16/2000璍DS.16/216-N

20 ns Worst-Case Multiply Time

u Low Power CMOS Technology
u

u Replaces Fairchild MPY016/TMC216,

Cypress CY7C516, IDT 7216L, and
AMD Am29516

u Two's Complement, Unsigned, or

Mixed Operands

u Three-State Outputs
u

u 68-pin PLCC, J-Lead

FEATURES

DESCRIPTION

LMU16/216

16 x 16-bit Parallel Multiplier

DEVICES INCORPORATED

The LMU16 and LMU216 are high-
speed, low power 16-bit parallel
multipliers. The LMU16 and
LMU216 are functionally identical;
they differ only in packaging.

The LMU16 and LMU216 produce
the 32-bit product of two 16-bit
numbers. Data present at the A
inputs, along with the TCA control
bit, is loaded into the A register on
the rising edge of CLK A. B data
and the TCB control bit are
similarly loaded by CLK B. The
TCA and TCB controls specify the
A and B operands as two's
complement when HIGH, or
unsigned magnitude when LOW.

RND is loaded on the rising edge of
the logical OR of CLK A and CLK B.
RND, when HIGH, adds `1' to the
most significant bit position of the
least significant half of the product.
Subsequent truncation of the 16 least
significant bits produces a result
correctly rounded to 16-bit precision.

At the output, the Right Shift control
(RS) selects either of two output
formats. RS LOW produces a 31-bit
product with a copy of the sign bit
inserted in the MSB postion of the
least significant half. RS HIGH gives a
full 32-bit product. Two 16-bit output
registers are provided to hold the
most and least significant halves of the
result (MSP and LSP) as defined by
RS. These registers are loaded on the
rising edge of CLK M and CLK L
respectively. For asynchronous
output, these registers may be made
transparent by setting the feed
through control (FT) HIGH.

The two halves of the product may be
routed to a single 16-bit three-state
output port (MSP) via a multiplexer.
MSPSEL LOW causes the MSP
outputs to be driven by the most
significant half of the result. MSPSEL
HIGH routes the least significant half
of the result to the MSP outputs. In
addition, the LSP is available via the B
port through a separate three-state
buffer.

The output multiplexer control
MSPSEL uses a pin which is a supply
ground in the Fairchild MPY016H/
TMC216H. When this control is LOW
(GND), the function is that of the
MPY016H/TMC216H, thus allowing
full compatibility.

LMU16/216 B

LOCK

IAGRAM

A REGISTER

B REGISTER

RESULT

CLK A

CLK B

RND

OEM

OEL

15-0

31-16

TCA

TCB

CLK M

FORMAT ADJUST

15-0

MSPSEL

CLK L

DEVICES INCORPORATED

LMU16/216

16 x 16-bit Parallel Multiplier

Multipliers

08/16/2000璍DS.16/216-N

IGURE

NPUT

ORMATS

IGURE

UTPUT

ORMATS

15 14 13

�2

(Sign)

�1

�2

�13

�14

�15

15 14 13

�2

(Sign)

�1

�2

�13

�14

�15

Fractional Two's Complement (TCA, TCB = 1)

15 14 13

�2

(Sign)

15 14 13

�2

(Sign)

Integer Two's Complement (TCA, TCB = 1)

15 14 13

�1

�2

�3

�14

�15

�16

15 14 13

�1

�2

�3

�14

�15

�16

Unsigned Fractional (TCA, TCB = 0)

15 14 13

Unsigned Integer (TCA, TCB = 0)

MSP

LSP

31 30 29

18 17 16

�2

(Sign)

�1

�2

�13

�14

�15

15 14 13

�2

(Sign)

�16

�17

�28

�29

�30

Fractional Two's Complement (RS = 0)

31 30 29

18 17 16

�2

(Sign)

15 14 13

Integer Two's Complement (RS = 1)

31 30 29

18 17 16

�1

�2

�3

�14

�15

�16

15 14 13

�17

�18

�19

�30

�31

�32

Unsigned Fractional (RS = 1)

31 30 29

18 17 16

15 14 13

Unsigned Integer (RS = 1)

31 30 29

18 17 16

�2

(Sign)

�1

�12

�13

�14

15 14 13

�15

�16

�17

�28

�29

�30

Fractional Two's Complement (RS = 1)

DEVICES INCORPORATED

LMU16/216

16 x 16-bit Parallel Multiplier

Multipliers

08/16/2000璍DS.16/216-N

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Output High Voltage

= Min., I

= �2.0 mA

2.4

Output Low Voltage

= Min., I

= 8.0 mA

0.5

Input High Voltage

2.0

Input Low Voltage

(Note 3)

0.0

0.8

Input Current

Ground

(Note 12)

�

礎

Output Leakage Current

Ground

OUT

(Note 12)

�

礎

CC1

Current, Dynamic

(Notes 5, 6)

CC2

Current, Quiescent

(Note 7)

1.0

Storage temperature ........................................................................................................... �65癈 to +150癈

Operating ambient temperature ........................................................................................... �55癈 to +125癈

supply voltage with respect to ground ............................................................................ �0.5 V to +7.0 V

Input signal with respect to ground ........................................................................................ �3.0 V to +7.0 V

Signal applied to high impedance output ............................................................................... �3.0 V to +7.0 V

Output current into low outputs ............................................................................................................. 25 mA

Latchup current ............................................................................................................................... > 400 mA

AXIMUM

ATINGS

Above which useful life may be impaired (Notes 1, 2, 3, 8)

PERATING

ONDITIONS

To meet specified electrical and switching characteristics

LECTRICAL

HARACTERISTICS

Over Operating Conditions (Note 4)

Mode

Temperature Range (Ambient)

Supply

Voltage

Active Operation, Commercial

0癈 to +70癈

4.75 V

5.25 V

Active Operation, Military

�55癈 to +125癈

4.50 V

5.50 V

DEVICES INCORPORATED

LMU16/216

16 x 16-bit Parallel Multiplier

Multipliers

08/16/2000璍DS.16/216-N

12345678901234567890123456789012123456

123456789012345678901234567890121234567890123456789012345

SWITCHING CHARACTERISTICS

WITCHING

AVEFORMS

HIGH IMPEDANCE

INPUT

ENA

DIS

CLK L

CLK M

OEL

OEM

31-0

MUC

SEL

MSPSEL

CLK A
CLK B

LMU16/216�

75*

65*

55*

40*

30*

25*

Symbol

Parameter

Min Max Min Max Min Max Min Max Min Max Min Max

Clocked Multiply Time

MUC

Unclocked Multiply Time

Clock Pulse Width

Input Setup Time

Input Hold Time

Output Delay

SEL

Output Select Delay

ENA

Three-State Output Enable Delay

(Note 11)

DIS

Three-State Output Disable Delay

(Note 11)

LMU16/216�

65*

55*

45*

35*

Symbol

Parameter

Min Max Min Max Min Max Min Max Min Max Min Max

Clocked Multiply Time

MUC

Unclocked Multiply Time

Clock Pulse Width

Input Setup Time

Input Hold Time

Output Delay

SEL

Output Select Delay

ENA

Three-State Output Enable Delay

(Note 11)

DIS

Three-State Output Disable Delay

(Note 11)

OMMERCIAL

PERATING

ANGE

(0癈 to +70癈)

Notes 9, 10 (ns)

ILITARY

PERATING

ANGE

(�55癈 to +125癈)

Notes 9, 10 (ns)

123456789012345678901234

ISCONTINUED

PEED

RADE

DEVICES INCORPORATED

LMU16/216

16 x 16-bit Parallel Multiplier

Multipliers

08/16/2000璍DS.16/216-N

1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.

2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.

3. This device provides hard clamping of
transient undershoot and overshoot. In-
put levels below ground or above V

will be clamped beginning at �0.6 V and
V

+ 0.6 V. The device can withstand

indefinite operation with inputs in the
range of �0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.

4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.

5. Supply current for a given applica-
tion can be accurately approximated by:

where

N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency

6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.

7. Tested with all inputs within 0.1 V of
V

or Ground, no load.

8. These parameters are guaranteed
but not 100% tested.

NCV F

NOTES

9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t

DIS

test), and input levels of nominally

0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified I

and I

at an output

voltage of V

min and V

max

respectively. Alternatively, a diode
bridge with upper and lower current
sources of I

and I

respectively,

and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.

This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:

a. A 0.1 礔 ceramic capacitor should be
installed between V

and Ground

leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device V

and the tester common, and device
ground and tester common.

b. Ground and V

supply planes

must be brought directly to the DUT
socket or contactor fingers.

c. Input voltages should be adjusted to
compensate for inductive ground and V

noise to maintain required DUT input
levels relative to the DUT ground pin.

10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.

11. For the t

ENA

test, the transition is

measured to the 1.5 V crossing point
with datasheet loads. For the t

DIS

test,

the transition is measured to the
�200mV level from the measured
steady-state output voltage with
�10mA loads. The balancing volt-
age, V

, is set at 3.5 V for Z-to-0

and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.

12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.

DUT

0.2 V

DIS

ENA

0.2 V

1.5 V

3.5V Vth

1.5 V

0V Vth

Measured V

with I

= �10mA and I

= 10mA

Measured V

with I

= �10mA and I

= 10mA

IGURE

B. T

HRESHOLD

EVELS

IGURE

A. O

UTPUT

OADING

IRCUIT

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: LMU216C-35

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: LMU216C-35