24-BIT QUADRATURE COUNTER

FEATURES:

· Programmable modes are: Up/Down,
Binary, BCD, 24 Hour Clock, Divide-by-N,
x1 or x2 or x4 Quadrature and Single-Cycle.
· DC to 20MHz Count Frequency.
· 8-Bit I/O Bus for Microprocessor
Communication and Control.
· 24-Bit comparator for pre-set count
comparison.
· Readable status register.
· Input/Output TTL and CMOS compatible.
· 5V operation (Vdd - Vss).
· LS7166 (DIP); LS7166-S (SOIC);
LS7166-TS24 (24-Pin TSSOP)

- See Fig. 1

GENERAL DESCRIPTION:

The LS7166 is a CMOS, 24-bit counter that
can be programmed to operate in several dif-
ferent modes. The operating mode is set up
by writing control words into internal control
registers (see Figure 8). There are three 6-bit
and one 2-bit control registers for setting up
the circuit functional characteristics. In addi-
tion to the control registers, there is a 5-bit out-
put status register (OSR) that indicates the cur-
rent counter status. The IC communicates with
external circuits through an 8-bit three state I/O
bus. Control and data words are written into
the LS7166 through the bus. In addition to the
I/O bus, there are a number of discrete inputs
and outputs to facilitate instantaneous hard-
ware

based

control

functions

and

in-

stantaneous status indication.

REGISTER DESCRIPTION:

Internal hardware registers are accessible
through the I/O bus (D0 - D7) for READ or
WRITE when CS = 0. The C/D input selects
between the control registers (C/D = 1) and the
data registers (C/D = 0) during a READ or
WRITE operation. (See Table 1)

The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.

(Write Input) WR

(Chip Select Input) CS

(Load Counter/Load Latch) LCTR/LLTC

(A, B Gate/Reset Counter)ABGT/RCTR

(+5V)

(Count Input) A

(Count Input) B

(GND)

RD (Read Input)

C/D (Control/ Data Input)

BW (Borrow Output)

CY (Carry Output)

LSI

LS7166

January 2003

FIGURE 1

7166-012703-1

LSI/CSI

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405

LS7166

A3800

20-Pin Package PIN ASSIGNMENT - Top View

(Contact factory for 24-Pin TSSOP Package Pinout)

PR (Preset register). The PR is the input port for the CNTR. The CNTR is loaded with a 24 bit data via the PR. The
data is first written into the PR in 3 WRITE cycle sequence of Byte 0 (PR0), Byte 1 (PR1) and Byte 2 (PR2).
The address pointer for PR0/PR1/PR2 is automatically incremented with each write cycle.
Accessed by

: WRITE when C/D = 0, CS = 0.

Bit # 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0

PR2 PR1 PR0
(BYTE 2) (BYTE 1) (BYTE 0)

Standard Sequence for Loading PR and Reading CNTR

1 MCR

; Reset PR address pointer

WRITE PR

; Load Byte 0 and into PR0 increment address

WRITE PR

; Load Byte 1 and into PR1 increment address

WRITE PR

; Load Byte 2 and into PR3 increment address

8 MCR

; Transfer PR to CNTR

MCR (Master Control Register). Performs register reset and load operations. Writing a "non-zero" word to MCR does
not require a follow-up write of an "all-zero" word to terminate a designated operation.
Accessed by

: WRITE when C/D = 1, CS = 0.

Bit # 7 6 5 4 3 2 1 0

0 0

1: Reset PR/OL address pointer
1: Transfer CNTR to OL (24 bits)
1: Reset CNTR, BWT and CYT. Set SIGN bit.
(CNTR = 0, BWT = 0, CYT = 0, SIGN = 1)
1: Transfer PR to CNTR (24 bits)
1: Reset COMPT (COMPT = 0)
1: Master reset. Reset CNTR, ICR, OCCR, QR, BWT, CYT, OL
COMPT, and PR/OL address pointer. Set PR (PR = FFFFFF) and SIGN.
0: Select MCR
0:

NOTE: Control functions may be combined.

ICR (Input Control Register). Initializes counter input operating modes.
Accessed by

: WRITE when C/D = 1, CS = 0.

Bit # 7 6 5 4 3 2 1 0

0 1
0: Input A = Up count input, Input B = Down count input
1: Input A = Count input, Input B = Count direction input (overridden in
quadrature mode) where B = 0 selects up count mode and B = 1
selects Down count mode.
(

NOTE: During counting operation B may switch only when A = 1.)

0: NOP
1: Increment CNTR once (A/B = 1, if enabled)
0: NOP
1: Decrement CNTR once (A/B = 1, if enabled)
0: Disable inputs A/B
1: Enable inputs A/B
0: Initialize Pin 4 as CNTR Reset input (Pin 4 = RCTR)
1: Initialize Pin 4 as Enable/Disable gate for A/B inputs (Pin 4 = ABGT)
0: Initialize Pin 3 as CNTR load input (Pin 3 = LCTR)
1: Initialize Pin 3 as OL load input (Pin 3 = LLTC)
1: Select ICR
0:

NOTE: Control functions may be combined.

7166-012703-2

OSR (Output Status Register).

Indicates CNTR status: Accessed by

: READ when C/D = 1, CS = 0.

Bit # 7 6 5 4 3 2 1 0

U U U 0/1 0/1 0/1 0/1 0/1

BWT. Borrow Toggle Flip-Flop. Toggles everytime CNTR underflows

generating a borrow.
CYT. Carry Toggle Flip-Flop. Toggles everytime CNTR overflows
generating a carry.
COMPT. Compare Toggle Flip-Flop. Toggles everytime CNTR equals PR
SIGN. Sign bit. Reset ( = 0) when CNTR underflows
Set ( = 1) when CNTR overflows
UP/DOWN. Count direction indicatior in quadrature mode.
Reset ( = 0) when counting down
Set ( = 1) when counting up
(Forced to 1 in non-quadrature mode)

OL(Output latch).

The OL is the output port for the CNTR. The 24 bit CNTR Value at any instant can be accessed

by performing a CNTR to OL transfer and then reading the OL in 3 READ cycle sequence of Byte 0 (OL0), Byte 1 (OL1)
and Byte 2 (OL2). The address pointer for OL0/OL1/OL2 is automatically incremented with each READ cycle.
Accessed by

: READ when C/D = 0, CS = 0.

Bit #

7 0 7 0 7 0

OL2 OL1 OL0

(BYTE 2) (BYTE 1) (BYTE 0)

Standard Sequence for Loading and Reading OL

3 MCR

; Reset OL address pointer and Transfer CNTR to OL

READ OL

; Read Byte 0 and increment address

READ OL

; Read Byte 1 and increment address

READ OL

; Read Byte 2 and increment address

TABLE 1 - Register Addressing Modes

D7 D6 C/D RD WR CS COMMENT

X X X X X 1 Disable Chip for READ/WRITE
0 0 1 1 0 Write to Master Control Register (MCR)

0 1 1 1 0 Write to input control register (ICR)

1 0 1 1 0 Write to output/counter control register (OCCR)

1 1 1 1 0 Write to quadrature register (QR)
X X 0 1 0 Write to preset register (PR) and increment register
address counter.

X X 0 1 0 Read output latch (OL) and increment register
address counter

X X 1 1 0 Read output status register (OSR).

X =

Don't Care

U = Undefined

7166-012703-3

OCCR (Output Control Register) Initializes CNTR and output operating modes.

Accessed by

: WRITE when C/D = 1, CS = 0.

Bit # 7 6 5 4 3 2 1 0
1 0
0

: Binary count mode (Overridden by D3 = 1).

: BCD count mode (Overridden by D3 = 1)

: Normal count mode

: Non-Recycle count mode. (CNTR enabled with a Load or Reset

CNTR and disabled with generation of Carry or Borrow.
In this mode no external CY or BW is generated. Instead
CYT or BWT should be used as cycle completion indicator.)
0

: Normal count mode

: Divide by N count mode (CNTR is reloaded with PR data upon

Carry or Borrow).
0

: Binary or BCD count mode (see D0)

: 24 Hour Clock mode with Byte 0 = Sec, Byte 1 = Min and Byte 2 = Hr.

(Overrides BCD/Binary Modes)

Pin 16 = CY, Pin 17 = BW. (Active Low)

Pin 16 = CYT, Pin 17 = BWT

Pin 16 = CY, Pin 17 = BW. (Active high)

Pin 16 = COMP, Pin 17 = COMPT

Select OCCR

QR (Quadrature Register). Selects quadrature count mode (See Fig. 7)
Accessed by

: WRITE when C/D = 1, CS = 0.

Bit # 7 6 5 4 3 2 1 0
1 1 X X X X
0

Disable quadrature mode

Enable x1 quadrature mode

Enable x2 quadrature mode

1

1

Enable x4 quadrature mode

Select QR

7166-012703-4

X = Don't Care

I/O DESCRIPTION:

(See REGISTER DESCRIPTION for I/O Prgramming.)

Data-Bus (D0 - D7) (Pin 8 - Pin 15). The 8-line data bus is a
three-state I/O bus for interfacing with the system bus.

CS (Chip Select Input) (Pin 2). A logical "0" at this input en-
ables the chip for Read and Write.

RD (Read Input) (Pin 19). A logical "0" at this input enables the
OSR and the OL to be read on the data bus.

WR (Write Input) (Pin 1). A logical "0" at this input enables the
data bus to be written into the control and data registers.

C/D (Control/Data Input) (Pin 18). A logical "1" at this input en-
ables a control word to be written into one of the four control
registers or the OSR to be read on the I/O bus. A logical "0" en-
ables a data word to be written into the PR, or the OL to be read
on the I/O bus.

A (Pin 6). Input A is a programmable count input capable of
functioning in three different modes, such as up count input,
down count input and quadrature input.

B (Pin 7). Input B is also a programmable count input that can
be programmed to function either as down count input, or count
direction control gate for input A, or quadrature input. When B is
programmed as count direction control gate, B = 0 enables A as
the Up Count input and B = 1 enables A as the Down Count in-
put. When programmed as the direction input, B can switch
state only when A is high.

ABGT/RCTR (PIN 4). This input can be programmed to func-
tion as either inputs A and B enable gate or as external counter
reset input. A logical "0" is the active level on this input.

DC Electrical Characteristics. (All voltages referenced to V

TA = 0° to 70°C, V

= 4.5V to 5.5V, fc = 0, unless otherwise specified)

Parameter Symbol Min. Value Max.Value Unit Remarks

Supply Voltage V

4.5

5.5

Supply Current

350

µA

Outputs open

Input Low Voltage

0.8

Input High Voltage

2.0

Output Low Voltage

0.4

4mA Sink

Output High Voltage

2.5

200µA Source

Input Current

Leakage
Current

Output Source Current

SRC

200

µA

= 2.5V

Output Sink Current

SINK

= 0.4V

Data Bus Off-State
Leakage Current

Absolute Maximum Ratings:

Parameter Symbol Values Unit

Voltage at any input

- 0.3 to V

+ 0.3

Operating Temperature

0 to +70 oC

Storage Temperature

STG

-65 to +150 oC

Supply Voltage V

DD -

+7.0 V

In non-quadrature mode, if Pin 4 is programmed as A and B en-
able gate input, it may switch state only when A is high (if A is
clock and B is direction) or when both A and B are high (if A
and B are clocks. In quadrature mode, if Pin 4 is programmed
as A and B enable gate, it may switch state only when either A
or B switches.

LCTR/LLTC (PIN 3). This input can be programmed to func-
tion as the external load command input for either the CNTR or
the OL. When programmed as counter load input, the counter
is loaded with the data contained in the PR. When pro-
grammed as the OL load input, the OL is loaded with data con-
tained in the CNTR. A logical "0" is the active level on this in-
put.

CY (Pin 16). This output can be programmed to serve as one
of the following:

A. CY. Complemented Carry out (active "0").
B. CY. True Carry out (active "1").
C. CYT. Carry Toggle flip-flop out.
D. COMP. Comparator out (active "0")

BW (Pin 17). This output can be programmed to serve as one
of the following:

A. BW. Complemented Borrow out (active "0").
B. BW. True Borrow out (active "1").
C. BWT. Borrow Toggle flip-flop out.
D. COMPT. Comparator Toggle output.

(Pin 5). Supply voltage positive terminal.

(Pin 20). Supply voltage negative terminal.

7166-012703-5

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