8020

MD400023/D

8020

MCC

Manchester

Code Converter

89305

Features

Compatible with IEEE 802.3 /Ethernet (10BASE5),
IEEE802.3/Cheapernet (10BASE2) and Ethernet

Rev. 1 Specifications

Compatible with 8003 ELDC

, 8005 Advanced

EDLC

Manchester Data Encoding/Decoding and
Receiver Clock Recovery with Phase Locked

Loop (PLL)

Receiver and Collision Squelch Circuit and Noise

Rejection Filter

Differential TRANSMIT Cable Driver

Loopback Capability for Diagnostics and

Isolation

Fail-Safe Watchdog Timer Circuit to Prevent

Continuous Transmission

20 MHz Crystal Oscillator

Transceiver Interface High Voltage (16 V)

Short Circuit Protection

MCC is a trademark of SEEQ Technology Inc.
EDLC is a registered trademark of SEEQ Technology Inc.

Low Power CMOS Technology with Single 5V

Supply

20 pin DIP & PLCC Packages

Description

The SEEQ 8020 Manchester Code Converter chip pro-
vides the Manchester data encoding and decoding func-
tions of the Ethernet Local Area Network physical layer. It
interfaces to the SEEQ 8003 and 8005 Controllers and any
standard Ethernet transceiver as defined by IEEE 802.3
and Ethernet Revision 1.

Pin Configuration

PLASTIC LEADED CHIP CARRIER

TOP VIEW

Figure 1. 8020 MCC Manchester Code Converter

Block Diagram.

Functional Block Diagram

RxD

GND

COLL

COLL+

GND

MODE 1

Tx+

TxD

TxEN

Rx+

CSN

COLL

RxC

LPBK/WDTD

TxC

8020

V CC

Tx+

MODE 1

GND

Rx+

CSN

COLL

RxC

RxD

VSS

TxD

TxEN

COLL+

COLL

LPBK/WDTD

TxC

TxEN

CSN

RxC

RxD

COLL

TRANSMIT

Tx+

RECEIVE

Rx+

COLL+

COLL

COLLISION

TxC

TxD

LPBK/
WDTD

WATCHDOG

TIMER

ENCODER

CARRIER

SENSE

DECODER

10MHz

DETECTOR

XTAL

CLOCK

MUX

VCC
VSS

MODE 1

DUAL-IN LINE

TOP VIEW

Note: Check for latest Data Sheet revision
before starting any designs.

SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.

This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.

8020

MD400023/D

The SEEQ 8020 MCC is a functionally complete Encoder/
Decoder including ECL level balanced driver and receiv-
ers, on board oscillator, analog phase locked loop for clock
recovery and collision detection circuitry. In addition, the
8020 includes a watchdog timer, a 4.5 microsecond win-
dow generator, and a loopback mode for diagnostic opera-
tion.

Together with the 8003 or 8005 and a transceiver, the 8020
Manchester Code Converter provides a high performance
minimum cost interface for any system to Ethernet.

Functional Description

The 8020 Manchester Code Converter chip has two por-
tions, transmitter and receiver. The transmitter uses
Manchester encoding to combine the clock and data into
a serial stream. It also differentially drives up to 50 meters
of twisted pair transmission line. The receiver detects the
presence of data and collisions. The 8020 MCC recovers
the Manchester encoded data stream and decodes it into
clock and data outputs. Manchester Encoding is the
process of combining the clock and data stream so that
they may be transmitted on a single twisted pair of wires,
and the clock and data may be recovered accurately upon
reception. Manchester encoding has the unique property
of a transition at the center of each bit cell, a positive going
transition for a "1", and a negative going transition for a "0"
(See Figure 2). The encoding is accomplished by exclu-
sive-ORing the clock and data prior to transmission, and
the decoding by deriving the clock from the data with a
phase locked loop.

Clock Generator
The internal oscillator is controlled by a 20 MHz parallel
resonant crystal or by an external clock on X1. The 20 MHz
clock is then divided by 2 to generate a 10 MHz

0.01%

transmitter clock. Both 10 MHz and 20 MHz clocks are
used in Manchester data encoding.

Figure 3. Differential Input Terminator

Figure 2. Manchester Coding

Manchester Encoder and Differential Output Driver
The encoder combines clock and data information for the
transceiver. In Manchester encoding, the first half of the bit
cell contains the complement of the data and the second
half contains the true data. Thus a transition is always
guaranteed in the middle of a bit cell.

Data encoding and transmission begin with TxEN going
active; the first transition is always positive for Tx(-) and
negative for Tx(+). In IEEE mode, at the termination of a
transmission, TxEN goes inactive and transmit pair ap-
proach to zero differential. In Ethernet mode, at the end of
the transmission, TxEN goes inactive and the transmit pair
stay differentially high. The transmit termination can occur
at bit cell center if the last bit is a one or at a bit boundary
if the last bit is a zero. To eliminate DC current in the
transformer during idle, Tx

is brought to 100 mV differen-

tial in 600 ns after the last transition (IEEE mode). The
back swing voltage is guaranteed to be less than .1 V.

Watchdog Timer
A watchdog timer is built on chip. It can be enabled or
disabled by the LPBK/WDTD signal. The timer starts
counting at the beginning of the transmission. If TxEN
goes inactive before the timer expires, the timer is reset
and ready for the next transmission. If the timer expires
before the transmission ends, transmission is aborted by
disabling the differential transmitter. This is done by idling
the differential output drivers (differential output voltage
becomes zero) and deasserting CSN.

Differential Input Circuit (Rx+ and Rx, COLL+ and
COLL).
As shown in Figure 3, the differential input for Rx+ and Rx-
and COLL+ and COLL- are externally terminated by a pair
of 39.2

1% resistors in series for proper impedance

matching.

SERIAL
DATA

TRANSMITTED
DATA
(MANCHESTER
ENCODED)

COLLISION OR
RECEIVE
INPUT

0.01 µF

39.2 ± 1%

TRANSCEIVER
CABLE

39.2

± 1%

8020

MD400023/D

The center tap has a 0.01

F capacitor, tied to ground, to

provide the AC common mode impedance termination for
the transceiver cable.

Both collision and receiver input circuits provide a static
noise margin of -140 mV to -300mV (peak value). Noise
rejection filters are provided at both input pairs to prevent
spurious signals. For the receiver pair, the range is 15 ns
to 30 ns. For the collision pair, the range is 10 ns to 18 ns.
The D.C. threshold and noise rejection filter assure that
differential receiver data signals less than -140 mV in
amplitude or narrower than 15 ns (10 ns for collision pair)
are always rejected, signals greater than -300 mV and
wider than 30 ns (18 ns for collision pair) are always
accepted.

Manchester Decoder and Clock Recovery Circuit
The filtered data is processed by the data and clock
recovery circuit using a phase-locked loop technique. The
PLL is designed to lock onto the preamble of the incoming
signal with a transition width asymmetry not greater than
+8.25 ns to -8.25 ns within 12 bit cell times worst case and
can sample the incoming data with a transition width
asymmetry of up to +8.25 ns to -8.25 ns. The RxC high or
low time will always be greater than 40 ns. RxC follows
TxC for the first 1.2

s and then switches to the recovered

clock. In addition, the Encoder/Decoder asserts the CSN
signal while it is receiving data from the cable to indicate
the receiver data and clock are valid and available. At the
end of the frame, after the node has finished receiving,
CSN is deasserted and will not be asserted again for a
period of 4.5

s regardless of the state of the state of the

receiver pair or collision pair. This is called inhibit period.
There is no inhibit period after packet reception. During
clock switching, RxC may stay high for 200ns maximum.

Collision Circuit
A collision on the Ethernet cable is sensed by the trans-
ceiver. It generates a 10 MHz

15% differential square

wave to indicate the presence of the collision. During the
collision period, CSN is asserted asynchronously with
RxC. However, if a collision arrives during inhibit period
4.5

s from the time CSN was deasserted, CSN will not be

reasserted.

Loopback
In loopback mode, encoded data is switched to the PLL
instead of Tx+/Tx- signals. The recovered data and clock
are returned to the Ethernet Controller. All the transmit and
receive circuits, including noise rejection filter, are tested
except the differential output driver and the differential

input receiver circuits which are disabled during loopback.
At the end of frame transmission, the 8020 also generates
a 650 ns long COLL signal 550 ns after CSN was deas-
serted to simulate the IEEE 802.3 SQE test. The watchdog
timer remains enabled in this mode.

Pin Description

The MCC chip signals are grouped into four categories:

· Power Supply and Clock
· Controller Interface
· Transceiver Interface
· Miscellaneous

Power Supply

..........................................................................+5V

.....................................................................Ground

X1 and X2 clock (Inputs): Clock Crystal: 20 MHz crystal
oscillator input. Alternately, pin X1 may be used at a TTL
level input for external timing by floating pint X2,

Controller Interface

RxC Receive Clock (Output): This signal is the recov-
ered clock from the phase decoder circuit. It is switched to
TxC when no incoming data is present from which a true
receive clock is derived. 10 MHz nominal and TTL compat-
ible.

RxD Receive Data (Output): The RxD signal is the
recovered data from the phase decoder. During idle
periods, the RxD pin is LOW under normal conditions. TTL
and MOS level compatible. Active HIGH.

CSN Carrier Sense (Output): The Carrier Sense Signal
indicates to the controller that there is activity on the
coaxial cable. It is asserted when receive data is present
or when a collision signal is present. It is deasserted at the
end of frame or at the end of collision, whichever occurs
later. It is asserted or deasserted synchronously with RxC.
TTL compatible.

TxC Transmit Clock (Output): A 10 MHz signal derived
from the internal oscillator. This clock is always active.
TTL and MOS level compatible.

TxD Transmit Data (Input): TxD is the NRZ serial input
data to be transmitted. The data is clocked into the MCC
by TxC. Active HIGH, TTL compatible.

8020

MD400023/D

Figure 4. 8020 Interface

TxEN Transmit Enable (Input): Transmit Enable, when
asserted, enables data to be sent to the cable. It is
asserted synchronously with TxC. TxEN goes active with
the first bit of transmission. TTL compatible.

COLL Collision (Output): When asserted, indicates to
the controller the simultaneous transmission of two or
more stations on network cable. TTL Compatible.

Transceiver Interface

Rx+ and Rx Differential Receiver Input Pair (Input):
Differential receiver input pair which brings the encoded
receive data to the 8020. The last transition is always
positive-going to indicate the end of the frame.

COLL+ and COLL Differential Collision Input Pair
(Input): This is a 10 MHz

15% differential signal from the

transceiver indicating collision. The duty cycle should not
be worse than 60%/40% -- 40%/60%. The last transition
is positive-going. This signal will respond to signals in the
range of 5 MHz to 11.5 MHz. Collision signal may be
asserted if `MAU not available' signal is present.

Tx+ and Tx- Differential Transmit Output Pair (Output):
Differential transmit pair which sends the encoded data to
the transceiver. The cable driver buffers are source
follower and require external 243

resistors to ground as

loading. These resistors must be rated at 1 watt to
withstand the fault conditions specified by IEEE 802.3. If
MODE 1=1, after 200 ns following the last transition, the
differential voltage is slowly reduced to zero volts in 8

to limit the back swing of the coupling transformer to less
than 0.1 V.

Miscellaneous

MODE 1 (Input): This pin is used to select between AC or
DC coupling. When it is tied high or left floating, the output
drivers provide differential zero signal during idle (IEEE
802.3 specification). When pin 1 is tied low, then the
output is differentially high when idle (Ethernet Rev.1
specification).

20 MHz

XTAL

20 pF

8003

8005

MODE 1

RxC

RxD

CSN

COLL

TxD

TxEN

Rx+

Tx+

COLL+

COLL

0.01 µF

39.2

±1%

243

±1%

0.01 µF

39.2

±1%

39.2

±1%

243

±1%

DI-A

DI-B

DO-A

DO-B

CI-A

CI-B

LPBK/WDTD

20 pF

LPBK/
WDTD

TxC

SEEQ

8020

39.2

±1%

AUI
CABLE

8020

MD400023/D

LPBK/WDTD Loopback /Wat

chdog Timer

Disable (Input):

Normal Operation: For normal operation this pin should
be HIGH or tied to V

. In normal operation the watchdog

timer is enabled.

Loopback: When this pin is brought low, the Manchester
encoded transmit data from TxD and TxC is routed through
the receiver circuit and sent back onto the RxD and RxC
Pins. During loopback, Collision and Receive data inputs
are ignored. The transmit pair is idled. At the end of
transmission, the signal quality error test (SQET) will be
simulated by asserting collision during the inhibit window.
During loopback, the watchdog timer is enabled.

Watchdog Timer Disable: When this pin is between 10 V
(Min.) and 16 V (Max.), the on chip 25 ms Watchdog Timer
will be disabled. The watchdog timer is used to monitor the
transmit enable pin. If TxEN is asserted for too long, then
the watchdog timer (if enabled) will automatically deassert
CSN and inhibit any further transmissions on the Tx+ and
Tx- lines. The watchdog timer is automatically reset each
time TxEN is deasserted.

Interconnection to a Data Link
Controller

Figure 5 shows the interconnections between the 8020
MCC and SEEQ's 8003 or 8005. There are three connec-
tions for each of the two transmission channels, transmit
and receive, plus the Collision Signal line (COLL).

Transmitter connections are:

Transmit Data, TxD
Transmit Clock, TxC
Transmit Enable, TxEN
Collision, COLL

Receiver connections are:

Receive Data, RxD
Receive Clock, RxC
Carrier Sense, CSN

D.C. and A.C. Characteristics and
Timing

Crystal Specification

Resonant Frequency (C

= 20 pF) ..................... 20 MHz

0.005% 0-70

and

0.003% at 25

Type ................................................. Fundamental Mode
Circuit .............................................. Parallel Resonance
Load Capacitance (C

) ........................................... 20pF

Shunt Capacitance (C

) ................................... 7pF Max.

Equivalent Series Resistance (R1) ................. 25

Max.

Motional Capacitance (C1) ........................ 0.02 pF Max.
Drive Level ............................................................. 2mW

TxD

TxEN

COLL

RxD

RxC

CSN

LOOPBACK

[1]

TxD

TxEN

LOOPBACK

COLL

RxD

RxC

CSN

8003

8005

8020
MCC

TxC

Figure 5. Interconnection of 8020 and 8003/8005

NOTE
1. Loopback output on 8005 only.

EQUIVALENT CIRCUIT OF CRYSTAL

Figure 6.

8020

MD400023/D

*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.

Absolute Maximum Rating*

Storage Temperature .......................... 65

C to +150

All Input or Output Voltage .................. 0.3 to V

+0.3

.... .............................................................. 0.3 to 7V

(Rx

, Tx

, COLL

) High Voltage

Short Circuit Immunity .............................. 0.3 to 16V

Symbol

Parameter

Min.

Max.

Unit

Conditions

Input Leakage Current (except

MODE 1, Receive and Collision Pairs)

MODE 1 Input Leakage Current

200

Receive and Collision Pairs (Rx

= 0

COLL

) Input Leakage Current

Current

All Inputs, Outputs Open

TTL Input Low Voltage

0.3

0.8

TTL Input High Voltage (except X1)

2.0

+ 0.3

X1 Input High Voltage

3.5

+ 0.3

TTL Output Low Voltage except TxC

0.4

= 2.1 mA

TxC Output Low Voltage

0.4

= 4.2 mA

TTL Output

High Voltage (except

RxC, TxC, RxD)

2.4

= 400

RxC, TxC, RxD Output High Voltage

3.9

= 400

ODF

Differential Output Swing

0.55

1.2

Termination Resistor and

243

Load Resistors

OCM

Common Mode Output Voltage

2.5

Termination Resistor and

243

Load Resistors

BKSV

Backswing Voltage During Idle

0.1

Shunt Inductive Load

IDF

Input Differential Voltage

0.3

1.2

(measured differentially)

ICM

Input Common Mode Voltage

[1]

Input Capacitance

OUT

[1]

Output Capacitance

NOTE:

1. Characterized. Not tested

DC Characteristics

= 0

C to 70

C; V

= 5 V

8020

MD400023/D

Figure 12. 20 MHz TTL Clock Timing

20 MHz TTL Clock Input Timing

= 0

C to 70

C; V

= 5 V

Symbol

Parameter

Min.

Max.

Unit

X1 Cycle Time

49.995

50.005

X1 High Time

X1 Low Time

X1 Rise Time

X1 Fall Time

X1 to TxC Delay Time

A.C. Test Conditions

Output Loading TTL Output:

Differential Output:

Differential Signal Delay Time Reference Level:

Differential Output Rise and Fall Time:

RxC, TxC, X1 High and Low Time:

RxD, RxC, TxC, X1 Rise and Fall Time:

TTL Input Voltage (except X1):

X1 Input Voltage:

Differential Input Voltage:

1 TTL gate and 20 pF capacitor.

243

resistor and 10 pF capacitor from each pin to V

and

a termination 78

resistor load resistor in parallel with a

H inductor between the two differential output pins

50% point of swing

20% to 80% points

High time measured at 3.0V
Low time measured at 0.6V

Measured between 0.6V and 3.0 V points

0.8V to 2.0V with 10 ns rise and fall time

0.8V to 3.5V with 5 ns rise and fall time

At least

300 mV with rise and fall time of 10 ns measured

between 0.2V and +0.2V

TxC

t 5A

t 3

t 1

t 5

t 4

t 2

8020

MD400023/D

Transmit Timing

= 0

C to 70

C; V

= 5 V

Symbol

Parameter

Min.

Max.

Unit

[1]

TxC

Cycle Time

99.99

100.01

TxC High Time

TxC Low Time

[1]

TxC Rise Time

[1]

TxC Fall Time

TxEN Setup Time

TxD Setup Time

[1]

Bit Center to Bit Center Time

99.5

100.5

[1]

Bit Center to Bit Boundary Time

49.5

50.5

[1]

Tx+ and Tx Rise Time

[1]

Tx+ and Tx Fall Time

Transmit Active Time From The Last

200

Positive Transition

17A

[1]

From Last Positive Transition of the

400

600

Transmit Pair to Differential Output
Approaches within 100 mV of 0 V

17B

[1]

From Last Positive Transition of the

7000

Transmit Pair to Differential Output
Approaches within 40 mV of 0 V

Tx+ and Tx Output Delay Time

TxD Hold Time

TxEN Hold Time

NOTE:

1. Characterized. Not tested.

8020

MD400023/D

Receive Timing

= 0

C to 70

C; V

= 5 V

Symbol

Parameter

Min.

Max.

Unit

CSN Assert Delay Time

240

CSN Deasserts Delay Time (measured

240

from Last Bit Boundary)

23A

CSN Hold Time

23B

CSN Set up Time

RxD Hold Time

RxD Set up Time

[1]

RxC Rise and Fall Time

[1]

During Clock Switch RxC Keeps High Time

200

RxC High and Low Time

[1]

RxC Clock Cycle Time (during

105

data period)

CSN Inhibit Time (on Transmission

4.3

4.6

Node only)

Rx+/Rx Rise and Fall Time

[1]

Rx+/Rx Begin Return to Zero from Last

160

Positive-Going Transition

[1]

RxD Rise Time

[1]

RxD Fall Time

Figure 9. Receive Timing-Start of Packet

t 23A

t 26

t23B

()

(+)

Rx(+)

Rx()

CSN

RxC

RxD

t25

t34

t33

t28

t24

t27

t26

t28

t31

t 21

()

(+)

()

(+)

RxC FOLLOWS TxC

8020

MD400023/D

Collision Timing

= 0

C to 70

C; V

= 5 V

Symbol

Parameter

Min.

Max.

Unit

COLL+ /COLL -- Cycle Time

118

COLL+/COLL -- Rise and Fall Time

COLL+/COLL -- High and Low Time

COLL+/COLL -- Width (measured at 0.3 V)

COLL Asserts Delay Time

300

COLL Deasserts Delay Time

500

CSN Asserts Delay Time

400

CSN Deasserts Delay Time

600

NOTES:
1. COLL + and COLL asserts and deasserts COLL, asynchronously, and asserts and deasserts CSN synchronously with RxC.
2. If COLL + and COLL arrives within 4.5

s from the time CSN was deasserted; CSN will not be reasserted (on transmission node only).

3. When COLL + and COLL terminates, CSN will not be deasserted if Rx+ and Rx are still active.
4. When the node finishes transmitting and CSN deasserted, it cannot be asserted again for 4.5

Figure 11. Collision Timing

COLL

()

(+)

COLL(+)

COLL()

CSN

t54

t55

t57

t51

t53

t52

()

(+)

t58

t56

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