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Электронный компонент: 84220

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MD400177/B
84220
1
Features
s
Single Chip 100BaseTX/100BaseFX/10BaseT
Physical Layer Solution
s
Four Independent Channels in One IC
s
3.3V Power Supply with 5V Tolerant I/O
s
Dual Speed - 10/100 Mbps
s
Half and Full Duplex
s
MII Interface or Reduced Pin Count MII (RMII)
Interface to Ethernet Controller
s
MI Interface for Configuration and Status
s
Optional Repeater Interface
s
AutoNegotiation for 10/100, Full/Half Duplex
s
Meets all Applicable IEEE 802.3, 10BaseT,
100BaseTX and 100BaseFX Standards
s
On Chip Wave Shaping - No External Filters
Required
s
Adaptive Equalizer for 100BaseTX
s
Baseline Wander Correction
s
LED Outputs
Link
Activity
Collision
Full Duplex
Far End Fault (for FX)
10/100
s
160L PQFP
Description
The 84220 is a highly integrated Ethernet Transceiver for
twisted pair and fiber Ethernet applications. The 84220
can be configured for either 100 Mbps (100BaseFX or
100BaseTX) or 10 Mbps (10BaseT) Ethernet operation.
The 84220 consists of four (4) separate and independent
channels. Each channel consists of: 4B5B/Manchester
encoder, scrambler, transmitter with wave shaping and on-
chip filters, transmit output driver, receiver with adaptive
equalizer, filters, baseline wander correction, clock and
data recovery, descrambler, 4B5B/Manchester decoder,
and controller interface (MII or RMII).
The addition of internal output waveshaping circuitry and
on-chip filters eliminates the need for external filters
normally required in 100BaseTX and 10BaseT
applications.
The 84220 can automatically configure itself for 100 or 10
Mbps and Full or Half Duplex operation, for each channel
independently, using the on-chip AutoNegotiation
algorithm.
The 84220 can access eleven 16-bit registers for each
channel through the Management Interface (MI) serial
port. These registers comply to Clause 22 of IEEE 802.3u
and contain configuration inputs, status outputs, and
device capabilities.
The 84220 is ideal as a media interface for 100BaseTX/
100BaseFX/10BaseT switching hubs, repeaters, routers,
bridges, and other multi port applications.
The 84220 is implemented in a low power CMOS
technology and operates with a 3.3V power supply.
84220
99036
Note: Check for latest Data Sheet revision before
starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com
This document is an LSI Logic document. Any
reference to SEEQ Technology should be consid-
ered LSI Logic.
Quad 100BaseTX/100BaseFX/10BaseT
Physical Layer Device
2
MD400177/B
84220
1.0 Pin Configuration
84220
Top View
160 Pin PQFP
2
1
3
7
6
5
4
8
9
GND
13
12
11
10
14
16
15
VDD
JAM
26
25
24
23
22
21
20
19
18
17
36
35
34
33
32
31
30
29
28
27
40
39
38
37
LED0_3
LED1_3
LED2_3
LED0_2
LED1_2
LED2_2
LED0_1
LED1_1
LED2_1
LED0_0
LED1_0
LED2_0
GND
VDD
PHYAD2
PHYAD3
PHYAD4
GND
VDD
RXD3_0
RXD0_0
RXD1_0
RXD2_0
RXDV_0
RXCLK_0
RXER_0/RXD4_0
TXER_0/TXD4_0
TXCLK_0
TXCLK_0
TXEN_0
TXEN_0
TXD1_0
TXD0_0
TXD2_0
TXD3_0
COL_0
VDD
GND
CRS_0
42
41
43
47
46
45
44
48
49
RXCLK_1
53
52
51
50
54
56
55
COL_1
66
65
64
63
62
61
60
59
58
57
76
75
74
73
72
71
70
69
68
67
80
79
78
77
VDD
RXD3_1
RXER_1/RXD4_1
TXCLK_1
GND
CRS_1
GND
VDD
RXD3_2
RXD0_2
RXD1_2
RXD2_2
RXDV_2
RXCLK_2
RXER_2/RXD4_2
TXER_2/TXD4_2
TXCLK_2
TXEN_2
TXD1_2
TXD0_2
TXD2_2
TXD3_2
COL_2
VDD
GND
CRS_2
RXDV_1
RXD0_1
RXD1_1
RXD2_1
TXER_1/TXD4_1
TXD2_1
TXD1_1
TXD0_1
TXEN_1
TXD3_1
RXD3_3
RXD2_3
119
120
118
114
115
116
117
113
112
108
109
110
111
107
105
106
95
96
97
98
99
100
101
102
103
104
85
86
87
88
89
90
91
92
93
94
81
82
83
84
SPEED_3
SPEED_2
LED3_3
LED3_2
LED3_1
LED3_0
SPEED_1
SPEED_0
ANEG
LEDDEF
DPLX_3
REPEATER
MDIO
COL_3
GND
VDD
TXCLK_3
RXD1_3
RXCLK_3
RXDV_3
RXD0_3
RXER_3/RXD4_3
TXER_3/TXD4_3
TXEN_3
TXD3_3
TXD2_3
TXD1_3
TXD0_3
CRS_3
MDINT
MDC
VDD
RMII_EN
DPLX_0
DPLX_1
DPLX_2
VDD
GND
RESET
CLKIN
159
160
158
154
155
156
157
153
152
148
149
150
151
147
145
146
135
136
137
138
139
140
141
142
143
144
125
126
127
128
129
130
131
132
133
134
121
122
123
124
GND
VDD
GND
GND
TPIP_3/FXOP_3
TPIN_3/FXON_3
REXT
VDD
TPOP_3/FXIN_3
GND
VDD
TPON_3/FXIP_3
SD_3/FXEN_3
GND
VDD
TPON_2/FXIP_2
TPOP_2/FXIN_2
SD_2/FXEN_2
TPIN_2/FXON_2
TPIP_2/FXOP_2
TPIP_1/FXOP_1
TPIN_1/FXON_1
VDD
GND
VDD
GND
VDD
GND
TPOP_1/FXIN_1
SD_1/FXEN_1
TPON_1/FXIP_1
TPON_0/FXIP_0
GND
VDD
TPOP_0/FXIN_0
GND
SD_THR
TPIN_0/FXON_0
TPIP_0/FXOP_0
SD_0/FXEN_0
84220
160 Pin PQFP
Top View
MD400177/B
84220
3
1.0 PIN DESCRIPTION
Power Supplies
Pin #
Pin Name
I/O
Description
15
16
22
40
41
60
78
96
100
107
125
128
132
135
144
147
151
154
VDD
---
Positive Supply.
+3.3 +/-5% Volts.
7
14
21
39
56
59
77
95
108
121
122
127
131
134
141
146
150
153
160
GND
---
Ground.
0 Volts.
4
MD400177/B
84220
1.0 PIN DESCRIPTION (cont'd)
Media Interface
Pin #
Pin Name
I/O
Description
126
136
145
155
TPOP_[3:0]/
FXIN_[3:0]
I/O
Twisted Pair Transmit Output, Positive.
Fiber Receive Input, Negative.
129
133
148
152
TPON_[3:0]/
FXIP_[3:0]
I/O
Twisted Pair Transmit Output, Negative.
Fiber Receive Input, Positive.
123
139
142
158
TPIP_[3:0]/
FXOP_[3:0]
I/O
Twisted Pair Receive Input, Positive.
Fiber Transmit Output, Positive.
124
138
143
157
TPIN_[3:0]/
FXON_[3:0]
I/O
Twisted Pair Receive Input, Negative.
Fiber Transmit Output, Negative.
130
137
149
156
SD_[3:0]/
FXEN_[3:0]
I
Fiber Interface Signal Detect Input.
Fiber Interface Enable.
When this pin in not tied to GND, the fiber interface is enabled and this pin
becomes a Signal Detect ECL input. The trip point for this ECL input is
determined by the voltage applied to the SD_THR pin. When this pin is tied
to GND, the fiber interface is disabled (i.e. TP Interface is enabled).
159
SD_THR
---
Fiber Interface Signal Detect Threshold Reference.
The voltage applied
to this pin sets the reference level for the fiber interface SD input pin so that
the device can directly connect SD pin to both 3.3V and 5V fiber optic
tansceivers. Typically, this pin is either tied to GND (for 3.3V) or to an
external voltage divider (for 5V).
140
REXT
---
Transmit Current Set.
An external resistor connected between this pin and GND will set the level
for the transmit outputs.
MD400177/B
84220
5
1.0 PIN DESCRIPTION (cont'd)
Controller Interface (MII & RMII)
Pin #
Pin Name
I/O
Description
87
69
50
31
TXCLK_[3:0]
O
Transmit Clock Output.
These interface outputs provide clocks to external
controllers. Transmit data from the controller on TXD, TXEN, and TXER is
clocked in on the rising edges of TXCLK and CLKIN.
88
70
51
32
TXEN_[3:0]
I
Transmit Enable Input.
These interface inputs must be be asserted active
high to allow data on TXD and TXER to be clocked in on the rising edges of
TXCLK and CLKIN.
[92:89]
[74:71]
[55:52]
[36:33]
TXD[3:0]_3
TXD[3:0]_2
TXD[3:0]_1
TXD[3:0]_0
I
Transmit Data Input.
These interface inputs contain input nibble data to be
transmitted on the TP or FX outputs and are clocked in on rising edges of
TXCLK and CLKIN. In RMII mode, only TXD[1:0] are used.
86
68
49
30
TXER_[3:0]/
TXD4_[3:0]
I
Transmit Error Input.
These interface inputs initiate an error pattern to be
transmitted on the TP or FX outputs and are clocked in on rising edges of
TXCLK when TXEN is asserted.
If the channel is placed in the Bypass 4B5B Encoder mode, these pins are
reconfigured to be the fifth TXD transmit data input, TXD4. In RMII mode,
these pins are not used.
84
66
47
28
RXCLK_[3:0]
O
Receive Clock Output.
These interface outputs provide a clock to the
controller. Receive data on RXD, RXDV, and RXER is clocked out to the
controller on falling edges of RXCLK.
94
76
58
38
CRS_[3:0]
O
Carrier Sense Output.
These interface outputs are asserted active high
when valid data is detected on the receive TP or FX inputs and is clocked
out on the falling edge of RXCLK.
83
65
46
27
RXDV_[3:0]
O
Receive Data Valid Output.
These interface outputs are asserted active
high when valid decoded data is present on the RXD outputs and is clocked
out on falling edges of RXCLK. In RMII mode, these pins are not used.
[79:82]
[61:64]
[42:45]
[23:26]
RXD[3:0]_3
RXD[3:0]_2
RXD[3:0]_1
RXD[3:0]_0
O
Receive Data Output.
These interface outputs contain recovered nibble
data from the TP or FX inputs and are clocked out on the falling edges of
RXCLK. In RMII mode, only RXD[1:0] are used.
85
67
48
29
RXER_[3:0]/
RXD4_[3:0]
O
Receive Error Output.
These interface outputs are asserted active high
when coding or other specified errors are detected on the TP or FX inputs
and are clocked out on falling edges of RXCLK.
If the channel is placed in the Bypass 4B5B Decoder mode, these pins are
reconfigured to be the fifth RXD receive data output, RXD4.
93
75
57
37
COL_[3:0]
O
Collision Output.
These interface outputs are asserted active high when
collision between transmit and receive data is detected.