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Электронный компонент: 84221

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MD400184/A
1
84221
Features
s
Single Chip 100BaseTX/10BaseT
Physical Layer Solution
s
Four Independent Channels in One IC
s
3.3V Power Supply with 5V Tolerant I/O
s
Dual Speed - 10/100 Mbps
s
Half and Full Duplex
s
Reduced Pin Count MII (RMII) Interface to
Ethernet Controller
s
MI Interface for Configuration and Status
s
Optional Repeater Interface
s
AutoNegotiation for 10/100, Full/Half Duplex
Hardware Controlled Advertisement
s
Meets all Applicable IEEE 802.3, 10BaseT,
100BaseTX Standards
s
On Chip Wave Shaping - No External Filters
Required
s
Adaptive Equalizer for 100BaseTX
s
Baseline Wander Correction
s
LED Outputs
Link
Activity
Collision
Full Duplex
10/100
s
128L PQFP
Description
The 84221 is a highly integrated Ethernet Transceiver for
twisted pair and fiber Ethernet applications. The 84221
can be configured for either 100BaseTX or 10BaseT
Ethernet operation.
The 84221 consists of four (4) separate and independent
channels. Each channel consists of: 4B5B/Manchester
encoder, scrambler, transmitter with wave shaping and on-
chip filters, transmit output driver, receiver with adaptive
equalizer, filters, baseline wander correction, clock and
data recovery, descrambler, 4B5B/Manchester decoder,
and controller interface (MII or RMII).
The addition of internal output waveshaping circuitry and
on-chip filters eliminates the need for external filters
normally required in 100BaseTX and 10BaseT
applications.
The 84221 can automatically configure itself for 100 or 10
Mbps and Full or Half Duplex operation, for each channel
independently, using the on-chip AutoNegotiation
algorithm.
The 84221 can access eleven 16-bit registers for each
channel through the Management Interface (MI) serial
port. These registers comply to Clause 22 of IEEE 802.3u
and contain configuration inputs, status outputs, and
device capabilities.
The 84221 is ideal as a media interface for 100BaseTX/
10BaseT switching hubs, repeaters, routers, bridges, and
other multi port applications.
The 84221 is implemented in a low power CMOS
technology and operates with a 3.3V power supply.
84221
99191
Quad 100BaseTX/10BaseT
Physical Layer Device
PRELIMINARY
Note: Check for latest Data Sheet revision before
starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com
This document is an LSI Logic document. Any
reference to SEEQ Technology should be consid-
ered LSI Logic.
2
MD400184/A
84221
1.0 Pin Configuration
2
1
3
7
6
5
4
8
9
TPOP_3
13
12
11
10
14
16
15
TPOP_2
TPIN_2
26
25
24
23
22
21
20
19
18
17
36
35
34
33
32
31
30
29
28
27
38
37
SPEED_3
GND
GND
TPIP_3
TPIN_3
VDD
GND
VDD
TPON_3
GND
VDD
TPON_2
GND
VDD
TPIP_2
REXT
GND
TPIP_1
TPIN_1
VDD
VDD
GND
TPOP_1
TPON_1
GND
VDD
TPON_0
GND
VDD
TPIN_0
TPOP_0
TPIP_0
NC
GND
LED0_3
42
41
43
47
46
45
44
48
49
LED1_1
53
52
51
50
54
56
55
64
63
62
61
60
59
58
57
LED0_2
LED1_2
LED2_1
LED1_0
VDD
RXD0_0
RXER_0
NC
TXEN_0
GND
TXD1_0
TXD0_0
LED0_1
GND
LED2_2
LED0_0
AD_REV
VDD
VDD
GND
GND
80
81
79
75
76
77
78
74
73
69
70
71
72
68
66
67
95
96
97
98
99
100
101
102
65
85
86
87
88
89
90
91
92
93
94
82
83
84
NC
GND
PHYAD3
TXD1_1
TXD0_1
TXEN_1
NC
PHYAD2
RXER_1
NC
NC
CRS_DV2
TXD1_2
ANEG
NC
NC
VDD
GND
CRS_DV1
RXD1_2
RXD0_2
RXER_2
TXD0_2
TXEN_2
NC
REPEATER
LEDDEF
GND
VDD
RXD1_3
RXD0_3
NC
VDD
VDD
CRS_DV0
RXD1_1
RXD0_1
PHYAD4
127
128
117
118
119
120
121
122
123
124
125
126
107
108
109
110
111
112
113
114
115
116
103
104
105
106
LED3_0
DPLX_0
RXER_3
TXEN_3
TXD0_3
TXD1_3
SPEED_1
CRS_DV3
GND
VDD
MDIO
REGDEF
MDC
VDD
DPLX_3
DPLX_2
VDD
GND
RESET
SPEED_0
LED3_1
LED3_2
LED3_3
SPEED_2
DPLX_1
CLKIN
40
39
LED1_3
LED2_3
LED2_0
RXD1_0
84221
128 Pin PQFP
Top View
MD400184/A
3
84221
1.0 PIN DESCRIPTION
Power Supplies
Pin #
Pin Name
I/O
Description
6
9
12
15
23
26
29
32
52
53
56
65
66
84
99
109
113
118
VDD
--
Positive Supply.
+3.3 +/-5% Volts.
2
3
8
11
14
20
25
28
31
37
44
51
55
64
80
83
98
108
119
GND
--
Ground.
0 Volts.
36
60
67
71
74
81
87
90
96
102
NC
--
No Connect.
Reserved for future use, must be left floating for proper
operation.
4
MD400184/A
84221
1.0 PIN DESCRIPTION (cont'd)
Media Interface
Pin #
Pin Name
I/O
Description
7
16
24
33
TPOP_[3:0]
O
Twisted Pair Transmit Output, Positive.
10
13
27
30
TPON_[3:0]
O
Twisted Pair Transmit Output, Negative.
4
18
21
35
TPIP_[3:0]
I
Twisted Pair Receive Input, Positive.
5
17
22
34
TPIN_[3:0]
I
Twisted Pair Receive Input, Negative.
19
REXT
--
Transmit Current Set.
An external resistor connected between this pin and GND will set the level
for the transmit outputs.
MD400184/A
5
84221
1.0 PIN DESCRIPTION (cont'd)
Controller Interface (RMII)
Pin #
Pin Name
I/O
Description
127
CLKIN
I
Clock Input.
This controller interface input latches controller interface data in and out of
the device on rising edges for all channels. There must be a 50 Mhz clock
tied to this pin.
104
91
75
61
TXEN_[3:0]
I
Transmit Enable Input.
These interface inputs must be be asserted active
high to allow data on TXD and TXER to be clocked in on the rising edges of
CLKIN.
[106:105]
[93:92]
[77:76]
[63:62]
TXD[1:0]_3
TXD[1:0]_2
TXD[1:0]_1
TXD[1:0]_0
I
Transmit Data Input.
These interface inputs contain input di-bit data to be
transmitted on the TP outputs and are clocked in on rising edges of CLKIN.
107
97
82
68
CRS_DV[3:0]
O
Carrier Sense Output.
These interface outputs are asserted active high
when valid data is detected on the receive TP inputs and is clocked out on
the rising edge of CLKIN.
[100:101]
[85:86]
[69:70]
[57:58]
RXD[1:0]_3
RXD[1:0]_2
RXD[1:0]_1
RXD[1:0]_0
O
Receive Data Output.
These interface outputs contain recovered di-bit data
from the TP inputs and are clocked out on the rising edges of CLKIN.
103
88
72
59
RXER_[3:0]
O
Receive Error Output.
These interface outputs are asserted active high
when coding or other specified errors are detected on the TP inputs and are
clocked out on rising edges of CLKIN.