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August 2000
1
Copyright 2000 by LSI Logic Corporation. All rights reserved.
L64364 ATMizer II+
ATM-SAR Chip
Addendum
Addendum Number
A000692
Product Code
L64364 ATMizer II+ ATM-SAR Chip
Revision
All
Date Code
All
Order Number for Manual
R14008
This addendum contains changes to the
L64364 ATMizer II+ ATM-SAR
Chip Technical Manual for the LX100 version. The LX100 operates at a
maximum frequency of 100 MHz. The LX100 is functionally the same as
the previous 80 MHz version (LX80), however, some of the AC timing
values change when the SYS_CLK input is 100 MHz. The following
tables show the AC timing changes.
2
L64364 ATMizer II+ ATM-SAR Chip Addendum
Table 1
Secondary Bus Timing
Ref # Signal Timing
Reference
Clock
Min
Max
Units
LX80
LX100
LX80
LX100
S0
SB_CLKO period
12.5
10.0
ns
S1
SB_CLKO duty cycle
(SYS_PLL = 0)
40
60
%
SB_CLKO duty cycle
(SYS_PLL = 1)
45
55
%
S2
SB_CLKO phase delay
(SYS_CLK_PCI = 1, SYS_PLL = 0)
PCI_CLK
4.1
14.7
ns
S3
SB_CLKO phase delay
(SYS_CLK_PCI = 0, SYS_PLL = 0)
SYS_CLK
2.8
12.8
ns
S4
SB_D[31:0] input setup time
SB_CLKO
2.0
1.0
ns
S5
SB_D[31:0] input hold time
SB_CLKO
0.5
ns
S6
SB_D[31:0] output valid
SB_CLKO
3.0
2.5
8.5
5.0
ns
SB_D[31:0] output hold time
SB_CLKO
1.0
ns
SB_D[31:0] output float
SB_CLKO
5.5
5.0
ns
S7
SB_A[21:2] output valid
SB_CLKO
3.0
2.5
9.0
6.0
ns
SB_A[21:2] output hold time
SB_CLKO
1.0
ns
SB_A[21:2] output float
SB_CLKO
5.5
5.0
ns
S8
SB_WEn[3:0] output valid
SB_CLKO
3.0
2.5
9.0
5.5
ns
SB_WEn[3:0] output hold time
SB_CLKO
1.0
ns
SB_WEn[3:0] output float
SB_CLKO
5.5
5.0
ns
S9
SB_OEn[3:0] output valid
SB_CLKO
3.0
2.5
9.0
5.5
ns
SB_OEn[3:0] output hold time
SB_CLKO
1.0
ns
SB_OEn[3:0] output float
SB_CLKO
5.5
5.0
ns
(Sheet 1 of 2)
L64364 ATMizer II+ ATM-SAR Chip Addendum
3
S10
SB_PCSn[4:0] output valid
SB_CLKO
3.0
2.5
9.0
5.5
ns
SB_PCSn[4:0] output hold time
SB_CLKO
1.0
ns
SB_PCSn[4:0] output float
SB_CLKO
5.5
5.0
ns
S11
SB_REQn input setup time
SB_CLKO
2.0
ns
S12
SB_REQn input hold time
SB_CLKO
0.5
ns
S13
SB_GNTn output valid
SB_CLKO
4.0
3.0
10.5
8.0
ns
S14
SB_RDYn setup time
1
SB_CLKO
2.0
S15
SB_RDYn hold time
1
SB_CLKO
0.5
1. While
SB_RDYn
is an asynchronous input, these times are provided if you choose to make the inputs
synchronous.
Table 1
Secondary Bus Timing (Cont.)
Ref # Signal Timing
Reference
Clock
Min
Max
Units
LX80
LX100
LX80
LX100
(Sheet 2 of 2)
4
L64364 ATMizer II+ ATM-SAR Chip Addendum
Table 2
Miscellaneous Timing
Ref #
Signal Timing
Reference
Clock
Min
Max
Units
LX80
LX100
LX80
LX100
M1
SYS_CLK frequency
(SYS_PLL = 0)
80.0
100.0
MHz
M2
SYS_CLK duty cycle
(SYS_PLL = 0)
40
60
%
M3
SYS_CLK frequency
(SYS_PLL = 1)
7.5
40.0
50.0
MHz
M4
SYS_CLK duty cycle
(SYS_PLL = 1)
40
60
%
M5
SE_DI input setup time
SE_CLK
10
ns
M6
SE_DI input hold time
SE_CLK
5
ns
M7
SE_ACK input setup time
SE_CLK
10
ns
M8
SE_ACK input hold time
SE_CLK
5
ns
M9
JTAG_TCLK frequency
0
20
MHz
M10
JTAG_TCLK duty cycle
40
60
%
M11
JTAG_TDI setup time
JTAG_TCLK
1
ns
M12
JTAG_TDI hold time
JTAG_TCLK
3
ns
M13
JTAG_TM setup time
JTAG_TCLK
1
ns
M14
JTAG_TM hold time
JTAG_TCLK
3
ns
M15
JTAG_TDO output delay
JTAG_TCLK
7
15
ns
M16
JTAG_TRSTn pulse width
JTAG_TCLK
20
ns
L64364 ATMizer II+ ATM-SAR Chip Addendum
5
Table 3
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
DD
Supply Voltage
3.135
3.3
3.465
V
V
CC
PCI clamp diode voltage
4.75
5.0
5.25
V
V
ILP
Voltage Input Low - PCI Bus
-
0.5
0.8
V
V
IHP
Voltage Input High - PCI Bus
2.0
5.5
V
V
OLP
Voltage Output Low - PCI Bus
0.2
0.55
V
V
OHP
Voltage Output High - PCI Bus
2.4
V
DD
V
V
ILS
Voltage Input Low - Secondary Bus
-
0.5
0.8
V
V
IHS
Voltage Input High - Secondary Bus
2.0
V
DD
+ 0.3
V
V
OL
Voltage Output Low - Secondary
Bus
0.2
0.4
V
V
OH
Voltage Output High - Secondary
Bus
2.4
V
DD
V
V
IL
Voltage Input Low - all other signals
-
0.5
0.8
V
V
IH
Voltage Input High - all other
signals
2.0
5.5
V
V
OL
Voltage Output Low - all other
signals
0.2
0.4
V
V
OH
Voltage Output High - all other
signals
2.4
V
DD
V
I
IL
Input current low
V
IN =
V
SS
-
10
-
1
A
I
ILP
Input current low - pins with
pull-ups
V
IN =
V
SS
-
214
-
115
-
35
A
I
IH
Input current high
V
IN =
V
DD
1
10
A
I
IHP
Input current high - pins with
pull-downs
V
IN =
V
DD
35
115
222
A
I
OZ
3-state leakage current
V
IN =
V
SS
- V
DD
-
10
10
A
I
DD
Dynamic supply current
80 MHz operation
740
830
mA
100 MHz operation
925
1040
mA
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