ii
This document is preliminary. As such, it contains data derived from functional
simulations and performance estimates. LSI Logic has not verified either the
functional descriptions, or the electrical and mechanical specifications using pro-
duction parts.
Document DB14-000002-01, Second Edition (August 1996)
This document describes revision B of LSI Logic Corporation's L64381 4-Port
Ethernet Controller (Quad CASCADE) Device and will remain the official refer-
ence source for all revisions/releases of this product until rescinded by an update.
To receive product literature, call us at 1.800.574.4286 (U.S. and Canada);
+32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, and Europe)
and ask for Department JDS; or visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or lia-
bility arising out of the application or use of any product described herein, except
as expressly agreed to in writing by LSI Logic; nor does the purchase or use of
a product from LSI Logic convey a license under any patent rights, copyrights,
trademark rights, or any other of the intellectual property rights of LSI Logic or
third parties.
Copyright 1995, 1996 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
LSI Logic logo design and CASCADE are registered trademarks of LSI Logic
Corporation. All other brand and product names may be trademarks of their
respective companies.
Preface
iii
Preface
This book is the primary reference and technical manual for the L64381
4-Port Ethernet Controller (Quad CASCADE) Device. It contains a com-
plete functional description for the L64381 and includes complete physi-
cal and electrical specifications for the L64381.
Audience
This document assumes that you have some familiarity with networking,
microprocessors, and related support devices. The people who benefit
from this book are:
Engineers and managers who are evaluating the L64381 for possible
use in a networking system
Engineers who are designing the L64381 into a system
Organization
This document has the following chapters and appendixes:
Chapter 1, Introduction
, describes the general characteristics and
capabilities of the L64381 product.
Chapter 2, Registers
, defines the on-chip registers.
Chapter 3, Signal Descriptions
, describes the input, output, and
bidirectional signals of the L64381 chip.
Chapter 4, L64381 Operation
, provides a detailed description of the
functional blocks and interfaces within the L64381 chip.
Chapter 5, Statistics Counters
, lists the purpose and contents of
the 32-bit Statistics Counters.
Chapter 6, Instruction Set
, defines the L64381 instruction set and
provides each instruction's valid modes.
Chapter 7, Specifications
, provides the AC and DC specifications
and packaging information for the L64381 chip.
iv
Preface
Appendix A, Customer Feedback
, includes a form that you may
use to fax us your comments about this document.
Related
Publications
Compacted and Scalable Dedicated Ethernet (CASCADE) Core Techni-
cal Manual, Order No. C14015
Conventions
Used in This
Manual
The first time a word or phrase is defined in this manual, it is
italicized.
The following signal naming conventions are used throughout this
manual:
A level-significant signal that is true or valid when the signal is LOW
always has an overbar (
) over its name.
An edge-significant signal that initiates actions on a HIGH-to-LOW
transition always has an overbar (
) over its name.
The word
assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix "0x" before the num-
ber--for example, 0x32CF. Binary numbers are indicated by a sub-
scripted "2" following the number--for example, 0011.0010.1100.1111
2
.
A
word is 32-bits long. A halfword is 16-bits long. A byte is 8-bits long.
Contents
v
Contents
Chapter 1
Introduction
1.1
Overview
1-1
1.2
Key Features
1-3
1.2.1
Ethernet Core
1-3
1.2.2
Internal Architecture
1-4
1.2.3
Bus Interface
1-4
1.2.4
Processor Interface
1-5
1.2.5
Key Programmable Features
1-5
Chapter 2
Registers
2.1
Register Addresses
2-2
2.2
Configuration Registers
2-3
2.2.1
Configuration Register 0
2-3
2.2.2
Configuration Register 1
2-4
2.2.3
Packet Configuration Register
2-9
2.3
Ethernet Address Registers
2-10
2.4
Error Registers
2-11
2.4.1
Error Register 0
2-11
2.4.2
Error Register 1
2-12
2.5
Error Mask Registers
2-13
2.5.1
Error Mask Register 0
2-13
2.5.2
Error Mask Register 1
2-14
2.6
Statistics Counters Registers
2-15
2.6.1
Statistics Counters Address Register
2-15
2.6.2
Statistics Counters Data-In Registers
2-16
2.6.3
Statistics Counters Data-Out Registers
2-16
2.7
Data FIFO Registers
2-17
2.7.1
Data FIFO Address Register
2-17
2.7.2
Data FIFO Data-In Registers
2-19
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