May 1997
ii
Rev. letter
Copyright 1995, 1996, 1997 by LSI Logic Corporation. All rights reserved.
Document DB14-000026-01, Second Edition (May 1997)
This document describes Revision A of LSI Logic Corporation's L64704 Satellite
Decoder and will remain the official reference source for all revisions of this prod-
uct until rescinded by an update.
To receive product literature, call us at 1.800.574.4286 (U.S. and Canada);
+32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, and Europe)
and ask for Department JDS; or visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or lia-
bility arising out of the application or use of any product described herein, except
as expressly agreed to in writing by LSI Logic; nor does the purchase or use of
a product from LSI Logic convey a license under any patent rights, copyrights,
trademark rights, or any other of the intellectual property rights of LSI Logic or
third parties.
Copyright 1995, 1996, 1997 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
LSI Logic logo design is a registered trademark of LSI Logic Corporation. All
other brand and product names may be trademarks of their respective
companies.
Contents
iii
Rev. letter
Copyright 1995, 1996, 1997 by LSI Logic Corporation. All rights reserved.
May 1997
Contents
Chapter 1
Introduction
1.1
General Description
1-1
1.2
Typical Application
1-3
1.3
Features Summary
1-5
Chapter 2
L64704 Signal Definitions
2.1
Channel Interface
2-3
2.2
Channel Clock Recovery
2-3
2.3
Channel Data Output Interface
2-4
2.4
Phase-Locked Loop Interface
2-5
2.5
Carrier Synchronizer Loop Controls
2-6
2.6
Microcontroller Interface
2-7
2.7
Control Signals
2-9
Chapter 3
L64704 Registers
3.1
L64704 Register Overview
3-2
3.1.1
Parallel Host Mode Register Operations
3-7
3.1.2
Programming Using the Serial Interface
3-9
3.2
Reset and How It Affects Registers
3-9
3.3
Group 0, 1 Address Pointer Register
3-10
3.4
Group 2 Registers
3-11
3.4.1
System Mode Register (SMR)
3-11
3.4.2
System Status Register (STS)
3-16
3.5
Group 3 Registers
3-20
3.5.1
Group 3, APR 0, 1 RS Corrected Error Count
3-21
3.5.2
Group 3, APR 2, 3 RS Uncorrected Error Count
3-21
3.5.3
Group 3, APR 4, 5 Viterbi Bit Error Count
3-22
3.5.4
Group 3, APR 6 Control Input and SNR
3-22
3.5.5
Group 3, APR 6, 7 Measured VCO Frequency
3-23
May 1997
iv
Contents
Rev. letter
Copyright 1995, 1996, 1997 by LSI Logic Corporation. All rights reserved.
3.5.6
Group 3, APR 8 AGC Loop Voltage Meter
3-23
3.5.7
Group 3, APR 9 Carrier and FEC Synchronization Status
3-23
3.5.8
Group 3, APR 10 RI Readback
3-25
3.5.9
Group 3, APR 11 RQ Readback
3-26
3.6
Group 4 Registers
3-26
3.6.1
Group 4, APR 0 PLL Parameter N
3-28
3.6.2
Group 4, APR 1 PLL Parameter S
3-28
3.6.3
Group 4, APR 2 PLL Parameter T, Demodulator
and Symbol Select
3-29
3.6.4
Group 4, APR 3 PLL Parameter M, Transport and
Viterbi Code Rate Select
3-30
3.6.5
Group 4, APR 4 Viterbi Max Data Bit Count 1
3-31
3.6.6
Group 4, APR 5, 6, 7 Viterbi Max Data Bit Count 2 3-31
3.6.7
Group 4, APR 8 Viterbi Maximum Bit Error Count 3-32
3.6.8
Group 4, APR 9 Synchronization Word
3-32
3.6.9
Group 4, APR 10 BER Monitor and Mismatching
Bits in Sync 2 Tracking Mode
3-33
3.6.10
Group 4, APR 11 Synchronization States and
BCLKOUT Format
3-34
3.6.11
Group 4, APR 12 Output Control
3-36
3.6.12
Group 4, APR 13 PLL Reset
3-37
3.6.13
Group 4, APR 14 Clock Loop Control 1
3-37
3.6.14
Group 4, APR 15 Clock Loop Control 2
3-39
3.6.15
Group 4, APR 16, 17 Nominal Frequency of
Clock Input
3-40
3.6.16
Group 4, APR 18 Clock Ratio
3-40
3.6.17
Group 4, APR 19 Power Reference Level
3-41
3.6.18
Group 4, APR 20 Power Estimation Bandwidth
and I/Q DC Offset
3-41
3.6.19
Group 4, APR 21 Scale Factor for DEMI and
DEMQ Outputs
3-42
3.6.20
Group 4, APR 22 SNR Estimator Threshold
3-42
3.6.21
Group 4, APR 23 Carrier Loop DC Offset
Compensation Value
3-42
3.6.22
Group 4, APR 24 Carrier Frequency Reference
Period
3-42
3.6.23
Group 4, APR 25, 26 Carrier Loop Filter Gain
(P and D Terms)
3-43
May 1997
Contents
v
Rev. letter
Copyright 1995, 1996, 1997 by LSI Logic Corporation. All rights reserved.
3.6.24
Group 4, APR 27 Carrier Lock Detector Threshold
3-43
3.6.25
Group 4, APR 28 Carrier Synchronizer Sweep
Rate
3-44
3.6.26
Group 4, APR 29, 30 Carrier Synchronizer Sweep
Upper Limit
3-44
3.6.27
Group 4, APR 31, 32 Carrier Synchronizer Sweep
Lower Limit
3-45
3.6.28
Group 4, APR 33 Carrier Loop Configuration
Register
3-45
3.6.29
Group 4, APR 34 Set to 0
3-48
3.6.30
Group 4, APR 35 Decoder Configuration Register 3-49
3.6.31
Group 4, APR 36 External Output Control Bits
and Reset Register
3-50
Chapter 4
Channel Interfaces and Data Control
4.1
Data Control and Clocking Schemes
4-2
4.2
Channel Data Input Interface
4-4
4.3
Channel Data Output Interface
4-5
4.4
PLL Clock Generation
4-5
4.5
Data Path Output Configurations
4-12
4.5.1
Descrambler Output
4-13
4.5.2
Synchronization Stage 3 Output
4-15
4.5.3
Reed-Solomon Decoder Output
4-15
4.5.4
Deinterleaver Output
4-16
4.5.5
Synchronization Stage 2 Output
4-17
4.5.6
Viterbi Decoder Output
4-17
4.5.7
Viterbi Depuncture/Synchronization Output
4-18
4.5.8
QPSK Demodulator Output
4-19
Chapter 5
Demodulator Module Functional Description
5.1
Overview
5-1
5.2
DC Offset Compensation and Coupling to ADC Output
5-3
5.3
Decimation Filters
5-3
5.4
Matched Filter
5-4
5.5
Channel Clock Recovery
5-4
5.5.1
Input Decimation
5-5
5.5.2
Clock Acquisition and Tracking Modes
5-5
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