December 2000
1
Copyright 2000 by LSI Logic Corporation. All rights reserved.
The LSI402ZX is a 16-bit fixed-point digital signal processor (DSP) based
on the LSI Logic ZSP400 DSP core. The LSI402ZX contains an entire
DSP system on a single chip, and is designed for applications requiring
high throughput and flexibility coupled with a high speed I/O, such as
communications infrastructure equipment.
The LSI402ZX operates at a clock rate of 200 MHz for a maximum
effective throughput of 800 RISC-like MIPS. The LSI402ZX RISC
architecture is easy to program and uses a four-way superscalar pipeline
with five stages to process up to 20 instructions at a time. The
processor's execution unit contains two multiply-accumulate units (MACs)
and two arithmetic logic units (ALUs). The LSI402ZX also supports single
cycle add-compare-select, bit manipulation, and 32-bit arithmetic and
logic operations.
Figure 1 shows a block diagram of the LSI402ZX.
LSI402ZX Digital Signal
Processor
Preliminary Datasheet
LSI402ZX Digital Signal Processor
3
The LSI402ZX provides 62 Kwords of on-chip instruction zero wait-state
RAM and 62 Kwords of on-chip data zero wait-state RAM supported by
an eight channel DMA controller, which can transfer instructions and
data. For optimum I/O performance and flexibility, the LSI402ZX contains
two high speed time-division multiplex (TDM) serial ports, a single 16-bit
host interface port, an external memory interface unit, and an eight-pin
programmable I/O port. An IEEE 1149.1 JTAG port supports program
download and debug.
LSI Logic provides a software development kit containing an assembler,
linker, GUI debugger, simulator, C compiler, and JTAG-based hardware
emulator.
The LSI402ZX is fabricated in the LSI Logic G12TM-p technology. The
LSI402ZX is powered by a 1.8 V core and a 3.3 V I/O supply, and is
packaged in a 208-ball mini-BGA package.
4
LSI402ZX Digital Signal Processor
LSI402ZX Features
Processor
RISC architecture
Instruction grouping by hardware
for parallel execution
Four-way superscalar architecture
Two multiply-accumulate units
(MACs)
Two arithmetic logic units (ALUs)
800 RISC-like MIPS maximum
throughput at 200 MHz
Multitasking support
Low latency interrupt structure with
programmable priority levels
Efficient context switch support
On-chip PLL for clock generation
Applications
Optimized for communications
infrastructure applications
Single-cycle dual 16-bit MAC with
40-bit result
Single-cycle high-precision (32-bit)
MAC with 40-bit result
Two-cycle complex multiply
Single-cycle add-compare-select
for Viterbi decoding
Technology
208-ball mini-BGA package
Memory
62 Kword internal instruction RAM
62 Kword internal data RAM
Eight channel DMA controller
Supports fast I/O transfers
Transfer instructions or data to and
from internal memory
32-bit external memory interface unit
Glueless interface to SBSRAMs
20-bit address space (2 Mwords) for
both instruction and data memory
Glueless interface to 16-bit SRAMs and
peripherals
2 Kword internal boot ROM
I/O
Two high-speed serial ports with
TDM mode
H.100/H.110 bit stream compatible
8/16-bit host processor interface
8-pin programmable I/O port
IEEE 1149.1 compliant JTAG port
Timers
Two 16-bit timers with a 6-bit prescale
value
Single-shot and continuous mode
LSI402ZX Digital Signal Processor
5
Functional Description
The LSI402ZX contains an entire DSP system and allows attachment of
external memory and peripherals. Refer to Figure 1 for a block diagram
of the LSI402ZX.
The pipeline control unit attempts to group instructions for parallel
execution, resolving data and resource dependencies in the program
sequence. By scheduling instructions for execution by the four functional
units (the two MACs and two ALUs), it relieves the programmer and the
compiler of this task. The pipeline control unit also synchronizes the
entire operation of the pipeline and processes interrupt requests.
The LSI402ZX is a four-way superscalar processor that employs a
five-stage pipeline. At any time, there may be a maximum of twenty
instructions in various stages of execution in the pipeline. The five
pipeline stages of this machine are Fetch/Decode (F/D), Group (G),
Read (R), Execute (E), and Write Back (W).
The pipeline control unit also contains two 16-bit timers for interrupt
generation. Each timer is fully programmable and has a 6-bit prescaler.
Once enabled, the timers count down from the user-specified initial value
to zero at a rate determined by the scaled output of the LSI402ZX output
clock. The timers generate an interrupt when zero is reached. The timers
can be configured to automatically reload with the initial count to
generate periodic interrupts.
The interrupt control unit interfaces with the pipeline control unit. A
nonmaskable interrupt (NMI) pin into the LSI402ZX allows for a separate
interrupt control unit.
The data unit fetches data and sends them to the data cache. The data
unit contains the data prefetcher and cache, and contains the logic for
two circular buffers.
The instruction unit fetches instructions, decodes and dispatches them,
and places the instructions in the instruction cache. The instruction unit
contains the instruction cache, the instruction prefetcher, and the
instruction dispatch unit. The instruction unit also contains branch
prediction logic.
PDF 
ZIP