DB08-000245-00
RapidChipTM Xtreme
Platform ASIC Family
ADVANCE
DATASHEET
J u l y 2 0 0 4
ii
Copyright 2004 by LSI Logic Corporation. All rights reserved.
This document is advance. As such, it describes a product under development.
This information is intended to help you evaluate the product. LSI Logic reserves
the right to change or discontinue this proposed product without notice.
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB08-000245-00, July 2004
This document describes the LSI Logic Corporation RapidChip Xtreme platform
ASIC family and will remain the official reference source for all revisions/releases
of this product until rescinded by an update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright 2004 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
LSI Logic, the LSI Logic logo design, CoreWare, G12, Gflx, GigaBlaze,
HyperPHY, Pad on I/O, RapidChip, RapidReady, RapidWorx, System CoreWare,
and ZSP are trademarks or registered trademarks of LSI Logic Corporation. ARM
is a registered trademark of ARM Ltd., used under license. MIPS and MIPS32
are trademarks or registered trademarks of MIPS Technologies, Inc. All other
brand and product names may be trademarks of their respective companies.
EH
To receive product literature, visit us at
http://www.lsilogic.com
For news and updates about RapidChip technology products, visit
www.rapidchip.com
For a current list of our distributors, sales offices, and design resource
centers, visit
http://www.lsilogic.com/contacts/index.html
RapidChip Xtreme Platform ASIC Family
iii
Copyright 2004 by LSI Logic Corporation. All rights reserved.
Preface
This document is an overview of the RapidChipTM technology and a
detailed description of the RapidChip Xtreme platform ASIC family, which
is based on the GflxTM process technology. These descriptions include
functional block descriptions, configurability, testing, packaging data, and
specifications.
Audience
This document assumes you are familiar with custom logic design, either
with ASICs or FPGAs, and related support tools. The people who benefit
from this book are:
Engineers and managers who are evaluating the RapidChip Xtreme
platform ASICs for possible use in a system
Engineers who are designing the RapidChip Xtreme platform ASICs
into a system
Organization
This document has the following sections:
Section 1, "RapidChipTM Technology Overview,"
provides a high-level
description of the RapidChip technology.
Section 2, "RapidChip Xtreme Platform ASIC Overview,"
is a
functional description of the RapidChip Xtreme platform ASIC family.
Section 3, "RapidChip Xtreme Platform ASIC Details,"
provides
detailed information on each RapidChip Xtreme platform ASIC family
member.
Section 4, "Specifications,"
provides the electrical specifications for
the RapidChip Xtreme platform ASIC family.
iv
Preface
Copyright 2004 by LSI Logic Corporation. All rights reserved.
Section 5, "Packaging,"
is an overview of the packaging of the
RapidChip Xtreme platform ASIC family.
Appendix A
, "
Packaging Details
," provides detailed information about
the packaging and the pinouts of the RapidChip Xtreme platform
ASIC family.
Related Publications
RapidChipTM Memory Overview, document number DB06-000471-01
ARM966EJ-S Technical Reference Manual, ARM Ltd.
MIPS32 4KEc Processor Core Datasheet, MIPS Technologies, Inc.
Preliminary Gflx-r RapidChip Cell Technology Databook, document
number DB04-000094-02
Using RapidBuilder to Generate a Clock Factory, Application Note,
document number DB06-000470-01.
Conventions Used in This Manual
Hexadecimal numbers are indicated by the prefix "0x" --for example,
0x32CF. Binary numbers are indicated by the prefix "0b" --for example,
0b0011.0010.1100.1111.
RapidChip Xtreme Platform ASIC Family
v
Copyright 2004 by LSI Logic Corporation. All rights reserved.
Contents
1
RapidChipTM Technology Overview
1
1.1
RapidChip Platform ASICs
2
1.2
RapidChip Platform ASIC Building Blocks
2
1.3
Packaging
5
1.4
Library Elements
5
1.5
RapidWorx Design Methodology
6
2
RapidChip Xtreme Platform ASIC Overview
12
2.1
Feature Summary
14
2.2
Naming Conventions
15
2.3
Family Members
15
2.4
Memory Implementation
16
2.5
Configurable I/Os
21
2.6
Clock Networks and PLLs
22
2.7
High-Speed SERDES Cores
27
2.8
Double-Data-Rate (DDR) PHY Support
38
2.9
Embedded Microprocessor Support
41
3
RapidChip Xtreme Platform ASIC Details
44
3.1
RC11XT404
44
3.2
RC11XT416
49
3.3
RC11XT432
53
3.4
RC11XT531
58
4
Specifications
64
4.1
VDD Terminology
65
4.2
Absolute Maximum Ratings
66
4.3
Recommended Operating Conditions
67
4.4
SSTL2 Buffer
67
4.5
HSTL Buffers
72
4.6
2.5 V LVDS Buffers
77
4.7
3.3 V LVDS Buffers
81
4.8
PECL Buffer
85
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