DB14-000253-02
RC1800
Foundation Slice Family
DATASHEET
A p r i l 2 0 0 3
Advance
ii
Rev. A
Copyright 2003 by LSI Logic Corporation. All rights reserved.
This document is advance. As such, it describes a product under development.
This information is intended to help you evaluate the product. LSI Logic reserves
the right to change or discontinue this proposed product without notice.
Document DB14-000253-02, April 2003
This document describes LSI Logic Corporation's RC1800 Foundation Slice
family and will remain the official reference source for all revisions/releases of this
product until rescinded by an update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of LSI
Logic or third parties.
Copyright 2003 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
LSI Logic, the LSI Logic logo design, CoreWare, G12, Gflx, GigaBlaze,
RapidChip, and RapidSlice are trademarks or registered trademarks of LSI Logic
Corporation. ARM is a registered trademark of ARM Ltd., used under license. All
other brand and product names may be trademarks of their respective
companies.
EH
To receive product literature, visit us at http://www.lsilogic.com.
For news and updates about RapidChip products, visit
http://rapidchip.lsilogic.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/index.html
RC1800 Foundation Slice Family Datasheet
iii
Rev. A
Copyright 2003 by LSI Logic Corporation. All rights reserved.
Preface
This document provides an overview of the RapidChip program and
describes the functional blocks within the RC1800 Foundation Slice
family in detail. The detailed information provided includes functional
block descriptions, configurability, testing, packaging data, and
specifications.
Audience
This document assumes you are familiar with custom logic design, either
with ASICs or FPGAs, and related support tools. The people who benefit
from this book are:
engineers and managers who are evaluating the RC1800 Foundation
Slices for possible use in a chip
engineers who are designing the RC1800 Foundation Slices into a
system
Organization
This document has the following sections and appendixes:
Section 1, "The RapidChipTM Program,"
provides a high-level
description of the RapidChip program.
Section 2, "RC1800 Foundation Slices,"
provides detailed
descriptions of the configurable I/Os, IPs, memories, PLLs, and
clocking resources that are available in the RC1800 Foundation Slice
family.
Section 3, "Library Elements,"
briefly describes the available libraries.
Section 4, "Design Tools,"
presents an overview of the design flow
process and the RTL generation tools used.
iv
Preface
Rev. A
Copyright 2003 by LSI Logic Corporation. All rights reserved.
Section 5, "Packaging,"
provides the mechanical drawings and
specifications for the initial package drawings.
Section 6, "Specifications,"
lists the electrical specifications and AC
timing parameters for the RC1800 Foundation Slice family.
Related Publications
Overview of G12
Cell-Based Technologies, DB06-000160-04
GigaBlaze
G12TM Rev 1.0 Core Design Manual, DB14-000079-02
G12 DDR Core (cw000701_2_0) Design Manual, DB14-000169-03
ARM 926EJ-S Technical Reference Manual, ARM Ltd.
Conventions Used in This Manual
Hexadecimal numbers are indicated by the prefix "0x" --for example,
0x32CF. Binary numbers are indicated by the prefix "0b" --for example,
0b0011.0010.1100.1111.
DB14-000253-02
April 2003
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Rev. A
Copyright 2003 by LSI Logic Corporation. All rights reserved.
RC1800 Foundation
Slice Family
Datasheet
Contents
1
The RapidChipTM Program
4
1.1
RapidSlice Platform Elements
5
Transistor Fabric and R-Cells
5
Embedded Memory Blocks
5
IP Blocks
5
Configurable I/Os
6
Typical RapidSlice Platform
7
1.2
Packaging
7
1.3
RC1800 Foundation Slices
8
1.4
Features Summary
10
2
RC1800 Foundation Slices
11
2.1
Configurable I/Os
11
2.2
GigaBlaze SERDES Transceivers
12
2.3
Double-Data-Rate (DDR) PHY Support
15
DDR PHY Resources Key Features
16
Memory I/O Types
17
2.4
Embedded Microprocessor Support
17
MMU
19
Caches and Write Buffer
19
Bus Interface Unit (BIU)
19
Tightly Coupled Memory (TCM) Interface
19
2.5
Memory Integration
20
Diffused Memories
20
R-Cell Memories
22
Configuration of Memories
22
2.6
PLLs and Clocks
23
General-Purpose PLL Resources
24
Clock Factories
29
3
Library Elements
31
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