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Электронный компонент: SYM53C895

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SYM53C895 Data Sheet
SYM53C895
PCI-to-Ultra2 SCSI I/O Processor
The SYM53C895 is a PCI-to-Ultra2 SCSI I/O
Processor incorporating Universal Low Voltage
Differential (LVD) signaling for SCSI. LSI Logic'
implementation of LVD transceivers is called
LVDlinkTM which meets all of the requirements of
the SPI-2 standard. LVDlink removes the distance
and device constraints that exist in today's Ultra
SCSI single-ended designs while continuing to
offer higher data transfer rates. As compared to
Ultra SCSI designs, the SYM53C895 provides
twice the performance and allows four times the
cable length and number of connected devices.
Whether you are moving from Ultra SCSI or Fast
SCSI, Ultra2 SCSI provides a high performance
I/O migration path while preserving your existing
PCI-SCSI software investment.
The SYM53C895, with integrated LVDlink
transceivers, provides the data reliability of
differential signaling without the added cost of
external differential transceivers. The device can
support up to 12-meter cables and up to 16 LVD
devices on a wide LVD SCSI bus, with the same
cables and connectors defined in the SCSI-3
Parallel Interface ANSI standard (refer to Table 1).
For backward compatibility to existing single-
ended devices, the Universal I/O features of
LVDlink transceivers allow the chip to switch
between LVD and single-ended mode. In single-
ended mode, the SYM53C895 performs
synchronous data transfers up to Ultra SCSI rates,
subject to Ultra SCSI distance and device
constraints.
Ultra2 SCSI Performance
The performance advantage of Ultra2 SCSI over
Fast SCSI-2 and Ultra SCSI is most noticeable in
applications that use large block size transfers such
as video production and editing, or medical
imaging, where large files must be stored or
transported. The high SCSI bandwidth of Ultra2
SCSI, and the improvements in distance,
connectivity, and reliability, make the SYM53C895
an ideal host connection to a RAID controller.
Ultra2 SCSI performance along with the other new
features in the SYM53C895 make it ideal for these
and other demanding applications in the high
performance RAID subsystem, workstation, and
server markets (refer to Table 2).
Lr
Benefits
Ultra2 SCSI I/O Processor
Performs SCSI data transfers up to 80 MB/s,
synchronous operation on a wide LVD SCSI bus
Transfers SCSI data synchronously up to Ultra
SCSI speeds in single-ended mode
Allows total SCSI cable lengths up to 12 meters
(longer cables may be possible in point-to-point
solutions)
Allows up to 16 LVD SCSI devices on the wide bus
Extra large 816 byte DMA FIFO for improved bus-to-
bus speed matching
Accommodates extra data while data bursting is
occurring
Provides better support for large block size
transfers at Ultra2 SCSI speeds
Allows the chip to handle a full disk sector
Supports up to 512 byte bursts across the PCI bus
31 levels of SCSI Synchronous Offset
Increases the pace of synchronous transfers to
match Ultra2 SCSI transfer speed
On-chip LVDlink Universal Low Voltage Differential
transceivers
Do not require external precision regulators or
resistors to operate
Allows greater device connectivity and longer
cable length
Transceivers switch between single-ended and LVD
to support backward compatibility
Provides reliability and distance of differential
SCSI without the cost of external differential
transceivers
LVDlink supports a long-term performance
migration path to over 100 megatransfers per
second
On-chip clock quadrupler for achieving 160 MHz
internal SCSI clock while using an external 40 MHz
oscillator
208-pin PQFP or 292-pin BGA
PCI Features
Connects directly as one load to the PCI bus
816 byte DMA FIFO for improved speed matching
Functions as full 32 bit PCI DMA Bus Master
Complies with PCI 2.1 Specification
Supports 33 MHz PCI Bus zero wait state operation
Supports maximum burst transfer rate of 132 MB/s
Supports PCI extended access cycles
SCSI Features
Includes 4 KB internal RAM for SCSI SCRIPTSTM
instruction storage, to reduce or eliminate instruction
fetches over the PCI bus
Prefetches up to 8 dwords of SCSI SCRIPTS
instructions, reducing PCI bus overhead
Expands arithmetic capabilities with enhanced
Register Move instruction support
Supports SCSI SCRIPTS Load and Store instructions,
for more efficient moving of data between memory
and chip register space
Integrates local memory bus for BIOS storage,
including EPROMs and FLASH memory
LVDlink transceivers utilize LSI Logic TolerANT active
negation technology for improved single-ended SCSI
signal integrity
SYM53C895
Block
Diagram
LVDlink - LSI Logic Universal LVD
Transceivers
To balance backward compatibility with I/O performance,
LSI Logic has integrated LSI Logic Universal LVDlink
transceivers on the SYM53C895. Using the Differential
Sense (DIFFSENS) signal to detect the bus cabling
condition, the universal features of LVDlink transceivers
support single-ended, high power differential (using
external transceivers), or LVD SCSI modes, depending
on the type of devices connected to the bus.
Software Support
LSI Logic provides a complete software solution with
BIOS and drivers to support the SYM53C895 and the
entire SYM53C8XX family of PCI-SCSI I/O Processors.
Drivers are available for DOS, Novell NetWare, Windows
NT, UnixWare, Windows 95, OS/2 and SCO
OpenServer.
SCSI Bus Widths and Throughput
Bus Width (bits)
SCSI-1
Fast SCSI
Fast Wide SCSI
Ultra SCSI
Wide Ultra SCSI
Ultra2 SCSI
Wide Ultra2 SCSI
8
8
16
8
16
8
16
5
10
20
20
40
40
80
Bus Throughput (MB/s)
Table 2.
Maximum Cable Length In Meters
1
Maximum Drives
LVD
3
Differential
Single-ended
8
8
16
8
4
16
8
4
8
16
SCSI-1
Fast SCSI
Fast Wide SCSI
Ultra SCSI
Ultra SCSI
Wide Ultra SCSI
Wide Ultra SCSI
Wide Ultra SCSI
Ultra2 SCSI
2
Ultra2 SCSI
2
6 m
3 m
3 m
1.5 m
3 m
-
1.5 m
3 m
-
-
25 m
25 m
25 m
25 m
-
25 m
-
-
-
-
12 m
12 m
12 m
12 m
-
12 m
-
-
12 m
12 m
1
This parameter may be exceeded in point-to-point and engineered applications.
2
Single-ended and high-power differential are not defined at Ultra2 speeds.
3
Preliminary expectations. The final specified cable length may vary.
Table 1.
LSI Logic logo design, ATMized, ATMizer, BitBuster, CASCADE, CoreWare and CoreWare logo design, FlexCore, G10 and G10 logo design, HYDRA, It
Takes Two To Make One Of A Kind, LSI Links, MiniRISC, MiniSIM, SeriaLink, The System on a Chip Company and VISC are registered trademarks, and
Cablestream, Cafe, C-MDE, Compacted Array, Cream, DCAM, DiscRISC, DiskRISK, Espresso, First-Time-Right, FlexStream and FlexStream logo
design, G11 and G11 logo design, G12 and G12 logo design, GigaBlaze, Grounds, Hyper-LVDS, HyperPHY, Integra, Internet on a Chip, Logically
Speaking, Merlin, Mint, Mint Technology, Mint logo design, Mocha, Netcore, Planet LSI, PowerPlay, Right-First-Time, Scenario, SerialICE, Sugar,
Symbios, Taking Cameras Digital, TinyRISC, TinySIM, WINS, TolerANT, LVDlink, and SCRIPTS are trademarks of LSI Logic Corporation. ARM is
a registered trademark of Advanced RISC Machines Limited, used under license; OakDSPCore is a registered trademark of DSP Group Inc., used under
license; SparKIT is a trademark of SPARC International, Inc. and is exclusively licensed to LSI Logic Corporation. All other brand and product names may
be trademarks of their respective companies.
LSI Logic Corporation reserves the right to make changes to any products and services herein at any time without notice. LSI Logic does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by LSI
Logic; nor does the purchase, lease, or use of a product or service from LSI Logic convey a license under any patent rights, copyrights, trademark rights,
or any other of the intellectual property rights of LSI Logic or of third parties.
1999 by LSI Logic Corporation. All rights reserved.
An ISO 9001 Registered Company
Printed in the U.S.A.
T9984I
0599
1.5M
1-800-856-3093
www.lsilogic.com
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