USB Hub Core
Hub Core for Universal Se rial Bus Solutions
Ove rview
LSI Logic's USB Hub Core, a component of LSI Logic's comprehensive
Universal Serial Bus (USB) solution set, is a flexible and configurable core
that supports additional USB connections within a USB system, enabling the
design of highly-integrated hub-based, single-chip system solutions.
Targeted for hub-enabled applications such as flat-panel displays and printers,
the USB Hub Core functions as the interface between a USB Host and one or
more USB devices, providing additional ports for peripheral connectivity and
expansion.
Simplified Design Integration
The USB Hub Core is USB specification-compliant and offers a self-con-
tained implementation that simplifies design integration. To simplify design
integration, the cores are provided in both encrypted RTL and unencrypted
SCAN-inserted netlist forms. RTL speeds the development of the system
ASIC architecture at the behavioral simulation level.
The USB Hub Core simplifies the design
of highly integrated hub-enabled system
ASIC's.
The USB Hub Core is part of a complete
suite of USB cores spanning the entire USB
topology, including peripherals and hub
applications.
As an element of LSI Logic's proven
CoreWare library, the USB Hub Core is fully
supported by industry-leading design
methodology and complements other cores
in the family.
The USB Hub Core simplifies the design of highly integrated hub-enabled system ASICs.
USB Hub Core
Fe atures
USB Specification Revision 1.1 Compliant
"Firm" implementationFixed netlist with
flexible layout guidelines
Programmable number of downstream ports
and configurable power option support
Integrated Digital PLL
Supports low- and full-speed data rates
Gated clock option
SCAN-inserted netlist
Interfaces with LSI Logic's USB transceiver
I/Os
Verified functionality and timing in LSI Logic's
ASIC technologies
Simplified Design Integration (continued)
The netlist accelerates the structural implementation, and with an optimized,
proven, fixed netlist in LSI Logic's ASIC technology, frees the designer to
concentrate on other value-added aspects of the system ASIC.
Cost-Ef fective and Diffe re ntiated Single-Chip USB Solutions
In addition, by combining the USB Hub Core and LSI Logic's USB transceiv-
er I/Os with other CoreWare products, and customer-defined logic, designers
can quickly create cost-effective and differentiated single-chip USB system
solutions.
The USB Hub Core is part of a complete suite of USB cores spanning the
entire USB topology, including peripherals and host applications. As an ele-
ment of LSI Logic's proven CoreWare
library, it is fully supported by indus-
try-leading design methodology and complements the other cores, including
MIPS, ARM, Ethernet, and PCI, in the family.
The USB Hub Core simplifies the design of highly integrated hub-enabled
system ASIC's.
USB Hub Core Description
The USB Hub Core manages hub connectivity on a per-port basis and handles
communications with the Host. The number and power option support of the
downstream hub ports can be easily configured to customize the implementa-
tion based on the application requirements. Together with separate USB
transceivers from LSI Logic's I/O library, the USB Hub Core provides a com-
plete solution to create applications with integrated hub support.
USB Hub Core Components
The USB Hub Core is composed of the following blocks:
Frame Timer Block:
The Frame Timer Block monitors the host's Start of Frame (SOF) signals
to synchronize the USB Hub Core to the host frame timing and generates
the End of Frame points (EOF1 and EOF2) used when establishing port
connectivity.
Benefits
Ensures "Hot Plug and Play" interoperability
More flexible layout interface vs. fixed layout
and placement
Performance and gate count optimized for
each application
No external components required
Compatible with all USB peripherals and
hosts
Reduces power consumption
Simplifies test verification
External transceiver chip not required
Fast time to market with Right-First-TimeTM
methodology designs
Hub Repeater Block:
The Hub Repeater Block manages connectivity between the Root Port and
the downstream Root Ports and is the interface to the Upstream Root Port,
the USB Hub Controller, and the Port State Machine Blocks.
Hub Functional State Machine Block:
This Block controls the suspend and resume logic and monitors the root port
signals. If the USB Hub Core remains idle for 3 milliseconds, the block will
place the Core into suspend. It will reactivate the Core when downstream
activity is detected or the host issues a resume signal.
Hub Controller Block:
The Hub Controller Block implements the standard USB device. It includes
the Serial Interface Engine (SIE) which performs parallel-to-serial and serial-
to-parallel data conversion, clock embedding and recovery, data encoding/
decoding and error checking functions between the Root Hub and the USB.
Power Switching and Over-Current Control Block:
This Block generates the power switching control signals to all downstream
Port State Machine Blocks and monitors for over-current conditions on all
downstream ports.
Hub Command Interpreter Block:
The Hub Command Interpreter Block is an interface between the USB Hub
and Port State Machine Blocks. It performs decoding of USB hub-class com-
mands and provides the host with hub and port status information.
Port State Machine Blocks:
These blocks control the downstream ports with the dedicated Port State
Machine per port. Each state machine detects connect/disconnect events and
the speed of the attached device; it enables, disables or suspends the port; it
reports status change and converts full-speed signaling to low speed and vice
versa, as required.
USB Hub Core
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