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tional 2.048 Mbps (E1) applications. It features a constant
low output impedance transmitter allowing for high trans-
mitter return loss in T1/E1 applications. Transmit pulse
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lengths and cable types.
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at 3 Hz, and is microprocessor controllable through a serial
interface.
It offers a variety of diagnostic features including transmit
and receive monitoring. The device incorporates an on-
chip crystal oscillator, and also accepts digital clock inputs.
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rate provides clock stabilization. Refer to Application
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is within two bits of overflowing or underflowing, the ES
adjusts the output clock by 1/8 of a bit period. The ES pro-
duces an average delay of 16 bits in the receive path.
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The transceiver incorporates a Driver Performance Moni-
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transformer. The DPM output goes High upon detection of
63 consecutive zeros. It is reset when a one is detected on
the transmit line, or when a reset command is received.
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shown in Figure 2. The output driver maintains a constant
low output impedance regardless of whether it is driving
marks or spaces.
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The LXT304A can be controlled through hard-wired pins
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MODE pin logic level. The LXT304A can also be com-
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valid, relative to the Serial Clock (SCLK) or RCLK as
listed in Table 3.
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Figure 5 is a 2.048 Mbps E1 TWP application using 15
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loss is not a critical factor, a 1:1 or 1:1.26 transformer with-
out in-line resistors provides maximum power savings. The
LXT304A is shown in Hardware Mode with a typical E1/
CRC4 Framer. The hard-wired control lines for TAOS,
LLOOP and RLOOP are individually controllable, and the
LLOOP and RLOOP lines are also tied to a single control
for the Reset function. This configuration is illustrated
with a crystal in place to enable the LXT304A Jitter Atten-
uation Loop, and a single power supply bus.
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Existing D4 Channel Bank architectures frequently em-
ploy: (1) a plug-in card for T1 pulse generation (6.0 V
peak); and (2) a separate card for pulse shaping and Line
Build-Out (LBO). The LXT304A integrates the functions
of both cards on a single chip producing a DSX-1 compat-
ible, 3.0 V peak output pulse with a standard transformer.
In new designs, the LXT304A can replace two cards with
one. However, the LXT304A is also compatible with ex-
isting dual-card architectures. With an appropriate output
transformer, the LXT304A can produce full 6.0 V peak am-
plitude pulses suitable for D4 Channel Bank applications
with separate pulse shaping/LBO cards.
To achieve the 6.0 V peak output, the FCC Part 68-010
Equalizer Code setting is used. (EC = 010.) With the stan-
dard 1:1.15 transformer, this code produces a 3.0 V peak
pulse. However, doubling the transformer turns ratio to
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load over operating temperature range. Includes device and load. Digital input lev-
els are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load.
2. Functionality of pins 23 and 25 depends on mode. See Host/Hardware Mode descriptions.
3. Output drivers will output CMOS logic levels into CMOS loads.
4. Except MTIP and MRING ILL = 50 A.
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3. Circuit attenuates jitter at 20 dB/decade above the corner frequency.
4. In accordance with ITU G.703/ETS 300166 return loss specifications when wired per Figure 7 (E1).
5. Guaranteed by design.
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Power dissipation while driving 75
load over operating temperature range. Includes device and load. Digital input lev-
els are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load.
2. Functionality of pins 23 and 25 depends on mode. See Host/Hardware Mode descriptions.
3. Output drivers will output CMOS logic levels into CMOS loads.
4. Except MTIP and MRING ILL = 50 A.
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