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Электронный компонент: GT-48208

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Galileo
GT-482xx
GT-48212 / GT-48208 / GT-48207
Advanced Switched Ethernet Controllers for 10+10/100 BaseX
Preliminary
Revision 1.2
1/27/99
FEATURES
www.galileoT.com info@galileoT.com Tel: 408-367-1400 Fax: 408-367-1401
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Please contact Galileo Technology for possible
updates before finalizing a design.
Single-chip Switched Ethernet Controllers for
10 and 10/100Base-X
- Provides packet switching functions between
eight or 12 Ethernet ports and two Auto-
Negotiated on-chip Fast Ethernet ports
- Switch expansion via Fast MII port
Three versions for different cost/performance
points
- GT-48212: 12 10BaseT ports, two 100BaseX
ports and advanced management features
- GT-48208: eight 10BaseT ports, two 100BaseX
ports and advanced management features
- GT-48207: eight 10BaseT ports, two 100BaseX
ports with no management features
Low-cost 32-bit CPU interface for
management
- Glueless interface to IDT 3041, Motorola
ColdFire, Intel i960R/Jx CPUs, and GT-641xx
controllers.
- Simple interface to other 32/64-bit CPUs
Management CPU not required
- Allows for cost sensitive unmanaged designs
Eight or Twelve 802.3 compliant Ethernet
ports
- 10Mbps Half-Duplex or 20Mbps Full-Duplex
- Serial mode selectable per port: 10Base-T or FL
Two Fast Ethernet Media Access Controllers
- Direct Interface to MII
- Half/Full Duplex Support
- IEEE 802.3 100Base-TX, T4, and FX compatible
- Full MII Management Support (MDC/MDIO)
- Auto-Negotiation supported through MII
Interface
Flow Control on all ports
- Standard 802.3x flow control for Full Duplex
mode
- Back pressure for Half Duplex mode
Direct support for packet buffering
- 1Mbyte: using one device - 256Kx32-bit
Synchronous graphics RAM (SGDRAM)
- 4Mbyte: using two devices - 1Mx16bit SDRAM
- Up to 2K buffers, 1536-bytes each, dynamically
allocated to the receive queues and CPU
High observability LED interface
- Three pin serial LED interface for additional
status information per port
Advanced address recognition on-chip
- Intelligent address recognition mechanism
enables forwarding rate at full wire speed
- Self-learning mechanism
- Supports up to 8K Unicast addresses and
unlimited Multicast/Broadcast addresses
- Multicast address support in Address Table
- Broadcast storm filtering
Extensive network management support
- Repeater MIB counters allowing implementation
of four RMON groups
- Hardware assist for Spanning Tree algorithm
- CPU access to Address Table
- CPU Query - Ability to read the information from
the Address Table
- Ability to define static addresses
- Monitoring (sniffer) mode
Port locking for security
Automatic address aging support
Priority queuing based on MAC address or
802.1Q tag
Port and MAC address based VLAN
IP Multicast support
Flexible software or hardware intervention in
packet routing decisions
Packet sampling management technology
GT-482xx Advanced Switched Ethernet Controllers for 10+10/100 BaseX
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2
Revision 1.2
- Takes "snapshots" of packets and counters at
programmable intervals
- Allows for the implementation of HP-EASE or
sampled RMON with low-cost CPUs
12 General Purpose Output pins (LEDs, etc.)
3.3V with 5V tolerant I/Os
208 pin PQFP package
B l o c k D i a g r a m o f T y p i c a l M a n a g e d S w i t c h
( T w o 1 0 0 M b i t P o r t s + 1 2 1 0 M b i t P o r t s )
CPU Bus (when CPU present)
C P U
(optional)
12 x 10BaseT
2 x 100BaseTX
G T - 4 8 2 1 2
S D R A M
10BaseT Filters
1 0 0 B a s e T X
P H Y / X C V R
CPU Bus (when CPU present)
G T - 4 8 2 1 2
S D R A M
10BaseT Filters
12 x 10BaseT
1 0 0 B a s e T X
P H Y / X C V R
1 x 100BaseTX
G T - 4 8 2 1 2
S D R A M
10BaseT Filters
12 x 10BaseT
1 0 0 B a s e T X
P H Y / X C V R
1 x 100BaseTX
F A S T M I I
C P U
(optional)
B l o c k D i a g r a m o f T y p i c a l M a n a g e d S w i t c h
( T w o 1 0 0 M b i t P o r t s + 2 4 1 0 M b i t P o r t s )
GT-482xx Advanced Switched Ethernet Controllers for 10+10/100 BaseX
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Revision 1.2
3
Table of Contents
1.
General Description ..................................................................................................... 9
1.1
Fast Ethernet Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2
Ethernet Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3
Flow Control and Back Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4
CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5
Synchronous GRAM/DRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6
Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7
IP Multicast and VLAN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.8
Priority Queueing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.9
Network Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.10 Differences Between the GT-48212, GT-48208 and GT-48207 . . . . . . . . . . . . . . . . . . . 12
2.
Pinout .......................................................................................................................... 13
2.1
Pin Functions and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.
Galaxy Family Overview ............................................................................................ 19
3.1
Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2
Address Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3
Packet Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4
Packet Forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.
Microarchitectural Overview ..................................................................................... 21
5.
Buffers and Queues ................................................................................................... 23
5.1
Rx Buffer Threshold Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2
Head-of-Line Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.
MAC Address Table ................................................................................................... 26
6.1
Forwarding Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2
Port Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3
Address Learning Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4
Locked Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.5
Address Entry Update and Query from CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.6
Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7
Address Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.8
Static Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.9
Address Recognition Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.10 Forwarding Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.
Packet Forwarding ..................................................................................................... 33
7.1
Forwarding a Unicast Packet to a Local Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2
Forwarding a Multicast Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.3
Forwarding a Packet to the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.4
Forwarding a Packet from the CPU to the GT-482xx . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.5
Intervention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.6
IGMP Packet Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.7
CRC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.8
Tx Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
GT-482xx Advanced Switched Ethernet Controllers for 10+10/100 BaseX
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Revision 1.2
8.
Fast Ethernet Interfaces ............................................................................................ 37
8.1
10/100 MII Compatible Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.2
Media Access Control (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.3
Auto-Negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.4
Backoff Algorithm Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.5
Data Blinder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.6
Inter-Packet Gap (IPG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.7
10/100 Mbps MII Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.8
10/100 Mbps MII Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.9
10/100 Mbps Full-duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.10 Illegal Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.11 Partition Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.12 Back Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.13 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.14 802.1q VLAN Tagging Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.15 MII Management Interface (SMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.16 Link Detection and Link Detection Bypass (ForceLinkPass) . . . . . . . . . . . . . . . . . . . . . . 43
8.17 Using the MII Interfaces to Connect Two (or More) Galaxy Devices . . . . . . . . . . . . . . . . 44
9.
Ethernet (10Mbps) Interfaces .................................................................................... 45
9.1
Media Access Control (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2
Illegal Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.3
Duplex Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.4
Backoff Algorithm Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.5
Manchester Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.6
Link Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.7
Data Blinder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.8
Inter-Packet Gap (IPG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.9
Partition Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.10 802.1q VLAN Tagging Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.11 Back Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.12 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.13 Serial Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.14 Physical Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.15 Serial Link Status Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.
Enabling/Disabling Ports........................................................................................... 48
11.
Network Management Support ................................................................................. 49
11.1 Repeater MIB Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.2 Monitoring (Sniffer) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.3 Spanning Tree (BPDU) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.4 Broadcast Storm Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.
Packet Sampling Technology (HP-EASE) ................................................................ 51
12.1 Packet Sampling Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.2 EASE Functionality on the GT-482xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.3 Ease Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.4 EASE Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.5 Sampled Packet Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
GT-482xx Advanced Switched Ethernet Controllers for 10+10/100 BaseX
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12.6 Error Source Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.7 Enabling/Disabling EASE Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
13.
LED Support ............................................................................................................... 54
13.1 LED Indications Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.2 Detailed LED Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13.3 LED Signal Timing Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
13.4 LED Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
14.
Interrupts .................................................................................................................... 65
15.
RESET Configuration................................................................................................. 66
15.1 Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
15.2 Configuration Input Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
16.
CPU Hardware Interface and Address Mapping...................................................... 69
16.1 Register and Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
16.2 CPU Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
16.3 CPU Interface Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
16.4 Selecting the CPU Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
16.5 GT-482xx Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
16.6 CPU Interface Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
16.7 CPU Interface Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
16.8 Memory Endianess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
17.
SDRAM Interface ........................................................................................................ 80
17.1 DRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
17.2 DRAM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
18.
Register Tables .......................................................................................................... 81
18.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
18.2 Port MIB Counters (14 Blocks), Offset (start): 0x600, 0xA00, 0xE00, 0x1200 . . . . . . . 107
19.
GT-482xx Pinout Differences .................................................................................. 112
19.1 Pinout Differences between GT-48207, GT-48208, and GT-48212 Devices . . . . . . . . 112
19.2 Using a GT-48212 in a GT-48208/7 Socket: Disabling Unused Ethernet Ports . . . . . . 112
19.3 Using a GT-48212 or GT-48208 in a GT-48207 Socket: Disabling Unused
CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
19.4 CClk in an Unmanaged System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
20.
GT-482xx Pinout Tables, 208-PQFP ....................................................................... 114
21.
DC Characteristics - PRELIMINARY/SUBJECT TO CHANGE ) .......................... 120
21.1 Thermal Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
22.
AC Timing - TARGET/SUBJECT TO CHANGE....................................................... 122
23.
Packaging ................................................................................................................. 127
24.
Document History .................................................................................................... 129
Appendix A ....................................................................................................................... 135