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Tag

SRAM

Cache

Data

SRAM

External Agent

(System Controller)

GT-64012

QS3383

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ExtReq*

ValidIn*

ysA

ysC

Tag

Secondary Cache Address

TagOp[1:0]

VIMux

TValidIn*

GValidIn*

GRdRdy*
GExtReq*

GRelease*

SCAdv*, SCAdS*
SCDOE*, SCDWr*

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SCALE*
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64-BIT MIPS PROCESSOR

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- 256KByte
- 512KByte

· Fixed line size

- 4 double-words (32 bytes)

· Write-through policy
· Direct mapping
· Physical address and tag
· Zero wait-states for cache hit
· Supports industry standard synchronous burst SRAMs

- 32Kx18
- 64Kx18
- 32Kx36

· Moderate Data SRAM speed required

- 12ns for 50MHz

· Supports de-facto standard cache tags

- 8Kx8 tag (IDT71B74)
- 16Kx15 tag (IDT71215)

· Read burst latency of 3-1-1-1

· Supports all write patterns (DDDD or slower)
· Supports the R4700's special write modes
-

Pipeline

- Re-issue

· "Transparent" architecture

- Design with no logic changes into existing systems

· Easy evaluation via Galileo-2 CPU module

- Fits into existing CPU sockets with no board
changes to R4600/R4700 system

· Compatible with Galileo GT-64010 System Controller
· Minimizes use of external logic components

- Only 4 standard logic components needed besides
memory

· Simple way to boost CPU performance

- Typical improvement range of 20%-100% depend-
ing on system architecture and code

· 5 Volt operation

- Easy to incorporate into a 3.3V environment

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The GT-64012 is a secondary cache controller for the MIPS R4600/4650/4700/5000, which can help system perfor-
mance increase by anywhere between 20% and 100%, depending on the system architecture and the nature of the
software run by it. The GT-64012 is also compatible with the R4400PC and R4000PC.

The architecture of the GT-64012 enables the addition of a secondary cache to an existing system without changes to
the system ASICs or controller logic, for a cost-effective increase in system performance. Brand new designs can attain
further optimizations.

The GT-64012 is designed with BiCMOS technology to ensure support of fast processor speeds, and to reduce the
speed requirement of the tag and data SRAMs, thus reducing system cost. The GT-64012 supports up to 50MHz clock
speeds in the bus with no wait-states, which means that it supports the R4600/R4700-100MHz in up to divide-by-2
mode, the R4600/R4700-133MHz, and R4600/R4700-150MHz in up to divide-by-3 mode, and the R4700-166MHz and
R4700-175MHz in up to divide-by-4 mode.

The GT-64012 supports industry standard synchronous SRAMs with a sub-block ordering burst sequence like the one
found in Intel processors, thus taking advantage of the economies of scale associated with the PC industry. By support-
ing synchronous SRAMs, zero wait-state is attained without the need for interleaving, thus reducing component count,
board space, and loading, while improving granularity. Only 2 or 4 data SRAMs are needed to build a 256KByte or
512KByte cache. At the maximum speed of 50MHz, the GT-64012 only requires the 12ns version of these SRAMs, thus
keeping system cost at reasonable levels.

The GT-64012 is designed to work with de-facto standard cache tags, very fast SRAMs that include the tag comparison
logic on-board. This simplifies the design and ensures no wait-state operation. For a 256KByte cache, a depth of 8K is
needed in the cache tag, whereas for a 512KByte cache a tag depth of 16K is necessary. The required speed for the
address-to-match comparison is 10ns, which is not the fastest tag SRAM speed available. The tag SRAM requirement
can be reduced to a single chip in the case of the IDT71215 16Kx15 device if a 512KB cache is used, or two IDT71B74
8Kx8 devices if a 256KB cache is used.

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The GT-64012 is housed in a low-cost surface mounted 44-pin PLCC package.

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A system can be easily retrofitted in one of two ways. First, the R4700 CPU can be replaced by a CPU module that
contains all the secondary cache components. An example of this is the Galileo-2 module, which is available for evalu-
ation, and the reference design of which is available for free (please request your copy). Secondly, a motherboard can
be easily redesigned to incorporate the cache subsystem knowing that no changes are necessary to the existing con-
troller logic or ASICs. In either case, all that is needed is to adjust the software or firmware to recognize the presence of
the secondary cache.

Brand new designs can use the schematics of the Galileo-2 module as a reference, to facilitate the design process.
New designs can reduce the "miss" penalty to 0 clock cycles for writes and non-cacheable read transactions, and 1
clock cycle for cacheable reads. This can be achieved by connecting the system controller to the CPU's ValidOut* sig-
nal and the Tag SRAM's Hit signal.

The Galileo-2 module consists of a small PC board that is plugged into an existing R4600 or R4700 179-PGA socket,
replacing the CPU. The CPU is then plugged into a similar 179-PGA socket on the Galileo-2 module. The module con-
tains the GT-64012 secondary cache controller, a 16Kx15 Tag SRAM, four 32Kx18 or 64Kx18 burst SRAMs, and 4
standard logic components. A block diagram of it appears on the cover.

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When a new System ASIC is being designed and the GT-64012 is used, it is possible to improve system perfor-
mance during reads.

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The GT-64012 distinguishes between two types of Reads: uncacheable (partial reads) and cacheable (block reads).

All partial reads (SysCmd[7:5] = 0 and SysCmd[3] = 1), are forwarded to the System a cycle later than the issue cycle
on the CPU bus. As both the SysAD and SysCmd buses are point-to-point connections between the CPU and the Sys-
tem, a newly designed System ASIC may monitor SysCmd, ValidOut*, TagOp0, and TagOp1 to detect a partial read
request. When a partial read is detected, with both TagOp0 and TagOp1 inactive, the System ASIC may start process-
ing the transaction immediately, knowing that a cycle later it should ignore the GValidOut* generated by the GT-64012.
One cycle is therefore saved.

Block reads are checked by the GT-64012 for Hit or Miss in the Tag SRAM. The lookup is done one cycle after Valid-
Out* is asserted. No action is taken by the GT-64012 until the CPU bus is released (read issue cycle). One cycle after
the CPU bus is released the GT-64012 asserts GValidOut* if the lookup turned to be a Miss so as to forward the
request to the system.

A newly designed System ASIC may monitor the Hit signal during the look-up phase to determine in advance if the
request will be forwarded to the system or not. If a Hit occurs, no action should be taken as data will be returned from
the secondary cache. If a Miss occurs, the System ASIC may start processing the request ignoring the GValidOut*
which will be generated by the GT-64012 at least a cycle later. Care should be taken to keep track over CPU bus status
(released or not) before SysAD and SysCmd get driven by the System; i.e., GRelease* should be monitored for asser-
tion before SysCmd and SysAD are truly released. In systems where RdRdy* is constantly asserted, GRelease* will be
asserted two cycles after the issue cycle.

In most systems, RdRdy* is constantly asserted or even tied to ground so the same cycle in which ValidOut* is firstly
asserted is also the issue cycle. Such systems may simplify the decision making involved in this process.

The GT-64010 System Controller from Galileo takes advantage of this methodology to provide a system designer with
maximum performance when also using the GT-64012 Secondary Cache Controller.

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It is possible to utilize a simple software mechanism to determine if a GT-64012 is present in the system or not. The
sequence of transactions to be made is as follows (all are addressed to the same cache line):

1. cacheable read (block);

2. first level cache invalidate (cache operation)

or two first level cache line replacements;

3. uncacheable write;

4. cacheable read.

If the returned data from step 4 is updated by the written data in step 3, the GT-64012 is not present in the system,
and vice versa.

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It is easy to interface the 5V GT-64012 to a 3.3V CPU subsystem. The block diagram that appears on the cover needs
to be augmented only by one component. The existing components are already 3.3V-compatible.

The burst synchronous SRAMs are available in 3.3V Vcc versions with 5V-tolerant inputs and thus can interface directly
to the GT-64012.

Tag SRAMs like the IDT71215 can have their I/Os working from a 5V or 3.3V source, while the supplied Vcc is 5V, and
thus can work in a mixed voltage environment.

The FCT163501 3.3V bidirectional latches can be used instead of the 5V version, since their inputs are still 5V tolerant.

The QuickSwitches used to gate the ValidOut and ValidIn signals provide an effective mechanism to interface between
5V and 3.3V.

Consequently, the only extra component needed is another QuickSwitch to interface the GT-64012 outputs ExtReq*
and GRelease*, plus the I/Os SysCmd[8:3], to the 3.3V subsystem. The QS3384 when supplied with 4.3V works as an
effective 5V to 3.3V converter with zero delay. This is illustrated in the figure below.

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GRelease*

ExtReq*

SysCmd[8:3]

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