Galileo
GT64120
System Controller For RC4650/4700/5000
and RM526X/527X/7000 CPUs
Datasheet
Revision 1.4
SEP 14, 1999
F
EATURES
www.galileoT.com support@galileoT.com
Please contact Galileo Technology for possible
updates before finalizing a design.
Integrated system controller with PCI interface
for high-performance embedded control
applications.
Supports all 64-bit bus MIPs CPUs:
- RM526X, RM527X and RM7000 from QED.
- RC4650 through RC5000 from IDT.
- R5000 compatibles from various vendors.
75MHz CPU bus frequency.
Supports up to four GT64120 devices on the
same SysAD bus.
64 byte CPU write posting buffer.
- 64-bit wide, eight levels deep.
- Accepts CPU writes with zero wait-states.
CPU address remapping to resources.
256KB or 512KB zero-wait state secondary
cache support.
- L2 of R4xxx.
- R5000, L3 of R7000.
Backward Software Compatibility with GT-
64010A and GT-64011
SDRAM controller:
- Supports 16, 64 and 128-Mbit SDRAMs.
- 1- 4 banks supported, 512MB address space.
- Supports 2-way & 4-way SDRAM bank
interleaving.
- 64-bit data width.
- Parity support.
- Zero wait-state interleaved burst accesses at
75MHz.
Supports the VESA Unified Memory
Architecture (VUMA) Standard.
- Allows for external masters access to SDRAM
directly.
Device controller:
- 5 chip selects.
- Programmable timing for each chip select .
- Supports many types of standard memory and I/
O devices.
- Up to 640MB address space.
- Optional external wait-state support.
- 8-,16-,32- and 64-bit width device support.
- Support for boot ROMs.
- Parity supported for devices.
Four channel DMA controller:
- Chaining via linked-lists of records.
- Byte address boundary for source and
destination.
- Moves data between PCI, memory, and
devices.
- Two 64-byte internal FIFOs allowing two
transfers to take place concurrently.
- Alignment of source and destination addresses.
- DMAs can be initiated by the CPU writing to a
register, external request via DMAReq* pin, or
an internal timer/counter.
- Termination of DMA transfer on each channel.
- Descriptor ownership transfer to CPU.
- Fly-By support for local data bus.
- Override capability of source/destination/record
address mapping.
One 32-bit wide timer/counter, 3 24-bit wide
timer/counters.
GT64120 System Controller For RC4650/4700/5000 and RM526X/527X/7000 CPUs
II
Revision 1.4
GALI
LEO
TECHNOL
OGY
CONF
IDENT
IAL
DO N
OT
RE
PRODUC
E
Part Number: GT64120
Publication Revision: 1.4
Galileo Technology, Inc.
No part of this datasheet may be reproduced or transmitted in any form or by any means,
electronic or mechanical, including photocopying and recording, for any purpose without
the express written permission of Galileo Technology, Inc.
Galileo Technology, Inc. retains the right to make changes to these specifications at any
time, without notice.
Galileo Technology, Inc. makes no warranty of any kind, expressed or implied, with
regard to this material, including, but not limited to, the implied warranties of merchant-
ability or fitness for any particular purpose. Galileo Technology, Inc. further does not
warrant the accuracy or completeness of the information, text, graphics, or other items
contained within these materials. Galileo Technology, Inc. makes no commitment to
update nor to keep current the information contained in this document.
Galileo Technology, Inc. assumes no responsibility for the use of any circuitry other than
circuitry embodied in Galileo Technology, Inc. products. No other circuit patent licenses
are implied.
Galileo Technology, Inc. products are not designed for use in life support equipment or
applications in which if the product failed it would cause a life threatening situation. Do
not use Galileo Technology, Inc. products in these types of equipment or applications.
Contact your local sales office to obtain the latest specifications before finalizing your
product.
Galileo Technology, Inc.
142 Charcot Avenue
San Jose, California 95131
Phone: 1 408 367-1400
Fax: 1 (408) 367-1401
E-mail: info@galileot.com
www.galileoT.com
Other brands and names are the property of their respective owners.
Two 32-bit or one 64-bit high-performance PCI
2.1 compliant devices:
- Dual mode PCI interface can be used as two
independent 32-bit interfaces (synchronous or
asynchronous to each other) or as a single 64-
bit interface.
- 192-bytes of posted write and read prefetch
buffers for each PCI interface.
- 32/64-bit PCI master and target operations.
- PCI bus speed of up to 66MHz with no wait
states.
- Universal PCI buffers.
- Operates either synchronous or asynchronous
to CPU clock.
- Burst transfers used for efficient data movement.
- Doorbell interrupts provided between CPU and
PCI.
- Supports flexible byte swapping through PCI
interface.
- Synchronization barrier support for PCI side.
- PCI address remapping to resources.
- PCI configuration registers can be accessed
from both CPU and PCI side.
Host to PCI bridge:
- Translates CPU cycles into PCI I/O or Memory
cycles.
- Generates PCI Configuration, Interrupt
Acknowledge, and Special cycles on PCI bus.
PCI to Main Memory bridge:
- Supports fast back-to-back transactions.
- Supports memory and I/O transactions to
internal configuration registers.
- Supports locked operations.
- I
2
OIndustry Standard I
2
O messaging unit on
primary 32-bit PCI interface (also available in
64-bit mode).
- Expansion ROM support.
PCI Hot-Plug and CompactPCI Hot-Swap
capable compliant
- All inputs are 5V tolerant
Advanced 0.35 micron process
GT64120 System Controller For RC4650/4700/5000 and RM526X/527X/7000 CPUs
Revision 1.4
III
Table of Contents
1.
Overview ................................................................................................................... 11
1.1
CPU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2
SDRAM and Device Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4
DMA Engines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.
Pin Information......................................................................................................... 21
2.1
Pin Assignment Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2
GT64120B0 and GT64120B1/3/4 Pinout Differences . . . . . . . . . . . . . . . . . . . 213
3.
Address Space Decoding........................................................................................ 31
3.1
Two Stage Decoding Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2
Disabling the Device Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3
DMA Unit Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4
Address Space Decoding Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.5
Default Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.6
CPU and PCI Address Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
3.7
CPU PCI Decode Override (1 Gbyte and 2 Gbyte PCI Address Spaces) . . . . . . . . . . 315
3.8
DMA PCI Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
4.
CPU Interface Description....................................................................................... 41
4.1
CPU Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2
SysAD, SysADC, and SysCmd Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3
Operation of WrRdy* and the Internal Write Posting Queues . . . . . . . . . . . . . . . . . . . . 47
4.4
MIPs Write Modes and Write Patterns Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.5
CPU Interface Endianess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.6
Burst Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.7
Multiple GT64120 Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.
Memory Controller ................................................................................................... 51
5.1
SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2
Connecting the Address Bus to the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
5.3
Programmable SDRAM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
5.4
SDRAM Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
5.5
SDRAM Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
5.6
Unified Memory Architecture (UMA) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
5.7
Device Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
5.8
Programming the ADP lines for other Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
5.9
Memory Controller Differences Between B0 and B1 . . . . . . . . . . . . . . . . . . . . . . . . 530
5.10 Memory Controller Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
GT64120 System Controller For RC4650/4700/5000 and RM526X/527X/7000 CPUs
IV
Revision 1.4
6.
PCI Interfaces ........................................................................................................... 61
6.1
Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.2
PCI Master Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3
PCI Target Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.4
PCI Synchronization Barriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
6.5
PCI Master Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
6.6
Target Configuration and Plug and Play . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
6.7
PCI Parity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
6.8
PCI Bus/Device Bus/CPU Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
6.9
64-bit PCI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
6.10 Retry Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
6.11 Locked Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
6.12 Hot-Swap Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6
6.13 PCI Interface Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
7.
Intelligent I/O (I2O) Standard Support .................................................................... 71
7.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.2
I2O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.3
Enabling I2O Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.4
Register Map Compatibility with the i960Rx Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.5
Message Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.6
Doorbell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.7
Circular Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.8
Index Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8.
DMA Controllers ....................................................................................................... 81
8.1
DMA Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.2
DMA Channel Control Register (0x840 - 0x84c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.3
Restarting a Disabled Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.4
Reprogramming an Active Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.5
Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.6
Current Descriptor Pointer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.7
Design Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8.8
Initiating a DMA from a Timer/Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
8.9
DMA Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
9.
Timer/Counters......................................................................................................... 91
10.
Interrupt Controller ................................................................................................ 101
10.1 Interrupt Cause Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
10.2 Interrupt Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
10.3 Interrupt Summaries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
10.4 Interrupt Select Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
11.
Reset Configuration ............................................................................................... 111
12.
Connecting the Memory Controller to SDRAM and Devices.............................. 121
12.1 Connecting to SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.2 Connecting to Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.3 SDRAM Interface Differences between B-0 and B-1 . . . . . . . . . . . . . . . . . . . . . . . . . . 125
GT64120 System Controller For RC4650/4700/5000 and RM526X/527X/7000 CPUs
Revision 1.4
V
13.
Big and Little Endian ............................................................................................. 131
13.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.2 Configuring a System for Big and Little Endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
13.3 PCI Interface Endianess Differences between B-0 and B-1/3/4 . . . . . . . . . . . . . . . . . 133
14.
Using the GT64120 Without the CPU Interface ................................................. 141
15.
Using the GT64120 in Different PCI Configurations ......................................... 151
16.
System Configurations.......................................................................................... 161
16.1 Minimal System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
16.2 Typical System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
16.3 High Performance System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
17.
Registers Tables .................................................................................................... 171
17.1 Access to On-Chip PCI Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . 171
17.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
17.3 CPU Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1710
17.4 CPU Address Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
17.5 CPU Sync Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719
17.6 SDRAM and Device Address Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719
17.7 SDRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1723
17.8 SDRAM Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725
17.9 Device Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1727
17.10 DMA Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729
17.11 DMA Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1732
17.12 DMA Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1736
17.13 Timer / Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
17.14 PCI Internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
17.15 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1750
17.16 PCI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1756
17.17 I2O Support Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767
18.
DC Chracteristics ................................................................................................... 181
18.1 Thermal Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
19.
AC Timing ............................................................................................................... 191
19.1 TClk/PClk Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
19.2 Additional Delay due to Capactive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
20.
Pinout Table, 388 pin BGA ................................................................................... 201
21.
BGA Package Mechanical Information ................................................................ 211
22.
Functional Waveforms........................................................................................... 221
23.
GT64120 Part Numbering .................................................................................... 231
23.1 Standard Part Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
23.2 Valid Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
24.
Revision History..................................................................................................... 241
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