Galileo
GT-96100A
Advanced Communication Controller
Datasheet
Revision 1.0
3 October, 2000
F
EATURES
www.galileoT.com support@galileoT.com
Please contact Galileo Technology for possible
updates before finalizing a design.
Integrated communication controller and
system controller with PCI interface for high-
performance embedded control applications.
Eight Multi-Protocol Serial Controllers
(MPSCs):
- Support HDLC, BISYNC, UART and
Transparent protocols.
- Bit rate of up to 55Mbit/s on multiple
channels simultaneously.
- Can drive dedicated pins or use
TDMs.
- Dedicated DPLL for clock recovery
and data encoding/decoding.
- Supports NRZ, NRZI, FM0, FM1,
Manchester and Differential
Manchester.
- Hardware support for HDLC over
asynchronous channel in UART
mode.
Four FlexTDM channels:
- Time slot assigner for serial and
control channels.
- Supports up to four Basic Rate ISDN
interfaces (2B+D) in GCI mode.
- Fully programmable via dual-port
memory.
Two 10/100Mbps Fast Ethernet MAC
controllers:
- MII/RMII interface.
- Full duplex and flow-control support.
- Programmable perfect filtering of 1/2K
or 8K MAC addresses (both physical
and multicast).
- 2 Queues for Tx Priority queueing
- 4 Queues for Priority queuing based
on IP DSCP field or 802.1q tag or
MAC address.
- IGMP and BPDU packet trapping.
Twenty Serial DMA (SDMA) channels to
support the communications and Ethernet
controllers.
- Moves data between communications
controllers and SDRAM/PCI.
- Buffer chaining via a linked list of
descriptors.
Eight baud rate generators with multiple clock
sources.
64-bit CPU bus interface:
- Supports all 64-bit bus MIPS CPUs:
RM5260, RM5270/1 and RM7000
from QED, RV4600 through RV5000
from IDT and R5000 compatibles from
various vendors.
- 100MHz bus frequency.
- 3.3V bus interface.
- Support for multiple GT-96100A
devices on the same SysAD bus (up
to 4).
- 8x64-bit (64 byte) CPU write posting
buffer accepts CPU writes with zero
wait-states.
- CPU address remapping to resources.
- Zero wait state secondary cache
support (L2 of R4xxx and R5000, L3
of R7000).
- Backward Software Compatibility with
GT-64010A, GT-64011 and GT-64120.
GT-96100A Advanced Communication Controller
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Revision 1.0
SDRAM controller:
- 3.3V (5V tolerant).
- 4GB address space.
- Supports 16/64/128/256/512Mbit
SDRAM devices.
- Supports 64-bit registered SDRAM.
- Supports 2-way & 4-way SDRAM
bank interleaving.
- Up to 4GB bank address space, 1MB
granularity.
- 1 to 4 banks supported.
- 64-bit data width.
- ECC support for 64-bit SDRAM.
- Zero wait-state interleaved burst
accesses at 100MHz.
- Supports the VESA Unified Memory
Architecture (VUMA) Standard -
allows for external masters access to
SDRAM directly.
Device controller:
- 5 chip selects.
- Programmable timing for each chip
select.
- Supports many types of standard
memory and
I/O devices.
- Up to 4GB address space.
- Optional external wait-state support.
- 8-,16-,32- and 64-bit width device
support.
- Support for boot ROMs.
Four Independent DMA (IDMA) channels:
- Chaining via linked-lists of records.
- Byte address boundary for source and
destination.
- Moves data between PCI, memory,
and devices.
- Two 64-byte internal FIFOs.
- Alignment of source and destination
addresses.
- DMAs can be initiated by the CPU
writing to a register, external request
via DMAReq* pin, or an internal timer/
counter.
- Termination of DMA transfer on each
channel.
- Descriptor ownership transfer to CPU.
- Fly-By support for local data bus.
- Override capability of source/
destination/record address mapping.
GT-96100A Advanced Communication Controller
Revision 1.0
3
Two 32-bit or one 64-bit high-performance PCI
2.1 compliant devices:
- Dual mode PCI interface can be used
as two independent 32-bit interfaces
(synchronous or asynchronous to
each other) or as a single 64-bit
interface.
- 192-bytes of posted write and read
prefetch buffers for each PCI
interface.
- 32/64-bit PCI master and target
operations.
- PCI bus speed of up to 66MHz with
zero wait states.
- Universal PCI buffers (each 32-bit PCI
use a different voltage).
- Operates either synchronous or
asynchronous to the CPU clock.
- Burst transfers used for efficient data
movement.
- Doorbell interrupts provided between
CPU and PCI.
- Supports flexible byte swapping
through PCI interface.
- Synchronization barrier support for
PCI side.
- PCI address remapping to resources.
Host to PCI bridge:
- Translates CPU cycles into PCI I/O or
Memory cycles.
- Generates PCI Configuration,
Interrupt Acknowledge, and Special
cycles on PCI bus.
PCI to Main Memory bridge:
- Supports fast back-to-back
transactions.
- Supports memory and I/O
transactions to internal configuration
registers.
- Supports locked operations.
I
2
O
and Plug and Play Support:
- Industry Standard I
2
O messaging unit
on primary 32-bit PCI interface (also
available in 64-bit mode).
- Plug and Play compatible
configuration registers.
- PCI configuration header can be
loaded from boot PROM.
- PCI configuration registers are
accessible from both CPU and PCI
bus.
- Expansion ROM support.
PCI Hot-Plug and CompactPCI Hot-Swap
capable compliant.
Two programmable PCI Arbiter functions:
- Supports up to 9 external agents in
addition to PCI_0 and PCI_1 internal
devices.
- Two level priority arbitration capability
- each request can be assigned either
high or low priority.
Two-stage watchdog timer (NMI, Reset).
One 32-bit wide timer/counter, Three 24-bit
wide timer/counters.
Eighty-eight pins dedicated for peripheral
functions and general purpose I/Os.
- Each pin can be configured
independently as peripheral or
General Purpose I/O.
- Supports simple I/O and LED control.
- Inputs can generate a maskable
interrupt.
2.5V Core Supply Voltage, 3.3V I/O Supply
Voltage (PCI and Peripherals).
- All inputs are 5V tolerant.
JTAG Boundary Scan.
492 pin PBGA package.
Advanced 0.25 micron CMOS process.
GT-96100A Advanced Communication Controller
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Revision 1.0
Part Number: GT-96100A
Publication Revision: 1.0
Galileo Technology, Inc.
No part of this datasheet may be reproduced or transmitted in any form or by any means,
electronic or mechanical, including photocopying and recording, for any purpose without
the express written permission of Galileo Technology, Inc.
Galileo Technology, Inc. retains the right to make changes to these specifications at any
time, without notice.
Galileo Technology, Inc. makes no warranty of any kind, expressed or implied, with
regard to this material, including, but not limited to, the implied warranties of merchant-
ability or fitness for any particular purpose. Galileo Technology, Inc. further does not war-
rant the accuracy or completeness of the information, text, graphics, or other items
contained within these materials. Galileo Technology, Inc. makes no commitment to
update nor to keep current the information contained in this document.
Galileo Technology, Inc. assumes no responsibility for the use of any circuitry other than
circuitry embodied in Galileo Technology, Inc. products. No other circuit patent licenses
are implied.
Galileo Technology, Inc. products are not designed for use in life support equipment or
applications in which if the product failed it would cause a life threatening situation. Do
not use Galileo Technology, Inc. products in these types of equipment or applications.
Contact your local sales office to obtain the latest specifications before finalizing your
product.
Galileo Technology, Inc.
142 Charcot Avenue
San Jose, California 95131
Phone: 1 408 367-1400
Fax: 1 (408) 367-1401
E-mail: info@galileot.com
www.galileoT.com
Other brands and names are the property of their respective owners.
GT-96100A Advanced Communication Controller
Revision 1.0
5
T
ABLE
OF
C
ONTENTS
1.
Overview ..................................................................................................................... 19
1.1
Communication Unit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.2
CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3
SDRAM and Device Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.4
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5
Independent DMA (IDMA) Engines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.6
Peripheral Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.
Pin Information........................................................................................................... 25
3.
Address Space Decoding.......................................................................................... 56
3.1
Two Stage Decoding Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.2
Disabling Address Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.3
DMA Unit Address Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.4
Address Space Decoding Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.5
Default Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.6
Address Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.7
Using the CPU PCI Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.8
Using the DMA to PCI Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.
CPU Interface Description......................................................................................... 72
4.1
CPU Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.2
SysAD, SysADC, and SysCmd Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.3
Operation of WrRdy* and the Internal Write Posting Queues . . . . . . . . . . . . . . . . . . . . . 79
4.4
CPU Write Modes and Write Patterns Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.5
CPU Interface Endianess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.6
Burst Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.7
MIPS L2 Cache Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.8
Multiple GT-96100A Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.9
CPU Interface Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.10 CPU Interface Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5.
Memory Controller ..................................................................................................... 95
5.1
SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.2
Connecting the Address Bus to the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.3
Programmable SDRAM Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.4
SDRAM Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.5
SDRAM Bank Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.6
Unified Memory Architecture (UMA) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.7
Device Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.8
Programming the ADP lines for other Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.9
Memory Controller Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.10 Registered SDRAM Interface Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.11 Memory Interface Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.
Data Integrity ............................................................................................................ 143
6.1
SDRAM ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.2
PCI Parity Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
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