DA7838.002
20 September, 2000
1 (9)
0$6
6<1&+521286 72 $6<1&+521286
&219(57(5 6$& &026
,QWHUIDFHV D GXSOH[ DV\QFKURQRXV FKDQQHO
WR D V\QFKURQRXV FKDQQHO
0RGHP V\VWHPV DW VSHHGV RI N
N N N DQG N
&KDUDFWHU OHQJWK IURP WR ELWV
LQFOXGLQJ VWDUW VWRS DQG SDULW\ ELWV
'(6&5,37,21
The MAS7838 is a single chip duplex synchronous to
asynchronous converter. It converts asynchronous start
stop characters to synchronous character format, with
stop bit deletion when required as defined in the CCITT
recommendation V.14 (V.22). On the receiver channel
the MAS7838 converts the incoming synchronous data
to asynchronous start stop character format with stop bit
insertion when required as defined in the CCITT
recommendation V.14 (V.22).The MAS7838 implements
the data modes for the synchronous interface as
specified in the V.14 (V.22). The device can be
configured to operate at any frequency to maximum
device speed within the above mentioned modes.
)($785(6
$33/,&$7,21
Implements CCITT recommendations V.14 and
V.22 chapters 4.1, 4.2 and 4.3
Operates in modes as defined in the CCITT
recommendations V.22 (i), ii), iii), iv) and v)
Transmission rate up to 64 kbit/s
CMOS compatible interface
Low power consumption (typically 25 mW)
No additional circuitry required to perform the
conversion
CMOS
device
Single =5V supply
Adapts asynchronous terminals to synchronous
modems
Full or half card PC modems using UART as a
data source
Simplifying data multiplexing in a MUX/DEMUX
system
%/2&. ',$*5$0
CL1
CL2
XESR
TMG
OSC
TSL
TXC
TDO
RXC
RDI
XASY
XHST
VSS
VDD
TDI
RDO
CONTROL
O
S
C
ASYNC
TO
SYNC
SYNC
TO
ASYNC
>
1
_
DA7838.002
20 September, 2000
2 (9)
3,1 &21),*85$7,21
Top marking: YYWW = Year Week, XXXXX.X = Lot Number, =ESD Indicator
3,1 '(6&5,37,21
3LQ QDPH
3LQ QR
,2
)XQFWLRQ
TSL
1
I
Timing select. 0 selects asynchronous sampling timing 16 x TXC from pin 2, TMG.
1 selects asynchronous sampling timing 256...8192 x TXC from pin 2, TMG.
TMG
2
I
Timing. Square wave timing signal 16 x TXC (TSL=0) or 256...8192 x TXC (TSL=1).
Max f=10 MHz.
OSC
3
O
Oscillator. Output for crystal. If used, the crystal is connected between pins 2 and 3.
TXC
4
I
Transmitter timing. Synchronous square wave timing for transmitter. The transmitted
data output, TDO is synchronized to the rising edge of TXC. The duty cycle of TXC
has to be 50% +/- 5%.
CL1
5
I
CL2
6
I
Character length. The total character length including one start bit, one stop bit and
possible parity bit is selected with the CL1 and CL2 signals.
XESR
7
I
Extended signalling rate. The tolerance of the synchronous bit rate can be:
XESR = 1 (basic signalling rate) TXC -2.5%...+1.0%
XESR = 0 (extended signalling rate) TXC -2.5%...2.3%
VSS
8
G
Ground
TDI
9
I
Transmitter data input. 1 = mark or stop bit, 0 = space, start or break signal
TDO
10
O
Transmitter data output. The output data is synchronized to the synchronous timing
signal TXC (pin 4). 1 = mark, 0 = space
XASY
11
I
Asynchronous mode. XASY=0 Asynchronous transmission. XASY=1 Synchronous
transmission. In synchronous transmission the converter is totally bypassed in both
directions: TDI=TDO, RDI=RDO
XHST
12
I
Higher speed signalling timing. XHST = 1 normal synchronous to asynchronous
conversion (Bell 212; CCITT V.22). XHST = 0 asynchronous to synchronous
conversion with higher speed synchronous timing (TXC, RXC). TXC and RXC timing
must be 1-2% higher than the normal bit rate in order to allow some overspeed in the
asynchronous data. On the receiver side the RX buffer is deleted and the
synchronous data RDI is directly connected to the asynchronous output RDO.
RDO
13
O
Receiver data output. RDO is the received data converted back to asynchronous
mode.
1 = mark or stop bit, 0 = space, start or break signal
RDI
14
I
Receiver data input. 1 = mark, 0 = space. The received data must be synchronized to
the receiver timing RXC from the synchronous channel (pin 15).
RXC
15
I
Receiver timing. Receiver square wave timing from the synchronous channel. The
received data RDI must be synchronized to the rising edge of RXC.
VDD
16
P
Power supply
PDIP 16
TSL
TMG
OSC
TXC
CL1
CL2
XESR
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 VDD
RXC
RDI
RDO
XHST
XASY
TDO
TDI
TSL
TMG
OSC
TXC
CL1
CL2
XESR
VSS
1
2
3
4
5
6
7
8
SO16
9
10
11
12
13
14
15
16 VDD
RXC
RDI
RDO
XHST
XASY
TDO
TDI
MAS7838N
MAS7838S
&
'"
'
Y
Y
Y
Y
Y
Y
`
`
X
X
&
'"
'
Y
Y
Y
Y
Y
Y
`
`
X
X
DA7838.002
20 September, 2000
3 (9)
$%62/87( 0$;,080 5$7,1*6
(GND = 0V)
3DUDPHWHU
6\PERO
&RQGLWLRQV
0LQ
0D[
8QLW
Supply Voltage
VDD
-0.5
5.5
V
Storage Temperature
Ts
-55
+150
o
C
5(&200('(' 23(5$7,21 &21',7,216
3DUDPHWHU
6\PERO
&RQGLWLRQV
0LQ
7\S
0D[
8QLW
Supply Voltage
VDD
4.75
5
5.25
V
Supply Current
IDD
4
6
mA
Operating Temperature
Ta
0
+70
o
C
(/(&75,&$/ &+$5$&7(5,67,&6
u ,QSXWV
(test conditions: VDD = +5V, VSS = 0V, 0
O
C to 70
O
C)
3DUDPHWHU
6\PERO
&RQGLWLRQV
0LQ
7\S
0D[
8QLW
Input high voltage
V
IH
3.5
V
Input low voltage
V
IL
1.1
V
Input leakage current
I
IL
-100
pA
Input capacitance load
C
I
5
pF
Internal pull-up resistor for
digital inputs
R
pull-up
VIN = 0.4v
VIN = 2.5v
350
850
k
u
2XWSXWV
(test conditions: VDD = +5V, VSS = 0V, 0
O
C to 70
O
C)
3DUDPHWHU
6\PERO
&RQGLWLRQV
0LQ
7\S
0D[
8QLW
Output low voltage
V
OL
IOL = -0.6mA
0.4
V
Output high voltage
V
OH
IOH = 0.4mA
4.6
V
u
'DWD 7LPLQJ
(test conditions: VDD = +5V, VSS = 0V, 0
O
C to 70
O
C)
3DUDPHWHU
6\PERO
&RQGLWLRQV
0LQ
7\S
0D[
8QLW
Low to high logic transition time
tR
CL = 10pF
20
ns
High to low logic transition time
tF
CL = 10pF
20
ns
(test conditions: TSL = 1)
3DUDPHWHU
6\PERO
&RQGLWLRQV
0LQ
7\S
0D[
8QLW
TDO delay time after TXC
T1
50
T
TXC
/16+350
ns
RDI set up time before RXC
T2
1/4 T
RXC
ns
RDI hold time after RXC
T3
1/4 T
RXC
ns
(test conditions: TSL = 0, TMG = 16xTXC)
3DUDPHWHU
6\PERO
&RQGLWLRQV
0LQ
7\S
0D[
8QLW
TDO delay time after TXC
T1
50
1/TMG+350
ns
RDI set up time before RXC
T2
1/4 T
RXC
ns
RDI hold time after RXC
T3
1/4 T
RXC
ns
DA7838.002
20 September, 2000
4 (9)
(/(&75,&$/ &+$5$&7(5,67,&6
Timings between synchronous clocks and data are shown below. Note that absolute delays depend on the speed of
the data transmission.
If pin TSL = 1 (Automatic synchronous sampling timing)
)81&7,216
u $V\QFKURQRXV WR V\QFKURQRXV FRQYHUWHU
The synchronous start-stop character, TDI (transmitter
data input), is read into the Tx buffer. When the
character is available the data bits are transferred as
TDO (transmitter data output) with the synchronous
timing signal TXC (transmitter clock). The bit rate of TDI
must be the same as the TDO rate within -2.5%...+1%
or -2.5%...+2.3% tolerance depending on XESR
(extended signalling rate) signal. The transmitter adds
extra stop bits to the synchronous data stream, if TDI is
slower than TDO. The over speed is handled by
deleting one stop bit in every 8th character at maximum
in the synchronous output data TDO. When extended
signal rate (XESR = 0) is used 4th stop bit may be
deleted. When the transmitter detects a break signal( at
least M bits of start polarity, where M is length of
character), it sends 2M + 3 bits of start - polarity to
TDO. If the break is longer than 2M + 3 bits, then all bits
are transferred to TDO. After a break signal, at least 2M
bits of stop polarity must be transmitted before sending
further data.
u 6\QFKURQRXV WR DV\QFKURQRXV FRQYHUWHU
The synchronous RDI (receiver data input) is buffered
to recognise the stop and start bits. If a missing stop bit
is detected, it is added to the RDO (receiver data
output). In this case the stop bits are shortened 12.5%
(25% if XESR = 0) during each character. When the
receiver gets at least 2M + 3 bits of start polarity, it does
not add stop bits to RDO. This enables the break signal
to go through the buffer.
u
&RQYHUWLQJ ZLWK KLJKHU VSHHG WLPLQJ
An alternative method to handle the over speed in
asynchronous data is to boost synchronous timing TXC
and RXC by 1-2%. In this mode XHST (higher speed
timing) = 0. In this case there is no need to delete any
stop bits in the transmitter buffer. The break signal goes
through unchanged. On the receiver side the
synchronous data, RDI, is transferred directly to the
asynchronous output RDO with RXC.
T
RXC
T2
T3
RXC
RDI
TXC
TDO
T
TXC
delay
T1
DA7838.002
20 September, 2000
5 (9)
)81&7,216
u 7LPLQJ VHOHFWLRQ
The MAS7838 requires clock signals in order to function
properly. The synchronous data transfer always
requires the TXC clock. The clock is used internally for:
-shifting data out from the TX buffer (to pin TDO)
-shifting data into the RX buffer (via pin RDI)
-detection of the bit rate in order to adjust the internal
baud rate generator (only if TSL = 1)
The asynchronous data transfer (pins TDI, TDO) is
accomplished by generating an internal timing signal for
the asychronous circuits. This internal timing signal
(16T) is 16 times the TXC bit rate in order to sample the
asynchronous data stream (TDI) at the proper speed.
$33/,&$7,21 ,1)250$7,21
u 6\QFKURQRXV PRGHP ZLWK DV\QFKURQRXV LQWHUIDFH
The MAS7838 is intended for applications where an
asynchronous and synchronous data source must be
linked together. A typical case appears in a data
modem
where the terminal interface of the modem has been
specified to be asynchronous but the modem data
pump operates in a synchronous fashion.
16 x TXC
TXC
Timing Circuits
MAS 7838
EXTERNALLY GENERATED 16T CLOCK
MAS9138
TXD
RXD
TDI
RDO
INTERFACE
RS232C
MODEM CIRCUITS
PHONE LINE
TDO
TXC
RDI
RXC
PDF 
ZIP