DA9181.006
13 October, 1999
1
! #"%$&('
#()('
010324)5'
687@9
ACBEDCFE9
G8HPI
QPD
QSRUTWVUG
68X
Y
`Ua
bEcCdSd8e
fPgihqp
h8rPh8s
gihPp
t8u@vCe
w
f8xEhqvEcCw
yCcEw
CiCE
iP
W
The MAS9181 comprises eight digital to analog
converters (DACs) each controlled by a two-wire I
2
C
bus. The DACs are individually programmed using an 8-
bit word to select an output from one of 256 voltage
steps. The maximum output voltage of all DACs is set
by Vmax and the resolution is Vmax/256. At power-on all
outputs are set to their lowest value. The I
2
C-bus slave
receiver has 3 programmable address pins (2 for
MAS9181 CS).
iCPEEi
dPeif
gdCPf
hWi
Rail to rail output stages
Octal 8-bit DACs on a single monolithic chip
Power supply range from +5 V to +12 V
-20
C to +85
C temperature range
16-pin PDIL and SO package
Power-up reset
Trimmer replacement
AGC/AFT or TVs and VCRs
Graphic equalizers
High resolution monitors
jEkml@nopCq
rsWtPru
Reference
Voltage
Generator
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
8-BIT DAC
DAC7
8-BIT DAC
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
VDD
A0
SDA
SCL
A1
A2
vxwmy
z
GND
I C Bus
Slave
Receiver
{
DA9181.006
13 October, 1999
2
|P}
~SEW~Ei}
WEPCP}
W~
|P}
~C8dE}
|88}
W~
E
x
VDD
1
1
P
Positive supply voltage
Vmax
2
2
I
Control input for DAC maximum output voltage
SDA
3
3
I/O
I
2
C bus serial data input/output
SCL
4
4
I
I
2
C bus serial data clock
A
0
5
6
I
Programmable address bits for I
2
C bus slave receiver
A
1
6
7
I
Programmable address bits for I
2
C bus slave receiver
A
2
7
NC
I
Programmable address bits for I
2
C bus slave receiver
GND
8
8
G
Ground
DAC0
9
9
O
Analog voltage output
DAC1
10
10
O
Analog voltage output
DAC2
11
11
O
Analog voltage output
DAC3
12
12
O
Analog voltage output
DAC4
13
13
O
Analog voltage output
DAC5
14
14
O
Analog voltage output
DAC6
15
15
O
Analog voltage output
DAC7
16
16
O
Analog voltage output
*1 MAS9181BN (PDIP16)
*2 MAS9181CS (SO16)
PDIP 16
VDD
Vmax
SDA
SCL
A0
A1
A2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
1
2
3
4
5
6
7
8
SO16
9
10
11
12
13
14
15
16 DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
VDD
Vmax
SDA
SCL
NC
A0
A1
GND
MAS9181BN
MAS9181CS
DA9181.006
13 October, 1999
3
dCWdP@d
%EPCP
C
(conditions)
E
x
x
C
ü
Supply Voltage
VDD
-0.5
18
V
Supply current
IDD
-10
40
P
I
2
C-bus line voltage
V(3),V(4)
-0.5
5.9
V
Input voltage
Vin
-0.5
VDD+0.5
V
Output voltage
Vo
-0.5
VDD+0.5
Maximum current on any
pin
Imax
10
mA
total power dissipation
Ptot
500
mW
Operating ambient
temperature range
Tamb
-20
+85
o
C
Storage temperature range
Tstg
-65
+150
o
C
E8EWU%CCdqWdPPE8
WSEWC
P
Wd
xx
m
o
C
Pm
P
x
!
"#!$%&
&
$
'
()&
$10!23(4
576#$&
Supply Voltage
VDD
4.5
12
13.2
V
Supply current
IDD
No loads, Vmax=VDD=12V, All
data=00
OCT
3.0
5.0
mA
Total power dissipation
Ptot
No loads, Vmax=VDD=12V, All
data=00
OCT
40
60
mW
8@9A8CB4D@EF
BHG)9IB)P@G)E@G)B4DC8HEF
Q@D@F
B4Q
RTS
U!VW
X
Y
`bacAd
`feAg)h
UV!W
Xfi
V
h
U
Y4p
d
qr
(All voltages are with respect to GND; Tamb = -20
o
C to 85
o
C; VDD = 5V to 12V unless otherwise specified)
stu
tvw
x
wu
y!v
#
f
x
!
)
Ht
#
x
Input voltage range
V
I
-0.5
5.5
V
Input low voltage
V
IL
1.0
V
Input high voltage
V
IH
3.0
V
Input leakage current
I
IL
Vin = 0V or VDD
-1
+1
A
Power-up reset
3.5
V
DA9181.006
13 October, 1999
4
@AC4d@ef
Hg)I)h@g)e@g)4dCHef
i@d@f
4i
jbk!kl
m
n
n)o
p!qr
st
q!u
pnHvw
xw
yz
(All voltages are with respect to GND; Tamb = -20
o
C to 85
o
C; VDD = 5V to 12V unless otherwise specified)
{|}
|~
}
~!
#!
)
H|
#
Input voltage range
V
I
0
VDD
V
Input low voltage
V
IL
1.0
V
Input high voltage
V
IH
3.0
V
Input current low
I
IL
-10
-15
A
Input current high
I
IH
1
A
b
)#!
!
!
!
!f #
!
!
!
4
!
(All voltages are with respect to GND; Tamb = -20
o
C to 85
o
C; VDD = 5V to 12V unless otherwise specified)
!
#!
)
H
#
Pin 2 current
I
2
7
10
A
H
!
(All voltages are with respect to GND; Tamb = -20
o
C to 85
o
C; VDD = 5V to 12V unless otherwise specified)
ǧȧ
˧
ϧ!
#!
)
اΧH
#ӧ
Io = +/- 100 A
0.1
VDD-0.1
V
DAC output (pin 9 to 16)
Output voltage range
Vo
Io = +/- 500 A
0.2
VDD-0.2
V
Output impedance
Zo
data = 7F
30
DAC output drive range
Io
Upper side saturation voltage= 0.2v
Low side saturation voltage = 0.2v
-1
1
mA
Output capacitive load
Co
2
nF
bޢH
!
f
4
(All voltages are with respect to GND; Tamb = -20
o
C to 85
o
C; VDD = 5V to 12V unless otherwise specified)
!
#
f
!
)
4
#!
Output voltage low
V
OL
I
3
= 3.0 mA
0.4
V
(All voltages are with respect to GND; Tamb = -20
o
C to 85
o
C; VDD = 5V to 12V unless otherwise specified)
! "$#
%&"$'
(0)
)
"'1
2)
'435627
869&')
Differential nonlinearity
DNL
Io = 0 (without load)
Vmax = VDD-1.0
-1
1
LSB
Integral nonlinearity
INL
Io = 0 (without load)
Vmax = VDD-1.0
-1.5
1.5
LSB
Zero code error
1
ZCE
data = 00
10
30
mV
Power supply rejection
1
PSRR
5
mV/V
Zero code temperature coefficient
1
TCo
-200
200
V/
o
C
Note 1: Guaranteed by design but not production tested
DA9181.006
13 October, 1999
5
@&AB7C7DFE
GHBPI
QSR
T
UWVXY
`
The MAS9181 I
2
C-bus interface is a receiver- only slave. Data is accepted from the I
2
C - bus in the following
format.
S
0 1 0 0 A2 A1 A0 0
A
I3 I2 I1 I0 SD SC SB
SA
A
D7 D6 D5 D4 D3 D2 D1
D0
A
P
Address byte
Instruction byte
First data byte
S
Start condition
A2, A1, A0
programmable address bits
P
Stop condition
I3, I2, I1, I0
instruction bits
A
Acknowledgement
SD, SC, SB, SA
sub-address bits
D7, D6, D5, D4, D3, D2, D2, D1, D0
data bits
aSb
c
dWefg
hPi
p
q!p
rs
SDA
SCL
Bit Transfer on the I C-bus
t
Data line
stable
(data valid)
Change
of data
allowed
S
P
1-7
8
9
1-7
8
9
1-7
8
9
Start
condition
Stop
condition
SDA
SCL
Address
Data
Data
R/W
Ack
Ack
Ack
Complete Data Transfer
PDF 
ZIP