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REV: 032503
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.
GENERAL DESCRIPTION
On the transmit side, the DS26101 receives ATM cells
from an ATM device through a UTOPIA II interface,
provides cell buffering (up to 4 cells), HEC generation
and insertion, cell scrambling, and converts the data
to a serial stream appropriate for interfacing to a
T1/E1 framer or transceiver. On the receive side, the
DS26101 receives a TDM stream from a T1/E1 framer
or transceiver; searches for the cell alignment; verifies
the HEC; provides cell filtering, descrambling, and cell
buffering; and passes the cells to an ATM device
through the UTOPIA II interface. Other low-level traffic
management functions are selectable for the transmit
and receive paths. The DS26101 can also be used in
fractional T1/E1 applications.
The DS26101 maps ATM cells to T1/E1 TDM frames
as specified in ATM Forum Specifications af-phy-
0016.000 and af-phy-0064.000. In the receive
direction, the cell delineation mechanism used for
finding ATM cell boundary within T1/E1 frame is
performed as per ITU I.432. The DS26101 provides a
mapping solution for up to 8 T1/E1 TDM ports. The
terms physical layer (PHY) and line side are used
synonymously in this document and refer to the
device interfacing with the line side of the DS26101.
The terms ATM layer and system side are used
synonymously and refer to the DS26101's UTOPIA II
interface.
FUNCTIONAL DIAGRAM
FEATURES
Supports 8 T1/E1 TDM Ports
Supports Fractional T1/E1
Compliant to ATM Forum Specifications for ATM
Over T1 and E1
Standard UTOPIA II Interface to the ATM Layer
Configurable UTOPIA Address Range
Configurable Tx FIFO Depth to 2, 3, or 4 Cells
Optional Payload Scrambling in Transmit
Direction and Descrambling in Receive Direction
per ITU I.432
Optional HEC Insertion in Transmit Direction with
Programmable COSET Polynomial Addition
HEC-Based Cell Delineation
Single-Bit HEC Error Correction in the Receive
Direction
Receive HEC-Errored Cell Filtering
Receive Idle/Unassigned Cell Filtering
User-Definable Cell Filtering
8-Bit Mux/Nonmux, Motorola/Intel Microprocessor
Interface
Internal Clock Generator Eliminates External
High-Speed Clocks
Internal One-Second Timer
Detects/Reports Up to Eight External Status
Signals with Interrupt Support
IEEE 1149.1 JTAG Boundary Scan Support
17mm x 17mm, 256-pin CSBGA
APPLICATIONS
DSLAMS
ATM Over T1/E1
Routers
IMA
ORDERING INFORMATION
PART TEMP
RANGE
PIN-PACKAGE
DS26101
-40C to +85C
256 CSBGA
www.maxim-ic.com
DS26101
8-Port TDM-to-ATM PHY
UTOPIA II
8 TDM
PORTS
Dallas
Semiconductor
DS26101
DS26101 8-Port TDM-to-ATM PHY
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TABLE OF CONTENTS
1. FEATURES .......................................................................................................................... 5
2. LIST OF APPLICABLE STANDARDS................................................................................. 5
3. ACRONYMS AND DEFINITIONS......................................................................................... 6
4. BLOCK DIAGRAM ............................................................................................................... 7
5. PIN DESCRIPTION .............................................................................................................. 8
6. SIGNAL DEFINITIONS....................................................................................................... 11
6.1
L
INE
-S
IDE
S
IGNALS
...................................................................................................................11
6.2
UTOPIA-S
IDE
S
IGNALS
............................................................................................................12
6.3
M
ICROPROCESSOR AND
S
YSTEM
I
NTERFACE
S
IGNALS
................................................................13
6.4
T
EST AND
JTAG S
IGNALS
.........................................................................................................16
7. TRANSMIT OPERATION ................................................................................................... 16
7.1
UTOPIA-S
IDE
T
RANSMIT
--M
UXED
M
ODE WITH
1 TXCLAV ........................................................16
7.2
UTOPIA-S
IDE
T
RANSMIT
--D
IRECT
S
TATUS
M
ODE
(MULTITXCLAV) .........................................18
7.3
T
RANSMIT
P
ROCESSING
............................................................................................................19
7.4
P
HYSICAL
-S
IDE
T
RANSMIT
.........................................................................................................20
8. RECEIVE OPERATION...................................................................................................... 23
8.1
P
HYSICAL
-S
IDE
R
ECEIVE
...........................................................................................................23
8.2
R
ECEIVE
P
ROCESSING
..............................................................................................................25
8.3
UTOPIA-S
IDE
R
ECEIVE
--M
UXED
M
ODE WITH
1 RXCLAV..........................................................26
8.4
UTOPIA-S
IDE
R
ECEIVE
--D
IRECT
S
TATUS
M
ODE
(MULTIRXCLAV) ...........................................27
9. REGISTER MAPPING........................................................................................................ 29
10. REGISTER DEFINITIONS.................................................................................................. 30
10.1
T
RANSMIT
R
EGISTERS
..............................................................................................................30
10.2
S
TATUS
R
EGISTERS
..................................................................................................................34
10.3
R
ECEIVE
R
EGISTERS
................................................................................................................35
10.3.1
Additional Receive Control Information
37
10.3.2
User-Programmable Cell Filtering
41
11. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT....................... 44
11.1
I
NSTRUCTION
R
EGISTER
............................................................................................................46
11.2
T
EST
R
EGISTERS
......................................................................................................................48
12. OPERATING PARAMETERS............................................................................................. 51
13. CRITICAL TIMING INFORMATION ................................................................................... 52
14. THERMAL INFORMATION ................................................................................................ 58
15. APPLICATIONS INFORMATION ....................................................................................... 59
15.1
A
PPLICATION IN
ATM U
SER
-N
ETWORK
I
NTERFACES
...................................................................59
15.2
I
NTERFACING WITH
F
RAMERS
....................................................................................................59
15.3
F
RACTIONAL
T1/E1 S
UPPORT
...................................................................................................60
16. PACKAGE INFORMATION................................................................................................ 61
17. REVISION HISTORY.......................................................................................................... 62
DS26101 8-Port TDM-to-ATM PHY
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TABLE OF FIGURES
Figure 4-1. Block Diagram ...........................................................................................................7
Figure 7-1. Polling Phase and Selection Phase at Transmit Interface .......................................17
Figure 7-2. End and Restart of Cell at Transmit Interface ..........................................................18
Figure 7-3. Transmission to PHY Paused for Three Cycles.......................................................18
Figure 7-4. Example of Direct Status Indication, Transmit Direction ..........................................19
Figure 7-5. Transmit Cell Flow and Processing .........................................................................20
Figure 7-6. Transmit Framer Interface in TFP Mode for T1........................................................21
Figure 7-7. Transmit Framer Interface in Gapped-Clock Mode for T1 .......................................21
Figure 7-8. Transmit Framer Interface in TFP Mode for E1 .......................................................22
Figure 7-9. Transmit Framer Interface in Gapped-Clock Mode for E1 .......................................22
Figure 8-1. Receive Framer Interface in RFP Mode for T1 ........................................................23
Figure 8-2. Receive Framer Interface in Gapped-Clock Mode for T1 ........................................24
Figure 8-3. Receive Framer Interface in RFP Mode for E1 ........................................................24
Figure 8-4. Receive Framer Interface in Gapped-Clock Mode for E1 ........................................24
Figure 8-5. Cell Delineation State Diagram................................................................................25
Figure 8-6. Header Correction State Machine............................................................................26
Figure 8-7. Polling Phase and Selection at Receive Interface ...................................................27
Figure 8-8. End and Restart of Cell Transmission at Receive Interface.....................................27
Figure 8-9. Example Direct Status Indication, Receive Direction ...............................................28
Figure 10-1. Accessing Tx PMON Counter ................................................................................33
Figure 10-2. Accessing Rx PMON Counters..............................................................................39
Figure 11-1. JTAG Functional Block Diagram............................................................................44
Figure 11-2. TAP Controller State Diagram ...............................................................................46
Figure 13-1. Intel Bus Read Timing (BTS = 0/MUX = 1) ............................................................52
Figure 13-2. Intel Bus Write Timing (BTS = 0/MUX = 1) ............................................................53
Figure 13-3.Motorola Bus Timing (BTS = 1/MUX = 1) ...............................................................53
Figure 13-4. Intel Bus Read Timing (BTS = 0/MUX = 0) ............................................................54
Figure 13-5. Intel Bus Write Timing (BTS = 0/MUX = 0) ............................................................55
Figure 13-6. Motorola Bus Read Timing (BTS = 1/MUX = 0) .....................................................55
Figure 13-7. Motorola Bus Write Timing (BTS = 1/MUX = 0) .....................................................55
Figure 13-8. Setup/Hold Time Definition ....................................................................................57
Figure 13-9. Delay Time Definition.............................................................................................57
Figure 13-10. JTAG Interface Timing Diagram ..........................................................................57
Figure 15-1. User-Network Interface Application .......................................................................59
Figure 15-2. DS26101 Interfacing with Dallas Framer in Framing-Pulse Mode .........................60
DS26101 8-Port TDM-to-ATM PHY
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LIST OF TABLES
Table 5-A. Pin Description List.....................................................................................................8
Table 9-A. Register Map ............................................................................................................29
Table 11-A. Instruction Codes for IEEE 1149.1 Architecture .....................................................47
Table 11-B. ID Code Structure...................................................................................................47
Table 11-C. Device ID Codes ....................................................................................................47
Table 11-D. Boundary Scan Control Bits ...................................................................................48
Table 13-A. AC Characteristics--Multiplexed Parallel Port (MUX = 1) ......................................52
Table 13-B. AC Characteristics--Nonmultiplexed Parallel Port (MUX = 1)................................54
Table 13-C. Framer Interface AC Characteristics ......................................................................56
Table 13-D. UTOPIA Transmit AC Characteristics ....................................................................56
Table 13-E. UTOPIA Receive AC Characteristics......................................................................56
Table 13-F. JTAG Interface Timing............................................................................................57
Table 13-G. System Clock AC Characteristics...........................................................................58
Table 14-A. Thermal Properties, Natural Convection.................................................................58
Table 14-B. Theta-JA (
q
JA
) vs. Airflow........................................................................................58
Table 15-A. Suggested Clock Edge Configurations ...................................................................60
Table 15-B. Fractional T1/E1 Register Settings .........................................................................60
DS26101 8-Port TDM-to-ATM PHY
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1. FEATURES
Supports 8 T1/E1 Ports
Supports Fractional T1/E1 and Arbitrary Bit
Rates in Multiples of 64kbps (DS0/TS) Up to
2.048Mbps
Supports Clear E1
Compliant to the ATM Forum Specifications for
ATM Over T1 and E1
Standard UTOPIA II Interface to the ATM Layer
Configurable UTOPIA Address Range
Generic 8-Bit Asynchronous Microprocessor
Interface for Configuration and Status Indications
Including Interrupt Capability
Physical-Layer Interface can Accept T1/E1 TDM
Stream in the Form of Either (1) Clock, Data, and
Frame-Overhead Indication or (2) Gapped Clock
(Gapped at Overhead Positions in the Frame)
and Data
Selectable Active Clock Edge for Interface with
the T1/E1 Framer
Supports Diagnostic Loopback
Optional Payload Scrambling in Transmit
Direction and Descrambling in Receive Direction
as per the ITU I.432 for the Cell-Based Physical
Layer
Optional HEC Insertion in Transmit Direction with
Programmable COSET Polynomial Addition
Option of Using Either Idle or Unassigned Cells
for Cell-Rate Decoupling in Transmit Direction
1-Byte Programmable Pattern for Payload of
Cells Used for Cell-Rate Decoupling
Tx FIFO Depth Configurable to either 2, 3, or 4
Cells
Transmit FIFO Depth Indication for 2-Cell Space
Through External Pins
Optional Single-Bit HEC-Error Insertion
HEC-Based Cell Delineation as per I.432
Optional Single-Bit HEC Error Correction in the
Receive Direction
Optional Filtering of HEC-Errored Cells Received
Optional Receive Idle/Unassigned Cell Filtering
Optional User-Defined Cell Filtering Based on
Programmable Header Bits
Programmable Loss-of-Cell Delineation (LCD)
Integration and Interrupt
Interrupt for FIFO Overrun in Receive Direction
Saturating Counts for (1) Number of Error-Free
Assigned Cells Received and Transmitted and
(2) Number of Correctable and Uncorrectable
HEC-Errored Cells Received
Selectable Internally Generated Clock (System
Clock Divided by 8) in Diagnostic Loopback
Mode
Integrated PLL Generates High-Frequency
Clocks
IEEE 1149.1 JTAG Boundary Scan Support
2. LIST OF APPLICABLE STANDARDS
[1] ATM Forum "DS1 Physical Layer Specification," af-phy-0016.000, September 1994
[2] ATM Forum "E1 Physical Layer Specification," af-phy-0064.000, September 1996
[3] ATM Forum "UTOPIA Level 2 Specification," Version 1.0, af-phy-0039.000, June 1995
[4] B-ISDN User-Network Interface--Physical Layer Specification--ITU-T Recommendation I.432--3/93
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