1 of 10
102902
FEATURES
2Mbits organized as a 64K x 40 memory
6 years minimum data retention in the
absence of external power
Nonvolatile circuitry transparent to and
independent of host system
Automatic write protection circuitry
safeguards against data loss
Battery monitor checks remaining capacity
daily
Fast access time of 70ns
Operating V
CC
range of 3.0V to 3.6V
Employs popular JEDEC standard 72-
position SIMM connector
Operating temperature: 0
o
C to +70
o
C
PIN DESCRIPTION
A0 - A15
-
Address Inputs
DQ0 DQ39 -
Data Inputs/Outputs
CEA\
-
Chip Enable Inputs
WE\
-
Write Enable Inputs
OE\
-
Output Enable Inputs
VCC
-
3.3V Power Supply
GND
- Ground
PIN ASSIGNMENT
DS38464 72-PIN SIMM
DS38464
3.3V 64K x 40 NV SRAM SIMM
www.maxim-ic.com
DS38464
2 of 10
DESCRIPTION
The DS38464 is a self-contained 2,621,440-bit, nonvolatile static RAM, which is organized as a 64K x
40 memory. Built using three 64K x 16 SRAMs, one nonvolatile control IC, and one lithium battery,
this nonvolatile memory contains all the necessary control circuitry and lithium energy source to
maintain data integrity in the absence of power for more than 6 years. The DS38464 employs the
popular JEDEC standard 72-position SIMM connection scheme and requires no additional circuitry.
READ MODE
The DS38464 executes a read cycle whenever WE\ is inactive (high) and CE\ and OE\ are active (low).
The unique address specified by the 16 address inputs (A
0
- A
15
) defines which byte of data is to be
accessed from the selected SRAMs. Valid data will be available to the data output drivers within t
ACC
(Access Time) after the last address input signal is stable, providing that CE\ and OE\ access times are
also satisfied. If OE\ and CE\ access times are not satisfied, then data access must be measured from the
later occurring signal (CE\ or OE\) and the limiting parameter is either t
CO
for CE\ or t
OE
for OE\ rather
than t
ACC
.
WRITE MODE
The DS38464 executes a write cycle whenever both WE\ and CE\ signals are in the active (low) state
after address inputs are stable. The later occurring falling edge of CE\ or WE\ will determine the start of
the write cycle. The write cycle is terminated by the earlier rising edge of CE\ or WE\. All address
inputs must be kept valid throughout the write cycle. WE\ must return to the high state for a minimum
recovery time (t
WR
) before another cycle can be initiated. The OE\ control signal should be kept inactive
(high) during write cycles to avoid bus contention. However, if the output drivers are enabled (CE\ and
OE\ active) then WE\ will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS38464 provides full functional capability for V
CC
greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of V
CC
without any additional support circuitry. The
nonvolatile static RAM constantly monitors V
CC
. Should the supply voltage decay, the NV SRAM
automatically write protects itself, all inputs become "don't care," and all outputs become high
impedance. As V
CC
falls below approximately 2.5 volts, power switching circuits connect the lithium
energy sources to the RAMs to retain data. During power-up, when V
CC
rises above approximately 2.5
volts, the power switching circuits connect external V
CC
to the RAMs and disconnects the lithium
energy source. Normal RAM operation can resume after V
CC
exceeds 3.0 volts.
BATTERY MONITORING
The DS38464 automatically performs periodic battery voltage monitoring on a 24 hour time interval.
Such monitoring begins within t
REC
after V
CC
rises about V
TP
and is suspended when power failure
occurs.
After each 24 hour period has elapsed, the battery is connected to an internal 1M
W test resistor for one
second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output BW\ is asserted. Once asserted, BW\ remains active until the SIMM is replaced.
The battery is still retested after each V
CC
power-up, even if BW\ is active. If the battery voltage is
found to be higher than 2.6V during such testing, BW\ is de-asserted and regular 24-hour testing
resumes. BW\ has an open drain output driver.
PDF 
ZIP
