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Электронный компонент: 7025ERPQE-45

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Memory
All data sheets are subject to change without notice
(619) 503-3300- Fax: (619) 503-3301- www.maxwell.com
(8K x 16-Bit) Dual Port RAM
7025E
2002 Maxwell Technologies
All rights reserved.
High-Speed CMOS
08.15.02 Rev 2
F
EATURES
:
8K x 16-bit dual port RAM
- Stand Alone
- Master Slave
R
AD
-P
AK
radiation-hardened against natural space
radiation
Total dose hardness:
- > 100 krad (Si), depending upon space mission
Excellent Single Event Effects:
-SEL
TH
LET = >100 MeV/mg/cm
2
-SEU
TH
LET = 7 MeV/mg/cm
2
Package:
-84 Pin R
AD
-P
AK
quad flat pack
Separate upper byte and lower byte control for multiplexed
bus compatibility
High speed access time: 35/45 ns
Expandable to 32 bits or more using master/slave select
when cascading
High speed CMOS technology
-TTL compatible, single 5V power supply
-Interrupt flag for port-to-port communication
-On chip port arbitration logic
-Asynchronous operation from either port
D
ESCRIPTION
:
Maxwell Technologies' 7025E Dual Port RAM High Speed
CMOS microcircuit features a greater than 100 krad (Si) total
dose tolerance, depending upon space mission. The 7025E is
designed to be used as a stand-alone 128k-bit Dual Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 32-
bit or more word systems. This design results in full-speed,
error-free operation without the need for additional discrete
logic. The 7025E provides two independent ports with sepa-
rate control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by CS
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Maxwell Technologies' patented R
AD
-P
AK
packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
AD
-P
AK
provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
Logic Diagram
Memory
2
All data sheets are subject to change without notice
2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
08.15.02 Rev 2
T
ABLE
1. 7025E P
INOUT
D
ESCRIPTION
N
AMES
L
EFT
P
ORT
R
IGHT
P
ORT
Chip Select
CS
L
CS
R
Read/Write Select
R/W
L
R/W
R
Output Select
OS
L
OS
R
Address
AO
L
-A12
L
AO
R
-A12
R
Data Input/Output
I/OO
L
-I/O15
L
I/OO
R
-I/O15
R
Semaphore Select
SEM
L
SEM
R
Upper Byte Select
UB
L
UB
R
Lower Byte Select
LB
L
LB
R
Interrupt Flag
INT
L
INT
R
Busy Flag
BUSY
L
BUSY
R
M/S
Master or Slave Select
V
CC
Power
GND
Ground
T
ABLE
2. 7025E A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
S
YMBOL
M
IN
M
AX
U
NITS
Supply Voltage (Relative to V
SS
)
V
CC
-0.3
7.0
V
Operating Temperature Range
T
A
-55
125
C
Input or Output Voltage Applied
--
GND -0.3V
V
CC
+ 0.3
V
Storage Temperature Range
T
STG
-65
150
C
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
V
ARIATION
I
CCOP
10% A
S
S
TATED
I T
ABLE
6
I
CCOP1
10% A
S
S
TATED
I T
ABLE
6
I
CCSB
10% A
S
S
TATED
I T
ABLE
6
I
CCSB1
10% A
S
S
TATED
I T
ABLE
6
T
ABLE
4. 7025E R
ECOMMENDED
O
PERATING
C
ONDITIONS
P
ARAMETER
S
YMBOL
M
IN
M
AX
U
NITS
Supply Voltage Positive
V
CC
4.5
5.5
V
Input Voltage
V
IL
V
IH
-0.5
2.2
0.8
6.0
V
Memory
3
All data sheets are subject to change without notice
2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
08.15.02 Rev 2
Thermal Impedance
JC
--
1.02
C/W
Operating Temperature Range
T
A
-55
125
C
T
ABLE
5. 7025E C
APACITANCE
P
ARAMETER
S
YMBOL
M
IN
M
AX
U
NITS
Input Capacitance: V
IN
= 0V
1
1. Guaranteed by design.
C
IN
--
5
pF
Output Capacitance: V
OUT
= 0V
1
C
OUT
--
7
pF
T
ABLE
6. 7025E DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 5V 10%, T
A
= -55
TO
125
C
UNLESS
OTHERWISE
)
P
ARAMETER
S
YMBOL
S
UBGROUPS
M
IN
M
AX
U
NITS
Input Leakage Current
1
1. VCC = 5.5V, VIN = GND to VCC, CS = VIH, VOUT = 0 to VCC.
I
LI
1, 2, 3
--
10
A
Output Leakage Current
2
2. Vcc=5.5V; Vout = GND to Vcc
I
LO
1, 2, 3
--
10
A
Standby Supply Current, Both ports TTL level inputs
-35
-45
I
CCSB
1, 2, 3
--
--
50
50
mA
Standby Supply Current, Both ports CMOS level inputs
-35
-45
I
CCSB1
1, 2, 3
--
--
5
5
mA
Operating Supply Current, Both ports Active
-35
-45
I
CCOP
1, 2, 3
--
--
320
280
mA
Operating Supply Current, One Port Active, One Port Standby
-35
-45
I
CCOP1
1, 2, 3
--
--
190
180
mA
Input Low Voltage
3
Input High Voltage
3. VIH max = VCC + 0.3V, VIL min = -0.3V or -1V pulse width 50 ns
V
IL
V
IH
1, 2, 3
--
2.2
0.8
--
V
Output Low Voltage
4
Output High Voltage
4. V
CC
min, I
OL
= 4 mA, I
OH
= -4 mA.
V
OL
V
OH
1, 2, 3
--
2.4
0.4
--
V
T
ABLE
4. 7025E R
ECOMMENDED
O
PERATING
C
ONDITIONS
P
ARAMETER
S
YMBOL
M
IN
M
AX
U
NITS
Memory
4
All data sheets are subject to change without notice
2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
08.15.02 Rev 2
T
ABLE
7. 7025E AC E
LECTRICAL
C
HARACTERISTICS
FOR
R
EAD
C
YCLE
(V
CC
= 5V 10%, V
SS
= 0V, T
A
= -55
TO
125
C)
P
ARAMETER
S
YMBOL
S
UBGROUPS
M
IN
M
AX
U
NIT
Read Cycle Time
-35
-45
t
RC
9, 10, 11
35
45
--
--
ns
Address Access Time
-35
-45
t
AA
9, 10, 11
--
--
35
45
ns
Chip Select Access Time
1
-35
-45
1. To access RAM, CS = V
IL
, UB or LB = V
IL
, SEM = V
IH
. To access semaphore, CS = V
IN
and SEM = V
IL
. Either condition must be
valid for the entire t
EW
time.
t
ACS
9, 10, 11
--
--
35
45
ns
Byte Select Access Time
1
-35
-45
t
ABE
9, 10, 11
--
--
35
45
ns
Output Select to Output Valid
-35
-45
t
AOE
9, 10, 11
--
--
20
25
ns
Output Low Z Time
2,3
-35
-45
2. Guaranteed by design.
3. Transition is measured 500 mV from low or high impedance voltage with load.
t
LZ
9, 10, 11
3
3
--
--
ns
Output High Z Time
2,3
-35
-45
t
HZ
9, 10, 11
--
--
20
20
ns
Chip Enable to Power Up Time
2
t
PU
9, 10, 11
0
--
ns
Chip Disable to Power Up Time
2
t
PD
9, 10, 11
--
50
ns
Semaphore Flag Update Pulse (OE or SEM)
t
SOP
9, 10, 11
15
--
ns
T
ABLE
8. 7025E AC E
LECTRICAL
C
HARACTERISTICS
FOR
W
RITE
C
YCLE
(V
CC
= 5V 10%, V
SS
= 0V, T
A
= -55
TO
125
C)
P
ARAMETER
S
YMBOL
S
UBGROUPS
M
IN
M
AX
U
NIT
Write Cycle Time
-35
-45
t
WC
9, 10, 11
35
45
--
--
ns
Address Valid to End of Write
-35
-45
t
AW
9, 10, 11
30
40
--
--
ns
Memory
5
All data sheets are subject to change without notice
2002 Maxwell Technologies
All rights reserved.
(8K x 16-Bit) Dual Port RAM High-Speed CMOS
7025E
08.15.02 Rev 2
Chip Select to End of Write
1
-35
-45
t
SW
9, 10, 11
30
40
--
--
ns
Address Setup Time
-35
-45
t
AS
9, 10, 11
0
0
--
--
ns
Write Pulse Width
-35
-45
t
WP
9, 10, 11
30
35
--
--
ns
Write Recovery Time
-35
-45
t
WR
9, 10, 11
0
0
--
--
ns
Data Valid to End of Write
-35
-45
t
DW
9, 10, 11
25
25
--
--
ns
Output High Z Time
2,3
-35
-45
t
HZ
9, 10, 11
--
--
20
20
ns
Data Hold Time
-35
-45
t
DH
9, 10, 11
0
0
--
--
ns
Write Select to Output in High Z
2,3
-35
-45
t
WZ
9, 10, 11
--
--
20
20
ns
Output Active from End of Write
2,3,4
-35
-45
t
OW
9, 10, 11
0
0
--
--
ns
SEM Flag Write to Read Time
-35
-45
t
SWRD
10
10
--
--
ns
SEM Flag Contention Window
-35
-45
t
SPS
10
10
--
--
ns
1. To access RAM, CS = V
IL
, UB or LB = V
IL
, SEM = V
IH
. To access semaphore, CS = V
IN
and SEM = V
IL
. Either condition must be
valid for the entire t
EW
time.
2. Guaranteed by design.
3. Transition is measured 500 mV from low or high impedance voltage with load.
4. The specification for t
DH
must be met by the device supplying write data to the RAM under all operating conditions. Although t
DH
and t
DW
.
T
ABLE
8. 7025E AC E
LECTRICAL
C
HARACTERISTICS
FOR
W
RITE
C
YCLE
(V
CC
= 5V 10%, V
SS
= 0V, T
A
= -55
TO
125
C)
P
ARAMETER
S
YMBOL
S
UBGROUPS
M
IN
M
AX
U
NIT