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16-Bit Latchup Protected Analog to Digital Converter

7809LP

01.11.05 Rev 7

BUSY

Busy Output. Falls when a conversion is started, and remains LOW until the conversion is com-
pleted and the data is latched into the output shift register. CS or R/C must be HIGH when
BUSY rises, or another conversion will start without time for signal acquisition.

PWRD

Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly
reduced. Results from the previous conversions are maintained in the output shift register.

LPVANA

Latchup Protection Analog Supply.

LPVDIG

Latchup Protection Digital Supply.

ABLE

2. 7809LP A

BSOLUTE

AXIMUM

ATINGS

ARAMETER

YMBOL

NIT

Analog Inputs

CAP

REF

1. Indefinite short to AGND2, momentarily short to V

ANA

-25
-25
-25

ANA

+ 0.3

25
25
25

AGND2 - 0.3

V
V
V
V

Ground Voltage Differences: DGND, AGND2

-0.3

0.3

ANA

DIG

to V

ANA

0.3

Specified Performance

-40

Digital Inputs

-0.3

DIG

+ 0.3

Storage Temperature

STG

-65

150

ABLE

3. 7809LP DC A

CCURACY

PECIFICATIONS

PECIFIED

ERFORMANCE

-40

+85°C)

ARAMETER

NIT

Integral Linearity Error
-40 to 85°C

--
--

±3
±5

LSB

Differential Linearity Error
-40 to 85°C

--
--

-2, 3
-1, 6

LSB
LSB

No Missing Codes

Bits

Transition Noise

1.3

LSB

Full Scale Error

4,5

±0.6

Full Scale Error

4,5

(using ext. 2.5000 V

ref

)

±0.6

Full Scale Error Drift

±7

ppm/

ABLE

1. 7809LP P

ESCRIPTION

YMBOL

ESCRIPTION

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16-Bit Latchup Protected Analog to Digital Converter

7809LP

01.11.05 Rev 7

Full Scale Error Drift (using ext. 2.5000 V

ref

)

±2

ppm/

Bipolar Zero Error

±10

Bipolar Zero Error Drift

±2

ppm/

Unipolar Zero Error

-40 to 85°C

--
--

±3

±16

mV
mV

Unipolar Zero Error Drift

±2

ppm/

Recovery to Rated Accuracy after Power Down (1 uF Capacitor to
CAP)

Power Supply Sensitivity (V

DIG

= V

ANA

= V

) 4.75 V > V

< 5.2 V

-40 to 85°C

--
--

±8

±32

LSB
LSB

1. LSB stands for Least Significant Bit. One LSB is equal to 305 µ V.

2. Not tested.

3. Typical rms noise at worst case transitions and temperatures.

4. Measured with various fixed resistors.

5. For bipolar input ranges, full scale error is the worst case of -Full Scale or +Full Scale untrimmed deviation from ideal first and

last scale code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset
error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It
also includes the effect of offset error.

ABLE

4. D

ELTA

IMITS

ARAMETER

ARIATION

+/- 10%

ABLE

5. 7809LP D

IGITAL

NPUTS

PECIFIED

ERFORMANCE

-40

+85°C)

ARAMETER

UBGROUPS

NIT

, I

1, 2, 3

-0.3

2.0

--
--
--

0.8

+ 0.3

±10

V
V

µ A

ABLE

3. 7809LP DC A

CCURACY

PECIFICATIONS

PECIFIED

ERFORMANCE

-40

+85°C)

ARAMETER

NIT

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16-Bit Latchup Protected Analog to Digital Converter

7809LP

01.11.05 Rev 7

ABLE

6. 7809LP A

NALOG

NPUT

AND

HROUGHPUT

PEED

PECIFIED

ERFORMANCE

-40

+85°C)

ARAMETER

UBGROUPS

NIT

Voltage Ranges

10 V, 0 V to 5 V

See Table 2.

Impedance

Capacitance

1. Guarenteed by design.

1, 2, 3

Conversion Time

9, 10, 11

7.6

µ s

Complete Cycle (Acquire and Convert)

9, 10, 11

µ s

Throughput Rate

2. Tested by application of signal.

9, 10, 11

100

kHz

ABLE

7. 7809LP AC A

CCURACY

PECIFICATIONS

PECIFIED

ERFORMANCE

-40

+85°C)

ARAMETER

UBGROUPS

NIT

Spurious-Free Dynamic Range, f

= 20 kHz

1. Guaranteed by design.

4, 5, 6

100

2. All specifications in dB are referred to a full-scale ±10 V input.

Total Harmonic Distortion, f

= 20 kHz

4, 5, 6

-100

-90

Signal-to-Noise (Noise + Distortion)

= 20 kHz

-60 dB Input

4, 5, 6

88
30

--
--

Signal-to-Noise

, f

= 20 kHz

Full-Power Bandwidth

1,3

3. Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to-Noise (Noise + Distortion) degrades to 60 dB.

9, 10, 11

250

kHz

ABLE

8. 7809LP S

AMPLING

YNAMICS

PECIFIED

ERFORMANCE

-40

+85°C)

ARAMETER

UBGROUPS

NIT

Aperture Delay

9, 10, 11

Aperture Jitter

9, 10, 11

Sufficient to meet AC specification

Transient Response FS Step

9, 10, 11

Overvoltage Recovery

1. Recovers to specified performance after 2 X FS input overvoltage.

9, 10, 11

150

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16-Bit Latchup Protected Analog to Digital Converter

7809LP

01.11.05 Rev 7

ABLE

9. 7809LP R

EFERENCE

PECIFIED

ERFORMANCE

-40

+85°C)

ARAMETER

ONDITIONS

NIT

Internal Reference Voltage

No Load

2.48

2.5

2.52

Internal Reference Source Current (Must be
ext. buffer)

µ A

External Reference Voltage Range for Speci-
fied Linearity

1. Tested by application of signal.

2.3

2.5

2.7

External Reference Current Drain

Ext. 2.5000V Ref

100

µ A

ABLE

10. 7809LP D

IGITAL

UTPUTS

PECIFIED

ERFORMANCE

-40

+85°C)

ARAMETER

UBGROUPS

ONDITIONS

NIT

Data Format
Data Coding
Pipeline Delay

Serial 16-bits
Binary Two's Complement or Straight Binary
Conversion results only available after completed conversion

Data Clock

Internal (Output Only When

Transmitting Data)

External (Can Run Continually)

Selectable for internal or external data clock

9, 10, 11

EXT/INT Low
EXT/INT High

0.1

2.3

MHz

1, 2, 3

SINK

= 1.6 mA

SOURCE

= 500 µ A

--
--

0.4

Leakage Current

1. Not tested.

1, 2, 3

High-Z State,
V

OUT

= 0V to V

DIG

±10

µ A

Output Capacitance

1, 2, 3

High-Z State

ABLE

11. 7809LP P

OWER

UPPLIES

PECIFIED

ERFORMANCE

-40

+85°C)

ARAMETER

UBGROUPS

ONDITIONS

NIT

DIG

1, 2, 3

Must be < V

ANA

4.75

5.25

ANA

1, 2, 3

4.75

5.25

DIG

1, 2, 3

0.3

ANA

1, 2, 3

Power Dissipation

PWRD LOW
PWRD HIGH

1, 2, 3

ANA

= V

DIG

= 5V

= 100 kHz

--
--

132
100

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16-Bit Latchup Protected Analog to Digital Converter

7809LP

01.11.05 Rev 7

ABLE

12. 7809LP C

ONTROL

INE

UNCTIONS

FOR

EAD

AND

ONVERT

PECIFIC

UNCTION

R/C

BUSY

EXT/INT

DATACL

PWRD

SB/BTC

PERATION

Initiate Conver-
sion and Output
Data using Inter-
nal Clock

1 > 0

Output

Initiates conversion "n".
Data from conversion "n-
1" clocked out on DATA
synchronized to 16 clock
pulses output on DATA-
CLK

Initiate Conver-
sion and Output
Data using Exter-
nal Clock

1 > 0

0 > 1

Input

Initiates conversion "n"

Outputs a pulse on SYNC
followed by data from con-
version "n" clocked out
synchronized to external
DATACLK.

Outputs a pules on SYNC
followed by data from con-
version "n-1" clocked out
synchronized to external
DATACLK

. Conversion

"n" in process.

Outputs a pulse on SYNC
followed by data from con-
version "n-1" clocked out
synchronized to external
DATACLK

. Conversion

"n" in process.

Incorrect Conver-
sions

0 > 1

CS or R/C must be HIGH
or a new conversion will
be initiated without time
for acquisition

Power Down

Analog circuitry powered.
Conversion will be initi-
ated without time for
acquisition

Analog circuitry disabled.
Data from previous con-
version maintained in out-
put registers

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16-Bit Latchup Protected Analog to Digital Converter

7809LP

01.11.05 Rev 7

Selecting Output
Format

0
3

Serial data is output in
Binary Two's Comple-
ment format.

Serial data is output in
Straight Binary format.

1. See Figure 4 for constraints on previous data valid during conversion.

ABLE

13. 7809LP I

NPUT

ANGE

ONNECTION

NALOG

NPUT

ANGE

ONNECT

VIA

200

ONNECT

VIA

100

ONNECT

MPEDANCE

±10V

AGND

CAP

22.9 k

±5V

AGND

CAP

13.3 k

±3.3V

CAP

10.7 k

0V to 10V

AGND

13.3k

0V to 5V

AGND

10.0 k

0V to 4V

AGND

10.7 k

ABLE

14. 7809LP C

ONVERSION

AND

ATA

IMING

= -40

UNLESS

OTHERWISE

SPECIFIED

)

YMBOL

ESCRIPTION

UBGROUPS

NIT

Convert Pulse Width

9, 10, 11

6000

BUSY Delay

9, 10, 11

BUSY LOW

9, 10, 11

µ s

BUSY Delay after End of Conversion

9, 10, 11

220

Aperture Delay

9, 10, 11

Conversion Time

9, 10, 11

7.6

µ s

Acquisition Time

9, 10, 11

µ s

t6 + t7

Throughput Time

9, 10, 11

µ s

R/C Low to DATACLK Delay

9, 10, 11

450

DATACLK Period

9, 10, 11

440

t10

Data Valid to DATACLK HIGH Delay

9, 10, 11

t11

Data Valid after DATACLK LOW
Delay

9, 10, 11

100

125

t12

External DATACLK

9, 10, 11

100

ABLE

12. 7809LP C

ONTROL

INE

UNCTIONS

FOR

EAD

AND

ONVERT

PECIFIC

UNCTION

R/C

BUSY

EXT/INT

DATACL

PWRD

SB/BTC

PERATION

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16-Bit Latchup Protected Analog to Digital Converter

7809LP

01.11.05 Rev 7

t13

External DATACLK HIGH

9, 10, 11

t14

External DATACLK LOW

9, 10, 11

t15

DATACLK HIGH Setup Time

9, 10, 11

t12 + 5

t16

R/C to CS Setup Time

9, 10, 11

t17

SYNC Delay After DATACLK High

9, 10, 11

t18

Data Valid Delay

9, 10, 11

t19

CS to Rising Edge Delay

9, 10, 11

t20

Data Available after CS LOW

9, 10, 11

µ s

ABLE

15. 7809LP C

ONVERSION

ATA

IMING

ESCRIPTION

NALOG

NPUT

IGITAL

UTPUT

INARY

OMPLEMENT

(SB/BTC

LOW)

TRAIGHT

INARY

(SB/BTC H

IGH

)

INARY

ODE

INARY

ODE

Full Scale
Range

±10

±5

±3.33V

0V to

10V

0V to 5V 0V to 4V

Least Signifi-
cant Bit (LSB)

305 µ V

153 µ V

102 µ V

153 µ V

76 µ V

61 µ V

+ Full Scale
(FS - 1 LSB)

9.99969

4.99984

3.33323

9.99984

4.99992

3.99993

0111 1111

1111 1111

7FFF

1111 1111
1111 1111

FFFF

Midscale

2.5V

0000 0000
0000 0000

0000

1000 0000
0000 0000

8000

One LSB
Below Mid-
scale

-305 µ V -153 µ V -102 µ V

4.99984

2.49992

1.99993

1111 1111
1111 1111

FFFF

0111 1111

1111 1111

7FFF

-Full Scale

-10V

-5V

3.33333

1000 0000
0000 0000

8000

0000 0000
0000 0000

0000

ABLE

14. 7809LP C

ONVERSION

AND

ATA

IMING

= -40

UNLESS

OTHERWISE

SPECIFIED

)

YMBOL

ESCRIPTION

UBGROUPS

NIT

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16-Bit Latchup Protected Analog to Digital Converter

7809LP

01.11.05 Rev 7

LPT

Operation

Latchup Protection Technology (LPT

) automatically detects an increase in the supply current of the 7809LP con-

verter due to a single event effect and internally cycles the power to the converter off, then on, which restores the
steady state operation of the device. A simplified block diagram of the 7809LP circuitry is shown in Figure 7. The
LPT

circuitry consists of two power switch and current sensor blocks, an LPT

controller block, a BIT current load

block, and an active input protection block.

Figure 7. 7809LP Simplified Block Diagram

The power switch/current sensor blocks sense the supply current drawn by the protected device on the analog and
digital supply pins. When a threshold level is exceeded on either supply line, indicating single event induced latchup of
the protected device, a signal is sent to the LPT

controller block. The LPT

controller then drives the power

switches to an off state which removes the power supplies from the protected device. At the same time, a signal is
sent to open the active input protection circuits and the LPSTATUS output pin is activated. After a period of time suffi-
cient to clear the latchup, the LPT

controller drives the power switches and input protection back to the on state

restoring the operation of the protected device. The LPTBIT circuit is used during system test to electrically trigger the
latchup function by drawing current through the power switch/current sensor blocks sufficient to trigger the LPT

pro-

tection.

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16-Bit Latchup Protected Analog to Digital Converter

7809LP

01.11.05 Rev 7

Differences Between the 7809LP and the ADS7809

Because the 7809LP uses the ADS7809 die to perform the analog to digital conversion function, its operation and per-
formance is very similar to the ADS7809 packaged part from Burr-Brown. In general the operation and application will
be the same for both parts. There are three primary differences: the operation of the supply pins, the operation of the
additional LPBIT and LPSTATUS pins, and the operation of the I/O pins when a latchup is detected.

The ADS7809 provides separate analog and digital supply pins, VANA and VDIG. These same supply pins on the
7809LPRP should be connected to the analog and digital supplies. There is no limit to the capacitance that can be
connected to these pins in the system application.

The 7809LP package also provides access to the ADS7809 die supply pins with the LPVANA and LPVDIG pins. The
signal paths between the supply input pins and the respective die supply pins are low resistance during normal device
operation. When an excessive supply current due to a single event latchup is sensed on either of the supply pins, the
LPT

circuit opens both paths to the die supply pins allowing the latchup condition to clear. The LPVANA and LPV-

DIG pins allow access to the current sense circuitry for electrical testing at the component level and provide optimal
locations for attaching supply decoupling capacitors. CAUTION: The LPVANA and LPVDIG pins must not be con-
nected to the respective power supplies since this will defeat the LPT

power switch and could result in permanent

latchup of the device during operation in a radiation environment. Electrolytic capacitors should not be connected to
these decoupling pins because the large capacitance will increase the recovery time of the 7809LP. Low ESR ceramic
capacitors should be used with a maximum of .2µ F per pin.

The LPBIT input provides a means to electrically test the LPT

circuit. A high level on the this pin causes a preset

current to be drawn in addition to the normal device current through the analog and digital current sensors. If the high
level is maintained for a sufficient duration, it will trigger the LPT

circuit which will cycle the power to the protected

device. If the LPBIT remains high, the LPT

circuit will continuously cycle the supply voltages off then on. Driving this

input with a 10 µ s high level pulse is sufficient duration to assure the LPT

circuit cycles the power off then on one

time only.

A high level on the LPSTATUS output indicates that the LPT

circuit has removed power from the protected device.

The LPSTATUS returns low when the power is restored. LPSTATUS can be used to generate an input to the system
data processor indicating that an LPT

cycle has occurred and the protected device output accuracy may not be met

until after the respective recovery time to the event.

During the time that power is removed from the protected device, it is critical that external circuitry driving the device I/
O pins does not back-drive the device supply through input protection diodes or similar integrated structures. Back-
driving of the supply through the device I/O pins could contribute to an extended or even a permanent latchup condi-
tion. For the ADS7809 testing has shown that for the normal signal range of operation on the analog input pins R1IN,
R2IN, and R3IN, latchup will not be sustained.

In order to prevent back-driving the supply from the digital I/O pins DATA, SYNC, TAG, R/C, CS, and PWRD, the
7809LP incorporates active input protection circuits. These circuits act as transmission gates in series with the digital
inputs. During normal operation, these gates are on and present low resistance connections between the package
input pins and the respective die pins. When the LPT

circuit detects a latchup, these gates are switched off and

present a high resistance path between the package inputs and the die inputs. The protected I/O pins are crow barred
during the latchup. The bidirectional signal, DATACLK, is also protected by a transmission gate.

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16-Bit Latchup Protected Analog to Digital Converter

7809LP

01.11.05 Rev 7

Dedicated digital outputs are not similarly protected since in most applications there will be no appreciable drive signal
on these outputs to back-drive the pins. Pull up resistors on these outputs should be 10 K

or greater to limit the

back-drive current. Low on resistance, transmission gate circuits are also connected between the package pins and
the die REF and CAP pins. These gates minimize the transient loading on the external filter capacitors required on
these pins. This greatly reduces the single event recovery time of the 7809LP to full accuracy after an LPT

cycle.

During an LPT

cycle, all outputs of the 7809LP are invalid and unpredictable until after the functional recovery time.

After the functional recovery time, data conversions occur with a degraded accuracy until the full accuracy recovery
time.

A summary of the pin differences between the ADS7809 and the 7809LP is provided in the table below.

ABLE

15. ADS7809

AND

7809LP P

IFFERENCES

UMBER

ADS7809

7809LPRP

IFFERENCE

ESCRIPTION

1-10

Various

Equivalent function to ADS7809 pins 1-10 respectively. Timing specifications
change slightly (0 - 10 ns) for the 7809LPRP due to the latchup protection circuitry
on ADS7809 die inputs.

15-22

Various

Equivalent function to ADS7809 pins 11-18 respectively. Timing specifications
change slightly (0 - 10 ns) for the 7809LPRP due to the latchup protection circuitry
on ADS7809 die inputs.

LPBIT

A built in test function of latchup protection. A TTL high level pulse for > 5 microsec-
onds duration on this input will trigger latchup protection of the device. This input
shall be low during normal operation.

LPSTATUS

Latchup protection status output. This TTL level output is low during normal opera-
tion and goes high during a 10 µ s decision time period prior to power being
removed. If the latch up current does not last at least 10 µ s then LPTSTATUS will
go low (inactive) after the 10 µ s decision period without power being removed.
When latchup protection is triggered, this output will go high for the duration of the
time that power is removed from the protected device (50 µ s). All output except
LPSTATUS are invalid during the time that power is removed from the ADS7809
die. This output foes low within 1 us of the power being re-applied to the protected
device. Functional operation of the device is within ~25 µ s after the LPSTATUS
output returns low with degraded accuracy due to the latchup filter circuitry. Full
accuracy is restored ~5 ms later. This output can be used to inform the system pro-
cessor of the latchup protection trigger and the subsequent degraded accuracy in
the 7809LPRP output data. Output pull-up resistors should be 10k

or larger on

outputs. I/O pins must not be driven high while this signal is active.

VANA

Equivalent function to ADS7809 pin 19. Analog Supply Input.

VDIG

Equivalent function to ADS7809 pin 20. Digital Supply Input.

LPVANA

Latchup protected analog supply pin to the ADS7809 die. Decouple to analog
ground with 0.1 µ F ceramic capacitor. Do not exceed 0.2 µ F. Do not connect to
VDIG and/or VANA.

LPVDIG

Latchup protected digital supply pin to the ADS7809 die. Decouple to digital ground
with 0.1 µ F ceramic capacitor. Do not exceed 0.2 µ F. Do not connect to VDIG and/
or VANA.

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16-Bit Latchup Protected Analog to Digital Converter

7809LP

01.11.05 Rev 7

Testing the 7809LPRP Latchup Protection Circuitry

The LPVANA and LPVDIG pins provide direct access to the 7809LP converter supply pins for attaching external
decoupling capacitors to ground. These pins can also be used to test the LPT

operation and threshold level by sink-

ing a pulsed current load to ground as shown in the test circuit in Figure 8. The most accurate threshold current mea-
surements are made with the ADS7809 in its lowest power state (PWRD = 5V).

The LPT

operation and device recovery times are most easily measured using the LPBIT input to trigger protection

and recovery. Applying a 10 µ sec high duration TTL level to the LPBIT pin causes internal test currents sufficient to
trigger the LPT

circuit to be drawn through both the analog and digital supply sense circuits.

LPT

operating characteristics are summarized in Table 16 according to the timing diagram shown in Figure 9. Dur-

ing the time that the power is cycled, output signals and data from the 7809LP are invalid. The LPSTATUS signal high
indicates that power is removed from the ADS7809 die. When this signal is low, power is applied to the ADS7809 die.
The LPSTATUS signal is used to measure the supply recovery time. The supply recovery time interval starts when the
supply current rises (causing LPSTATUS to go high) and ends when the LPSTATUS signal stabilizes low again.

Within the functional recovery time interval (~25 µ sec after the LPT

circuit reapplies power), the normal functional

operation of the converter is restored with less than 5% full scale error. Additional settling time is then required to
return to full accuracy operation. Recovery time intervals are defined which indicate the time to recover first to within 8
bit accuracy, then to within 12 bit accuracy, and finally to full 16 bit accuracy. These recovery times are primarily due to
the single event and power cycling effects on the reference circuits and the settling times of their respective filter
capacitors.

ABLE

16. 7809LP LPT

PERATING

HARACTERISTICS

ARAMETER

YMBOL

ONDITIONS

NIT

Supply Threshold Current

ITHR

PWRD = 5V

Protection Time

TPT

LPBIT = 2.4V for 5 µ s

µ sec

Supply Recovery Time

TSR

LPBIT = 2.4V for 5 µ s

µ sec

Functional Recovery Time

TFR

LPBIT = 2.4V for 5 µ s

TSR + 25

µ sec

8-bit Accuracy Recovery Time

T8R

LPBIT = 2.4V for 5 µ s

µ sec

Full Accuracy Recovery Time

TFAR

LPBIT = 2.4V for 5 µ s

msec

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16-Bit Latchup Protected Analog to Digital Converter

7809LP

01.11.05 Rev 7

Important Notice:

These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.

Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech-
nologies. Maxwell Technologies' liability shall be limited to replacement of defective parts.

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 7809LP