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(619) 503-3300 - Fax: (619) 503-3301 - www.maxwell.com

16 Megabit (512K x 32-Bit)

89LV1632

Low Voltage MCM SRAM

08.18.05 Rev 3

EATURES

· Four 512k x 8 SRAM die
· R

-P

® technology hardens against natural space radia-

tion technology

· Total dose hardness:

- > 100 krad (Si), depending upon space mission

· Excellent Single Event Effects:

- SEL > 101MeV-cm

/mg

- SEU threshold = 3 MeV-cm

/mg

- SEU saturated cross section: 8E-9 cm

/bit

· Package: 68-pin quad flat package
· Completely static memory - no clock or timing strobe

required

· Internal bypass capacitor
· High-speed silicon-gate CMOS technology
· 3.3 V ± 10% power supply
· Equal address and chip enable access times
· Three-state outputs
· All inputs and outputs are TTL compatible

ESCRIPTION

Maxwell Technologies' 89LV1632 high-performance 16 Mega-
bit Multi-Chip Module (MCM) Static Random Access Memory
features a greater than 100 krad(Si) total dose tolerance,
depending upon space mission. The four 4-Megabit SRAM die
and bypass capacitors are incorporated into a high-reliable
hermetic quad flat-pack ceramic package. With high-perfor-
mance silicon-gate CMOS technology, the 89LV1632 reduces
power consumption and eliminates the need for external
clocks or timing strobes. It is equipped with output enable
(OE) and four byte chip enable (CS1 - CS4) inputs to allow
greater system flexibility. When OE input is high, the output is
forced to high impedance.

Maxwell Technologies' patented R

-P

® packaging technol-

ogy incorporates radiation shielding in the microcircuit pack-
age. In a GEO orbit, R

-P

® packaging provides greater

than 100 krad(Si) total radiation dose tolerance, dependent
upon space mission. It eliminates the need for box shielding
while providing the required radiation shielding for a lifetime in
orbit or a space mission. This product is available in with
screening up to Maxwell Technologies self-defined Class K.

CS 1-4

MCM

OE, WE

Address

4Mb SRAM

Power

Ground

I/O 0-7

I/O 8-15

I/O 16-23

I/O 24-31

16 Megabit (512k x 32-bit) SRAM MCM

Logic Diagram

89LV1632

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16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM

89LV1632

08.18.05 REV 3

ABLE

1. P

INOUT

ESCRIPTION

YMBOL

ESCRIPTION

34-28, 42-36, 62-64, 7, 8

A0-A18

Address Enable

WriteEnable

Output Enable

3-6

CS1 - CS4

Chip Enable

43-46, 48-51,53-56, 58-61,

9-12, 14-17, 19-22, 24-27

I/O0-I/O31

Data Input/Output

2, 67, 68

No Connection

1, 18, 35, 52

+3.3V Power Supply

13, 23, 47, 57

Ground

ABLE

2. 89LV1632 A

BSOLUTE

AXIMUM

ATINGS

OLTAGE

REFERENCED

= 0V)

ARAMETER

YMBOL

NITS

Power Supply Voltage Relative to V

-0.5 +7.0

Voltage Relative to V

for Any Pin Except V

, V

OUT

-0.5

+0.5

Weight

Grams

Thermal Resistance

3.6

C/W

Power Dissipation

4.0

Operating Temperature

-55

+125

Storage Temperature

-65

+150

ABLE

3. 89LV1632 R

ECOMMENDED

PERATING

ONDITIONS

= 3.3+ 10%, T

= -55

+125

UNLESS

OTHERWISE

NOTED

)

ARAMETER

YMBOL

NITS

Supply Voltage, (Operating Voltage Range)

3.0

3.6

Input High Voltage

2.2

+ 0.5

(1)

1. V

(max) = V

+ 2V ac (pulse width < 10ns) for I < 80 mA.

Input Low Voltage

-0.5

(2)

2. V

(min) = -2.0V ac; (pulse width < 20 ns) for I < 80 mA.

0.8

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16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM

89LV1632

08.18.05 REV 3

ABLE

4. 89LV1632 D

ELTA

IMITS

ARAMETER

ARIATIONL

+10% of stated value in table 5

SB1

+10% of stated value in table 5

ABLE

5. 89LV1632 DC E

LECTRICAL

HARACTERISTICS

= 3.3+ 10%, T

= -55

+125

UNLESS

OTHERWISE

NOTED

)

ARAMETER

YMBOL

EST

ONDITIONS

UBGROUPS

NITS

Input Leakage Current

= 0 to V

1, 2, 3

-8.0

+8.0

Output Leakage Current

CS = V

, V

OUT

= V

to V

1, 2, 3

-8.0

+8.0

Average Operating Current
Cycle Time:

35 ns

Min. Cycle, 100% Duty, CS = V

OUT

= 0 mA

= V

or V

1, 2, 3

640

Standby Power Supply Current

CS= V

, Min Cycle

1, 2, 3

240

CMOS Standby Power Supply
Current

SB1

CS > V

- 0.2V, f = 0 MHz, V

- 0.2V or

0.2V

1, 2, 3

Output Low Voltage

= + 8.0 mA

1, 2, 3

0.4

Output High Voltage

= -4.0 mA

1, 2, 3

2.4

Input Capacitance

CS1 - CS4,
OE, WE
I/O0-7, I/O8-15, I/O16-23,

I/O24-31
A0 - A18

1. Guaranteed by design.

= 0 V

4, 5, 6

7
7

Output Capacitance

OUT

I/O

= 0 V

4, 5, 6

ABLE

6. 89LV1632 AC O

PERATING

ONDITIONS

AND

HARACTERISTICS

= 3.3+ 10%, T

= -55

+125

UNLESS

OTHERWISE

NOTED

)

ARAMETER

NITS

Input Pulse Level

0.0

3.0

Output Timing Measurement Reference Level

1.5

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16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM

89LV1632

08.18.05 REV 3

Input Rise/Fall Time

3.0

Input Timing Measurement Reference Level

1.5

ABLE

7. 89LV1632 R

EAD

YCLE

= 3.3+ 10%, T

= -55

+125

UNLESS

OTHERWISE

NOTED

)

ARAMETER

YMBOL

UBGROUPS

NITS

Read Cycle Time

-30

9, 10, 11

Address Access Time

-30

9, 10, 11

Chip Select to Output

-30

9, 10, 11

Output Enable to Output

-30

9, 10, 11

Output Enable to Low-Z Output

-30

OLZ

9, 10, 11

Chip Enable to Low-Z Output

-30

9, 10, 11

Output Disable to High-Z Output

-30

OHZ

9, 10, 11

Chip Disable to High-Z Output

-30

9, 10, 11

Output Hold from Address Change

-30

9, 10, 11

Chip Select to Power Up Time

-30

9, 10, 11

Chip Select to Power DownTime

-30

9, 10, 11

ABLE

8. 89LV1632 F

UNCTIONAL

ESCRIPTION

ODE

I/O P

UPPLY

URRENT

1. X = don't care.

Not Select

High-Z

, I

SB1

Output Disable

High-Z

Read

OUT

Write

ABLE

6. 89LV1632 AC O

PERATING

ONDITIONS

AND

HARACTERISTICS

= 3.3+ 10%, T

= -55

+125

UNLESS

OTHERWISE

NOTED

)

ARAMETER

NITS

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16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM

89LV1632

08.18.05 REV 3

ABLE

9. 89LV1632 W

RITE

YCLE

= 3.3+ 10%, T

= -55

+125

UNLESS

OTHERWISE

NOTED

)

ARAMETER

YMBOL

UBGROUPS

NITS

Write Cycle Time

-30

9, 10, 11

Chip Select to End of Write

-30

9, 10, 11

Address Set-up Time

-30

9, 10, 11

Address Valid to End of Write

-30

9, 10, 11

Write Pulse Width (OE High)

-30

9, 10, 11

Write Pulse Width (OE Low)

-30

WP1

9, 10, 11

Write Recovery Time

-30

9, 10, 11

Write to Output High-Z

-30

WHZ

9, 10, 11

Data to Write Time Overlap

-30

9, 10, 11

Data Hold from Write Time

-30

9, 10, 11

End Write to Output Low-Z

-30

9, 10, 11

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16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM

89LV1632

08.18.05 REV 3

IGURE

1. AC T

EST

OADS

IGURE

2. T

IMING

AVEFORM

EAD

YCLE

(1)

DDRESS

ONTROLLED

)

IGURE

3. T

IMING

AVEFORM

EAD

YCLE

(2)

(WE = V

)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

+ 3.3V

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16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM

89LV1632

08.18.05 REV 3

3. t

and t

OHZ

are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V

levels.

4. At any given temperature and voltage conditions, t

(max) is less than t

(min) both for a given device and from device to

device.

5. Transition is measured +200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS = V

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write

cycle.

IGURE

4. T

IMING

AVEFORM

RITE

YCLE

(1)

(OE C

LOCK

)

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16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM

89LV1632

08.18.05 REV 3

IGURE

5. T

IMING

AVEFORM

RITE

YCLE

(2)

(OE L

IIXED

)

IGURE

6. T

IMING

AVEFORM

RITE

YCLE

(3)

(CS C

ONTROLLED

)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low.

A write ends at the earliest transition CS going high or WE going high. t

is measured from the beginning of write to the end

of write.

3. t

is measured from the later of CS going low to end of write.

4. t

is measured from the address valid to the beginning of write.

5. t

is measured from the end of write to the address change. t

applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization of elimination of bus contention conditions is necessary during read and write

cycle.

8. If CS foes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. D

OUT

is the read data of the new address.

10.When CS is low, I/O pins are in the output state. The input signals in the opposite phase leading to the output should not

be applied.

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16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM

89LV1632

08.18.05 REV 3

Q68-04

Note: All dimensions in inches

68 P

-P

® Q

UAD

LAT

ACKAGE

YMBOL

IMENSION

0.206

0.225

0.244

0.015

0.017

0.018

0.008

0.009

0.12

1.479

1.494

1.509

0.800

0.050 BSC

0.339

1.239

1.244

1.249

1.429

1.434

1.439

2.485

2.510

2.545

2.485

2.500

2.505

1.690

1.700

1.710

0.180

0.195

0.210

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16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM

89LV1632

08.18.05 REV 3

Important Notice:

These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.

Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech-
nologies. Maxwell Technologies' liability shall be limited to replacement of defective parts.

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16 Megabit (512K x 32-Bit)Low Voltage MCM SRAM

89LV1632

08.18.05 REV 3

Product Ordering Options

Model Number

Feature

Option Details

89LV1632 RP

-XX

Access Time

Screening Flow

Package

Radiation Feature

Base Product
Nomenclature

30 = 30 ns

Multi Chip Module (MCM)

K = Maxwell Self-Defined Class K
H = Maxwell Self-DefinedClass H
I = Industrial (testing at-55°C,
+25°C, +125°C)
E = Engineering (testing at +25°C)

Q = Quad Flat Pack

RP = R

-P

® package

16 Megabit (512K x 32-Bit) MCM
SRAM

1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K flows.

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