REVISIONS
NO
VERSION
APPROVED
The information disclosed herein was originated by and is the
property of MAZeT. MAZeT reserves all patent, proprietary, design,
use, sales, manufacturing an reproduction rights thereto. Product
names used in this publication are for identification purposes only
and may be trademark of their respective companies.
1
1.0
2000-09-18
Approvals
Date
MAZeT GmbH
Compiled:
2000-09-18
Checked:
2000-09-18
Status: valid
MAZeT GmbH Sales
Gschwitzer Strae 32
07745 JENA / GERMANY
Phone: +49 3641 2809-0
Fax: +49 3641 2809-12
E-Mail: sales@MAZeT.de
Url: http://www.MAZeT.de
Released:
2000-09-18
DOC. NO: DB-99-064e
Page 1 of 11
Data Sheet
MMI200-PC/104
Encoder Interface Board
SSI
square wave
incremental signals
(Bi-directional interface for absolute
encoders according to the
specification of DR. J. HEIDENHAIN
GmbH)
(Unidirectional interface for
absolute encoders)
(TTL-interface for incremental
encoders with a 32 bit encoder
counter)
Table of contents
1 GENERAL DESCRIPTION
2
2 ISA INTERFACE
3
3 REGISTER DESCRIPTION
4
3.1
On-board command register
4
3.2
Optical coupler input register
4
3.3
On-board interrupt enable register
4
3.4
MMI4832 registers
5
4 OPTICAL COUPLER
6
4.1
Optical coupler inputs
6
4.2
Optical coupler outputs
7
5 MEASUREMENT SYSTEM INTERFACE
8
6 BOARD DESIGN MECHANICS
10
7 ELECTRICAL SPECIFICATIONS
10
7.1
Absolute Maximum ratings
10
7.2
Recommended operating conditions
10
7.3
Electrical characteristics
11
REVISIONS
NO
VERSION
APPROVED
1
1.0
2000-09-18
1
The information in this publication is believed to be accurate in all respects at the time
of publication. MAZeT reserves the right to make changes in its products without notice
in order to improve design or performance characteristics.
DOC. NO:
DB-99-064e
Page 2 of 11
DATA SHEET MMI200-PC/104
1 General description
The MIP200-PC/104 board comprises two measurement channels for data acquisition. It is used as
an interface board for EnDat, SSI or incremental encoders.
A timer is available in all operational modes (i.e. EnDat, SSI, incremental). The timer can be used to
generate a hardware strobe for equidistant data sampling by defining the break interval. The system
is clocked at 33.00 MHz, for EnDat mode preferably at 24.00 MHz.
*
)
The power supply for the encoders (5/12 V, Ground) is supplied on sockets D-SUB9 / D-SUB15.
**
)
The maximum available current is 300 mA.
Figure 1 shows the MIP200-PC/104 board's block diagram connected to an EnDat encoder on
channel X1 and to an incremental encoder on channel X2.
74 ALS 245
D0 ...D15
MMI4832
DATA_DV
SN75176B
D0
D15
/IR6
/RD
/CS
/WR
TCLK
SD0 ...SD15
ispLSI2064
2 x
WR_M
/RS
CS_2
CS_1
RD_M
CS_1
RD_M
Res_M
JP
IOW\, IOR\, RESDRV
CLK
/IR7
MOT
/STR
IOCHRDY
CMD
WR_M
:
SA0 ...SA15
EnDat -
Encoder
CLK+
CLK -
Quartz-
oscillator
/IR61
/IR71
/STR1
IOCS16
DE
DE
/RE
D
SN75176B
DE
/RE
D
+5V
D+
D-
DATA_RC
R
<
>
CMD
CMD
CHA
CHB
CHC
CHD
GND
GND
>
<
<
>
>
>
>
<
<
+5V
MMI4832
DATA_DV
D0
D15
/IR6
/RD
/CS
/WR
TCLK
/RS
CLK
/IR7
MOT
/STR
CMD
:
DE
DATA_RC
CHA
CHB
CHC
CHD
GND
GND
<
<
D0 ...D15
CS_2
RD_M
Res_M
WR_M
CMD
Res_M
40MHz
40MHz
40MHz
>
GND
<
SN75176B
DE
/RE
D
SN75176B
DE
/RE
D
+5V
R
>
>
P
C
/
1
0
4
CLK+
CLK -
D+
D-
>
>
>
>
<
<
<
X2
UWB_in-Modul
X1
CLK+
CLK -
D+
D-
>
>
>
>
<
<
CHA
CHB
X 3,
X4
Optical
coupler
>
<
X9
<
>
>
4
/
4
/
<
UWB_in-Modul
Optical
coupler
<
Register
<
>
incremental
-
encoder
-
Register
CHA
CHB
CHC
Figure 1: Block diagram MMI200-PC/104
*
) Default configuration 33 MHz
**
) Default configuration 5V power supply for encoder
REVISIONS
NO
VERSION
APPROVED
1
1.0
2000-09-18
1
The information in this publication is believed to be accurate in all respects at the time
of publication. MAZeT reserves the right to make changes in its products without notice
in order to improve design or performance characteristics.
DOC. NO:
DB-99-064e
Page 3 of 11
DATA SHEET MMI200-PC/104
2 ISA Interface
The board supports only 16 bit accesses (to even addresses).
Board addresses
The board address setting is done by switches S1.1 .. S1.3 according to Table 1.
S1.3
S1.2
S1.1
Base address
off
off
off
30x
off
off
ON
31x
off
ON
ON
33x
ON
off
off
34x
ON
off
ON
35x
ON
ON
off
36x
Table 1: Board address
Register addresses
The available addressable registers are divided into on-board registers and measurement interface
circuit MMI4832 registers. On-board registers are interrupt enable register, command register,
optical coupler register. They are directly accessible by reading from or writing to the appropriate
address. MMI4832 registers are hidden, meaning that they can be accessed by first writing the
address and then reading or writing the actual data.
Offset address
Function
0x0 (read/write)
Data access MMI4832 (measurement interface IC) channel 1
0x2 (write only)
Address selection MMI4832 (measurement interface IC) channel 1
0x4 (read/write)
Data access MMI4832 (measurement interface IC) channel 2
0x6 (write only)
On-board Interrupt enable register
0x8 (write only)
Software reset
0xA (write only)
Address selection MMI4832 (measurement interface IC) channel 1
0xC (write only)
On-board command register
(analog interpolator, optical coupler outputs)
0xC (read only)
Optical coupler input register
others
reserved
Table 2: Offset addresses
REVISIONS
NO
VERSION
APPROVED
1
1.0
2000-09-18
1
The information in this publication is believed to be accurate in all respects at the time
of publication. MAZeT reserves the right to make changes in its products without notice
in order to improve design or performance characteristics.
DOC. NO:
DB-99-064e
Page 4 of 11
DATA SHEET MMI200-PC/104
3 Register description
3.1 On-board command register
This register holds the settings of the analog interpolation coefficient and the control of four optical
coupler outputs.
analog interpolation coefficient
optical coupler outputs
D(7)
D(6)
D(5)
D(4)
D(3)
O_OPTO4
D(2)
O_OPTO3
D(1)
O_OPTO2
D(0)
O_OPTO1
The (optional) MIP200's interpolation coefficient is set and modified by bits D(7) to D(4). According
to Table 3 every channel has its own interpolation coefficient. Refer to chap. 4 for a detailed
description of the optical coupler signals.
analog
interpolation
coefficient
D(7)
channel 2
D(6)
channel 2
D(5)
channel 1
D(4)
channel 1
5
0
0
0
0
10
0
1
0
1
25
1
0
1
0
50
1
1
1
1
Table 3: Selecting the interpolation coefficient of MIP200
3.2 Optical coupler input register
This register holds the current status of the two coupler inputs I_OPTO5 and I_OPTO6. The other
coupler inputs can be polled via the MMI4832 internal status register.
D(3)
D(2)
---
O_OPTO6
O_OPTO5
3.3 On-board interrupt enable register
Two interrupt levels can be selected by writing this register (1=enable, 0=disable) as a board
interrupt. Valid interrupts are IRQ10 and 11.
D(2)
D(1)
D(0)
---
IRQ11
IRQ10
REVISIONS
NO
VERSION
APPROVED
1
1.0
2000-09-18
1
The information in this publication is believed to be accurate in all respects at the time
of publication. MAZeT reserves the right to make changes in its products without notice
in order to improve design or performance characteristics.
DOC. NO:
DB-99-064e
Page 5 of 11
DATA SHEET MMI200-PC/104
3.4 MMI4832 registers
Internal MMI4832 registers are accessed by first writing the register address to the offset address
0x2 (channel 1) or 0xA (channel 2). After that only the internal register can be read or written to via
the offset address 0x0 (channel 1) or 0x4 (channel 2).
Table 4 contains the bit mapping of MMI4832's internal address register.
D7
D6
D5
D4
D3
D2
D1
D0
---
M16
AINC
address
A4
address
A3
address
A2
address
A1
address
A0
Table 4: Internal address register
M16 = 1
16 bit accesses (this board only supports 16 bit accesses)
AINC = 1
Autoincrement addressing mode. The base address of an internal register is written to A(4:2). The
access is repeated n times, where n is the number of words.
A(4:2)
/WR-,
/RD-
access
Register
Write 16 bit port
Read 16 bit port
Transmit register
Write Transmit register
Read Transmit register
0
1
Write D(0:15)
Read D(0:15)
2
Write D(16:31)
Read D(16:31)
2
2
Receive register
Latching the value of the Serial-
Parallel converters
Read Receive register,
Strobe-RG
1
1
into the Receive register
Read D(0:15)
2
---
Read D(16:31)
3
---
Read D(32:47)
1
1 - 3 **
2
--
-
---
---
Reference / Offset
register
Write Ref./Offset register
Read Receive register +
Offset
3
1
Write D(0:15)
Read D(0:15)
2
Write D(16:31)
Read D(16:31)
2
2
Control register
Write control register
Read control register
4
1
Write D(0:15)
Read D(0:15)
2
Write D(16:31)
Read D(16:31)
2
2
Status register
Software strobe
Read Status register with reset
5
1
---
Read D(0:7)
1
1
Interrupt mask
register
Write Interrupt mask register
Read Interrupt mask register
6
1
Write D(0:7)
Read D(0:7)
1
1
Timer register
Write Timer register
Read Status register without reset
7
1
Write D(0:15)
Read D(0:7)
1
1
Table 5: Parallel port mode "Intel": autoincrement (MOT = "0", AINC = "1")
**
The number of necessary accesses is determined by the data width set in control register (bits 24:29)
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