FEATURES

128K x 16 organization(MX27C2048, JEDEC pin out)

256K x 8 or 128K x 16 organization(MX27C2100,

ROM pin out compatible)

+12.5V programming voltage

Fast access time: 55/70/90/120/150 ns

Totally static operation

Completely TTL compatible

Operating current: 40mA

Standby current: 100uA

Package type:
- 40 pin plastic DIP
- 44 pin PLCC(MX27C2048)

GENERAL DESCRIPTION

The MX27C2100/2048 is a 5V only, 2M-bit, One Time
Programmable Read Only Memory. It is organized as
128K words by 16 bits per word(MX27C2048), 256K x 8
or 128K x 16(MX27C2100), operates from a single + 5
volt supply, has a static standby mode, and features fast
single address location programming. All programming
signals are TTL levels, requiring a single pulse. For

P/N: PM0158

REV. 4.5, JAN. 14, 2003

programming outside from the system, existing EPROM
programmers may be used. The MX27C2100/2048
supports a intelligent fast programming algorithm which
can result in programming times of less than one minute.

This EPROM is packaged in industry standard 40 pin
dual-in-line package and 44 lead PLCC package.

PIN CONFIGURATIONS

PDIP(MX27C2048)

BLOCK DIAGRAM (MX27C2048)

PLCC(MX27C2048)

MX27C2100/27C2048

2M-BIT [256Kx8/128x16] CMOS EPROM

MX27C2048

VPP

Q15

Q14

Q13

Q12

Q11

Q10

GND

VCC

PGM

A16

A15

A14

A13

A12

A11

A10

GND

MX27C2048

Q12

Q11

Q10

GND

A13

A12

A11

A10

GND

Q13

Q14

Q15

VPP

VCC

PGM

A16

A15

A14

18 23

CONTROL

LOGIC

OUTPUT

BUFFERS

Q0~Q15

PGM

A0~A16

ADDRESS

INPUTS

Y-DECODER

X-DECODER

Y-SELECT

2M BIT

CELL

MAXTRIX

VCC

VSS

VPP

PIN DESCRIPTION(MX27C2048)

SYMBOL

PIN NAME

A0~A16

Address Input

Q0~Q15

Data Input/Output

Chip Enable Input

Output Enable Input

PGM

Program Enable Input

VPP

Program Supply Voltage

VCC

Power Supply Pin (+5V)

GND

Ground Pin

MX27C2100/27C2048

P/N: PM0158

REV. 4.5, JAN. 14, 2003

PIN CONFIGURATIONS

PDIP(MX27C2100)

BLOCK DIAGRAM (MX27C2100)

SYMBOL

PIN NAME

A0~A16

Address Input

Q0~Q14

Data Input/Output

Chip Enable Input

Output Enable Input

BYTE/VPP

Word/Byte Selection

/Program Supply Voltage

Q15/A-1

Q15(Word mode)/LSB addr. (Byte mode)

VCC

Power Supply Pin (+5V)

GND

Ground Pin

PIN DESCRIPTION(MX27C2100)

TRUTH TABLE OF BYTE FUNCTION(MX27C2100)

BYTE MODE(BYTE = GND)

Q15/A-1

MODE

Q0-Q7

SUPPLY CURRENT

Non selected

High Z

Standby(ICC2)

Non selected

High Z

Operating(ICC1)

A-1 input

Selected

DOUT

Operating(ICC1)

WORD MODE(BYTE = VCC)

Q15/A-1

MODE

Q0-Q14

SUPPLY CURRENT

High Z

Non selected

High Z

Standby(ICC2)

High Z

Non selected

High Z

Operating(ICC1)

DOUT

Selected

DOUT

Operating(ICC1)

NOTE : X = H or L

MX27C2100

GND

Q10

Q11

A10

A11

A12

A13

A14

A15

A16

BYTE/VPP

GND

Q15/A-1

Q14

Q13

Q12

VCC

CONTROL

LOGIC

OUTPUT

BUFFERS

Q0~Q14

Q15/A-1

BYTE/VPP

A0~A16

ADDRESS

INPUTS

Y-DECODER

X-DECODER

Y-SELECT

2M BIT

CELL

MAXTRIX

VCC

GND

MX27C2100/27C2048

P/N: PM0158

REV. 4.5, JAN. 14, 2003

FUNCTIONAL DESCRIPTION

THE PROGRAMMING OF THE MX27C2100/2048

When the MX27C2100/2048 is delivered, or it is
erased, the chip has all 2M bits in the "ONE", or HIGH
state. "ZEROs" are loaded into the MX27C2100/2048
through the procedure of programming.

For programming, the data to be programmed is applied
with 16 bits in parallel to the data pins.

VCC must be applied simultaneously or before VPP, and
removed simultaneously or after VPP. When
programming an MXIC EPROM, a 0.1uF capacitor is
required across VPP and ground to suppress spurious
voltage transients which may damage the device.

FAST PROGRAMMING

The device is set up in the fast programming mode when
the programming voltage VPP = 12.75V is applied, with
VCC = 6.25 V and PGM = VIL(or OE = VIH) (Algorithm
is shown in Figure 1). The programming is achieved by
applying a single TTL low level 100us pulse to the PGM
input after addresses and data line are stable. If the data
is not verified, an additional pulse is applied for a
maximum of 25 pulses. This process is repeated while
sequencing through each address of the device. When
the programming mode is completed, the data in all
address is verified at VCC = VPP = 5V

10%.

PROGRAM INHIBIT MODE

Programming of multiple MX27C2100/2048's in parallel
with different data is also easily accomplished by using
the Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX27C2100/2048 may be
common. A TTL low-level program pulse applied to an
MX27C2100/2048 CE input with VPP = 12.5

0.5 V will

program the MX27C2100/2048. A high-level CE input
inhibits the other MX27C2100/2048s from being
programmed.

PROGRAM VERIFY MODE

Verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verification should be performed with OE and CE at

VIL(for MX27C2048), OE at VIL, CE at VIH(for
MX27C2100) and VPP at its programming voltage.

AUTO IDENTIFY MODE

The auto identify mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and device type. This mode is intended for use by
programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25

C ambient

temperature range that is required when programming
the MX27C2100/2048.

To activate this mode, the programming equipment
must force 12.0

0.5 V on address line A9 of the device.

Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL to
VIH. All other address lines must be held at VIL during
auto identify mode.

Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For the
MX27C2100/2048, these two identifier bytes are given
in the Mode Select Table. All identifiers for manufacturer
and device codes will possess odd parity, with the MSB
(Q15) defined as the parity bit.

READ MODE

The MX27C2100/2048 has two control functions, both
of which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE's, assuming that CE has been LOW and
addresses have been stable for at least tACC - t OE.

WORD-WIDE MODE

With BYTE/VPP at VCC ± 0.2V outputs Q0-7 present
data Q0-7 and outputs Q8-15 present data Q8-15, after
CE and OE are appropriately enabled.

MX27C2100/27C2048

P/N: PM0158

REV. 4.5, JAN. 14, 2003

BYTE-WIDE MODE

With BYTE/VPP at GND

0.2V, outputs Q8-15 are tri-

stated. If Q15/A-1 = VIH, outputs Q0-7 present data bits
Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits
Q0-7.

STANDBY MODE

The MX27C2100/2048 has a CMOS standby mode
which reduces the maximum VCC current to 100 uA. It
is placed in CMOS standby when CE is at VCC

0.3 V.

The MX27C2100/2048 also has a TTL-standby mode
which reduces the maximum VCC current to 1.5 mA. It
is placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a two-
line control function is provided to allow for:

1. Low memory power dissipation,
2. Assurance that output bus contention will not
occur.

It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.

SYSTEM CONSIDERATIONS

During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
output capacitance loading of the device. At a minimum,
a 0.1 uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
Vcc and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be
used between VCC and GND for each eight devices.

The location of the capacitor should be close to where
the power supply is connected to the array.

MX27C2100/27C2048

P/N: PM0158

REV. 4.5, JAN. 14, 2003

MODE SELECT TABLE (MX27C2100)

BYTE/

MODE

Q15/A-1

VPP(5)

Q8-14

Q0-7

Read (Word)

VIL

Q15 Out

VCC

Q8-14 Out

Q0-7 Out

Read (Upper Byte)

VIL

VIH

GND

High Z

Q8-15 Out

Read (Lower Byte)

VIL

GND

High Z

Q0-7 Out

Output Disable

VIL

VIH

High Z

Standby

VIH

High Z

Program

VIL

VIH

Q15 In

VPP

Q8-14 In

Q0-7 In

Program Verify

VIH

VIL

Q15 Out

VPP

Q8-14 Out

Q0-7 Out

Program Inhibit

VIH

High Z

VPP

High Z

Manufacturer Code(3)

VIL

VCC

00H

C2H

Device Code(3)

VIL

VIH

VCC

01H

8AH

NOTES: 1. VH = 12.0 V

0.5 V

2. X = Either VIH or VIL

3. A1 - A8 = A10 - A16 = VIL(For auto select)
4. See DC Programming Characteristics for VPP voltage during

programming.

NOTES: 1. VH = 12.0V

0.5V

2. X = Either VIH or VIL.
3. A1 - A8, A10 - A16 = VIL(For auto select)

4. See DC Programming Characteristics for VPP voltages.
5. BYTE/VPP is intended for operation under DC Voltage

conditions only.

MODE SELECT TABLE (MX27C2048)

PINS

MODE

PGM

VPP

OUTPUTS

Read

VIL

VIH

VCC

DOUT

Output Disable

VIL

VIH

VCC

High Z

Standby (TTL)

VIH

VCC

High Z

Standby (CMOS)

VCC

0.3V

VCC

High Z

Program

VIL

VIH

VIL

VPP

DIN

Program Verify

VIL

VIH

VPP

DOUT

Program Inhibit

VIH

VPP

High Z

Manufacturer Code(3)

VIL

VCC

00C2H

Device Code(3)

VIL

VIH

VCC

0122H

MX27C2100/27C2048

P/N: PM0158

REV. 4.5, JAN. 14, 2003

DC CHARACTERISTICS

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

CONDITIONS

VOH

Output High Voltage

2.4

IOH = -0.4mA

VOL

Output Low Voltage

0.4

IOL = 2.1mA

VIH

Input High Voltage

2.0

VCC + 0.5

VIL

Input Low Voltage

-0.3

0.8

ILI

Input Leakage Current

-10

VIN = 0 to 5.5V

ILO

Output Leakage Current

-10

VOUT = 0 to 5.5V

ICC3

VCC Power-Down Current

100

CE = VCC

0.3V

ICC2

VCC Standby Current

1.5

CE = VIH

ICC1

VCC Active Current

CE = VIL, f=5MHz, Iout = 0mA

IPP

VPP Supply Current Read

CE = OE = VIL, VPP = 5.5V

NOTICE:
Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended period may affect reliability.

NOTICE:
Specifications contained within the following tables are subject to
change.

DC/AC Operating Conditions for Read Operation

CAPACITANCE

TA = 25

C, f = 1.0 MHz (Sampled only)

SYMBOL

PARAMETER

TYP.

MAX.

UNIT

CONDITIONS

CIN

Input Capacitance

VIN = 0V

COUT

Output Capacitance

VOUT = 0V

CVPP

VPP Capacitance

VPP = 0V

MX27C2048

MX27C2100/2048

-55

-70

-90

-12

-15

Operating Temperature

Commercial

C to 70

Vcc Power Supply

10%

ABSOLUTE MAXIMUM RATINGS

RATING

VALUE

Ambient Operating Temperature

C to 70

Storage Temperature

-65

C to 125

Applied Input Voltage

-0.5V to 7.0V

Applied Output Voltage

-0.5V to VCC + 0.5V

VCC to Ground Potential

-0.5V to 7.0V

A9 & Vpp

-0.5V to 13.5V

MX27C2100/27C2048

P/N: PM0158

REV. 4.5, JAN. 14, 2003

AC CHARACTERISTICS

2100/2048-55

2100/2048-70

2100/2048-90

SYMBOL

PARAMETER

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

UNIT

CONDITIONS

tACC

Address to Output Delay

CE = OE = VIL

tCE

Chip Enable to Output Delay

OE = VIL

tOE

Output Enable to Output Delay

CE = VIL

tDF

OE High to Output Float,

or CE High to Output Float

tOH

Output Hold from Address,

CE or OE which ever occurred first

AC CHARACTERISTICS

2100/2048-12

2100/2048-15

SYMBOL PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT

CONDITIONS

tACC

Address to Output Delay

120

150

CE = OE = VIL

tCE

Chip Enable to Output Delay

120

150

OE = VIL

tOE

Output Enable to Output Delay

CE = VIL

tDF

OE High to Output Float,

or CE High to Output Float

tOH

Output Hold from Address,

CE or OE which ever occurred first

AC CHARACTERISTICS

27C2100-70

27C2100-90

27C2100-12

27C2100-15

SYMBOL PARAMETER

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

UNIT

tBHA

BYTE Access Time

120

150

tOHB

BYTE Output Hold Time

tBHZ

BYTE Output Delay Time

tBLZ

BYTE Output Set Time

MX27C2100/27C2048

P/N: PM0158

REV. 4.5, JAN. 14, 2003

AC PROGRAMMING CHARACTERISTICS

TA = 25

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

CONDITIONS

tAS

Address Setup Time

2.0

tOES

OE Setup Time

2.0

tDS

Data Setup Time

2.0

tAH

Address Hold Time

tDH

Data Hold Time

2.0

tDFP

Out put Enable to Output Float Delay

130

tVPS

VPP Setup Time

2.0

tPW

PGM Program Pulse Width

105

tVCS

VCC Setup Time

2.0

tCES

CE Setup Time

2.0

tOE

Data valid from OE

150

DC PROGRAMMING CHARACTERISTICS

TA = 25

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

CONDITIONS

VOH

Output High Voltage

2.4

IOH = -0.40mA

VOL

Output Low Voltage

0.4

IOL = 2.1mA

VIH

Input High Voltage

2.0

VCC + 0.5

VIL

Input Low Voltage

-0.3

0.8

ILI

Input Leakage Current

-10

VIN = 0 to 5.5V

A9 Auto Select Voltage

11.5

12.5

ICC3

VCC Supply Current (Program & Verify)

IPP2

VPP Supply Current(Program)

CE = VIL, OE = VIH

VCC1

Fast Programming Supply Voltage

6.00

6.50

VPP1

Fast Programming Voltage

12.5

13.0

MX27C2100/27C2048

P/N: PM0158

REV. 4.5, JAN. 14, 2003

PLASTIC PACKAGE

PART NO.

ACCESS TIME

OPERATING CURRENT

STANDBY CURRENT

PACKAGE

(ns)

MAX.(mA)

MAX.(uA)

MX27C2100PC-70

100

40 Pin DIP(ROM pin out)

MX27C2100PC-90

100

40 Pin DIP(ROM pin out)

MX27C2100PC-12

120

100

40 Pin DIP(ROM pin out)

MX27C2100PC-15

150

100

40 Pin DIP(ROM pin out)

MX27C2048PC-55

100

40 Pin DIP(JEDEC pin out)

MX27C2048PC-70

100

40 Pin DIP(JEDEC pin out)

MX27C2048PC-90

100

40 Pin DIP(JEDEC pin out)

MX27C2048PC-12

120

100

40 Pin DIP(JEDEC pin out)

MX27C2048PC-15

150

100

40 Pin DIP(JEDEC pin out)

MX27C2048QC-55

100

44 Pin PLCC

MX27C2048QC-70

100

44 Pin PLCC

MX27C2048QC-90

100

44 Pin PLCC

MX27C2048QC-12

120

100

44 Pin PLCC

MX27C2048QC-15

150

100

44 Pin PLCC

ORDERING INFORMATION

MX27C2100/27C2048

P/N: PM0158

REV. 4.5, JAN. 14, 2003

REVISION HISTORY

Revision No. Description

Page

Date

3.0

SWITCHING TEST WAVEFORMS: For 90/120/150ns, the AC

10/23/1996

driving level are revised from 2.4V/0.4V to 3.0V/0V.

4.0

1)Eliminate Interactive Programming Mode.

6/13/1997

2)40-CDIP package quartz len, change to square shape.

4.1

IPP : 100uA----> 10uA

8/8/1997

4.2

Cancel Ceramic DIP package type

P1,2,3,13,14 MAR/01/2000

4.3

Cancel "Ultraviolet Erasable" wording in General Description

AUG/22/2001

To modify Package Information

P14~16

4.4

To modify Package Information

P14~16

NOV/19/2002

4.5

1. To remove 10 x 14mm 40-TSOP package type.

P1,13,16

JAN/14/2003

2. To modify 40-PDIP package information

P14

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 27C2048

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 27C2048